Supermicro X11SPG-TF operation manual

X11SPG-TF

USER'S MANUAL

Revision 1.1

The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes

!

no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update
or to keep current the information in this manual, or to notify any person or organization of the updates. Please Note:

For the most up-to-date version of this manual, please see our website at www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product described in this manual
at any time and without notice. This product, including software and documentation, is the property of Supermicro and/
or its licensors, and is supplied only under a license. Any use or reproduction of this product is not allowed, except
as expressly permitted by the terms of said license.

IN NO EVENT WILL Super Micro Computer, Inc. BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL,
SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT
OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER
MICRO COMPUTER, INC. SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED
OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara County in the
State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution
of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.

FCC Statement: This equipment has been tested and found to comply with the limits for a Class B digital device
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can
radiate radio frequency energy and, if not installed and used in accordance with the manufacturer’s instruction manual,
may cause harmful interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your own expense.

California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate warning applies only
to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate Material-special handling may apply.
See www.dtsc.ca.gov/hazardouswaste/perchlorate”.

WARNING: This product can expose you to chemicals including
lead, known to the State of California to cause cancer and birth
defects or other reproductive harm. For more information, go
to www.P65Warnings.ca.gov.

The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment,
nuclear facilities or systems, aircraft, aircraft devices, aircraft/emergency communication devices or other critical

systems whose failure to perform be reasonably expected to result in signicant injury or loss of life or catastrophic

property damage. Accordingly, Supermicro disclaims any and all liability, and should buyer use or sell such products
for use in such ultra-hazardous applications, it does so entirely at its own risk. Furthermore, buyer agrees to fully
indemnify, defend and hold Supermicro harmless for and against any and all claims, demands, actions, litigation, and
proceedings of any kind arising out of or related to such ultra-hazardous use or sale.

Manual Revision 1.1

Release Date: March 28, 2019

Unless you request and receive written permission from Super Micro Computer, Inc., you may not copy any part of this

document. Information in this document is subject to change without notice. Other products and companies referred

to herein are trademarks or registered trademarks of their respective companies or mark holders.

Copyright © 2019 by Super Micro Computer, Inc.
All rights reserved.

Printed in the United States of America

Preface

Preface

About This Manual

This manual is written for system integrators, IT technicians and knowledgeable end users.
It provides information for the installation and use of the X11SPG-TF motherboard.

About This Motherboard

The Supermicro X11SPG-TF supports an Intel® Xeon 81xx/61xx/51xx/41xx/31xx and
82xx/62xx/52xx/42xx/32xx series (Socket P0-LGA 3647) processor with a thermal design
power (TDP) of up to 205W. Built with the Intel C621 chipset, the X11SPG-TF includes three

PCI-E slots for GPU and AOC support and o󰀨ers such features as SATA 3.0, dual 10GbE

LAN, USB ports, and a built-in PCIe storage solution enhancement via Intel VROC. This
motherboard supports 6-channel, 6-DIMM DDR4 ECC RDIMM/LRDIMM memory with speeds
of up to 2933MHz. The X11SPG-TF is the ideal solution for GPU server platforms that address
the needs of next generation computing. Please note that this motherboard is intended to
be installed and serviced by professional technicians only. For processor/memory updates,
please refer to our website at http://www.supermicro.com/products/.

Note 1: 2933MHz memory is supported by the 82xx/62xx series processors.

Note 2: Intel VROC requires a separate hardware key to enable.

Conventions Used in the Manual

Warning! Indicates important information given to prevent equipment/property damage

or personal injury.

Warning! Indicates high voltage may be encountered while performing a procedure.

Important: Important information given to ensure proper system installation or to

relay safety precautions.

Note: Additional Information given to di󰀨erentiate various models or provides infor-
mation for proper system setup.

3

Super X11SPG-TF User's Manual

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Ave.

San Jose, CA 95131 U.S.A.

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

Website: www.supermicro.com

Europe

Address: Super Micro Computer B.V.

Het Sterrenbeeld 28, 5215 ML

's-Hertogenbosch, The Netherlands

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

[e-mail] (Customer Support)

Website: www.supermicro.nl

Asia-Pacic

Address: Super Micro Computer, Inc.

3F, No. 150, Jian 1st Rd.

Zhonghe Dist., New Taipei City 235

Taiwan (R.O.C)

Tel: [phone]

Fax: [phone]

Email: [e-mail]

Website: www.supermicro.com.tw

4

Preface

Table of Contents

Chapter 1 Introduction

1.1 Checklist ...............................................................................................................................8

Quick Reference ...............................................................................................................11

Quick Reference Table ......................................................................................................12

Motherboard Features .......................................................................................................14

1.2 Processor and Chipset Overview .......................................................................................18

1.3 Special Features ................................................................................................................19

Recovery from AC Power Loss .........................................................................................19

1.4 System Health Monitoring ..................................................................................................19

Onboard Voltage Monitors ................................................................................................19

Fan Status Monitor with Firmware Control .......................................................................19

Environmental Temperature Control .................................................................................19

System Resource Alert......................................................................................................19

1.5 ACPI Features ....................................................................................................................20

1.6 Power Supply .....................................................................................................................20

1.7 Serial Port ...........................................................................................................................20

Chapter 2 Installation

2.1 Static-Sensitive Devices .....................................................................................................21

Precautions .......................................................................................................................21

Unpacking .........................................................................................................................21

2.2 Processor and Heatsink Installation ...................................................................................22

The Intel Xeon 81xx/61xx/51xx/41xx/31xx and 82xx/62xx/52xx/42xx/32xx Series

Processor ..........................................................................................................................22

Overview of the Processor Carrier Assembly ...................................................................23

Overview of the CPU Socket ............................................................................................23

Overview of the Processor Heatsink Module ....................................................................24

Creating the Non-F Model Processor Carrier Assembly...................................................25

Assembling the Processor Heatsink Module ....................................................................26

Preparing the CPU Socket for Installation ........................................................................27

Installing the Processor Heatsink Module .........................................................................28

Removing the Processor Heatsink Module .......................................................................29

2.3 Motherboard Installation .....................................................................................................30

5

Super X11SPG-TF User's Manual

Tools Needed ....................................................................................................................30

Location of Mounting Holes ..............................................................................................30

Installing the Motherboard.................................................................................................31

2.4 Memory Support and Installation .......................................................................................32

Memory Support ................................................................................................................32

DDR4 Memory Support for 81xx/61xx/51xx/41xx/31xx Platform ......................................32

DDR4 Memory Support for 82xx/62xx/52xx/42xx/32xx Platform ......................................33

General Guidelines for Optimizing Memory Performance .............................................. 34

DIMM Installation ..............................................................................................................35

DIMM Removal .................................................................................................................35

2.5 Rear I/O Ports ....................................................................................................................36

2.6 Front Control Panel ............................................................................................................40

2.7 Connectors .........................................................................................................................45

Power Connections ...........................................................................................................45

Headers .............................................................................................................................46

2.8 Jumper Settings .................................................................................................................55

How Jumpers Work ...........................................................................................................55

2.9 LED Indicators ....................................................................................................................58

Chapter 3 Troubleshooting

3.1 Troubleshooting Procedures ..............................................................................................61

Before Power On ..............................................................................................................61

No Power ..........................................................................................................................61

No Video ...........................................................................................................................62

System Boot Failure .......................................................................................................62

Memory Errors ..................................................................................................................62

Losing the System's Setup Conguration .........................................................................63

When the System Becomes Unstable ..............................................................................63

3.2 Technical Support Procedures ...........................................................................................65

3.3 Frequently Asked Questions ..............................................................................................66

3.4 Battery Removal and Installation .......................................................................................67

Battery Removal ................................................................................................................67

Proper Battery Disposal ....................................................................................................67

6

Preface

Battery Installation .............................................................................................................67

3.5 Returning Merchandise for Service ....................................................................................68

Chapter 4 UEFI BIOS

4.1 Introduction .........................................................................................................................69

4.2 Main Setup .........................................................................................................................70

4.3 Advanced Setup Congurations .........................................................................................72

4.4 Event Logs .........................................................................................................................99

4.5 IPMI ..................................................................................................................................101

4.6 Security .............................................................................................................................104

4.7 Boot .................................................................................................................................108

4.8 Save & Exit .......................................................................................................................111

Appendix A UEFI BIOS Codes

Appendix B Software Installation

B.1 Installing Software Programs ...........................................................................................11 5

B.2 SuperDoctor® 5 .................................................................................................................116

Appendix C Standardized Warning Statements

Battery Handling ..............................................................................................................117

Product Disposal .............................................................................................................119

Appendix D UEFI BIOS Recovery

7

Super X11SPG-TF User's Manual

Chapter 1

Introduction

Congratulations on purchasing your computer motherboard from an industry leader.
Supermicro motherboards are designed to provide you with the highest standards in quality
and performance.

In additon to the motherboard, several important parts that are included in the retail box are
listed below. If anything listed is damaged or missing, please contact your retailer.

1.1 Checklist

Main Parts List

Description Part Number Quantity

Supermicro Motherboard X11SPG-TF 1

SATA Cables CBL-0044L 6

Quick Reference Guide MNL-1965-QRG 1

Important Links

For your system to work properly, please follow the links below to download all necessary
drivers/utilities and the user’s manual for your server.

• Supermicro product manuals: http://www.supermicro.com/support/manuals/

• Product drivers and utilities: https://www.supermicro.com/wftp/driver/

• Product safety info: http://www.supermicro.com/about/policies/safety_information.cfm

• If you have any questions, please contact our support team at: [e-mail]

This manual may be periodically updated without notice. Please check the Supermicro website

for possible updates to the manual revision level.

8

Figure 1-1. X11SPG-TF Motherboard Image

Chapter 1: Introduction

Note: All graphics shown in this manual were based upon the latest PCB revision
available at the time of publication of the manual. The motherboard you received may
or may not look exactly the same as the graphics shown in this manual.

9

Super X11SPG-TF User's Manual

Figure 1-2. X11SPG-TF Motherboard Layout

(not drawn to scale)

USB1

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

VGA

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

DESIGNED IN USA

+

BT1

JSD2

JSD1

S-SATA0

S-SATA1

Aspeed

AST2500

JPG1

REV: 1.01

X11SPG-TF

C621

Intel

JPTG1

JWD1

JBT1

USB0

JPCK1

JD1

JP2

JPME2

M.2-H_1 PCI-E 3.0 X4

JP1

CPU

LAN2

LAN1

Intel

X550

MH12

MH10

M.2-H_2 PCI-E 3.0 X4

IPMI_LAN

USB4/5(3.0)

JIPMB1

USB6/7(3.0)

JP4

USB2/3

+

SP1

USB8(3.0)

LE3
LE4

SXB2A

SXB2B PCI-E 3.0 X16

JP3

JTPM1

JNVI2C1

FANC

FAND

ON

JPWR5

JPI2C1

DIMMF1

FAN4

DIMME1

DIMMD1

FAN3

SAN MAC

IPMI CODE

MAC CODE

BIOS LICENSE

DIMMA1

FAN2

BAR CODE

DIMMC1

DIMMB1

FAN1

JL1

JF1

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

Note: Components not documented are for internal testing only.

10

JRK1

JOH1

JPWR6

Quick Reference

JPI2C1

Chapter 1: Introduction

COM2

SXB1A

SLOT3

LEDM1

JPG1

JSTBY1

JD1

JWD1

JPME2

SXB1B

BT1
JSD2
JSD1

I-SATA4

I-SATA5
S-SATA0
S-SATA1

I-SATA6

I-SATA7

JBT1

S-SGPIO1

I-SGPIO2

FANA
FANB

DIMMD1

DIMME1

DIMMF1

DIMMC1

DIMMB1

DIMMA1

JPWR5

JPI2C1

JUIDB1

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

VGA

LE1

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

DESIGNED IN USA

+

BT1

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

JPTG1

VGA

Aspeed

AST2500

JPG1

REV: 1.01

X11SPG-TF

DIMMD1

SAN MAC

USB1

USB1

JPTG1

JWD1

Intel
C621

JBT1

USB0

USB0

JPCK1

JD1

JPME2

JP1

CPU

IPMI CODE

MAC CODE

JP2

LAN2

LAN1

LAN2

LAN1

Intel

X550

MH12

MH10

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

IPMI_LAN

USB4/5 (3.0)

SXB2A

IPMI_LAN

USB4/5(3.0)

USB2/3

+

JIPMB1

SP1

USB6/7(3.0)

JP4

USB8(3.0)

LE3
LE4

BIOS LICENSE

DIMMC1

DIMMB1

DIMMA1

FAN2

FAN1

SXB2B PCI-E 3.0 X16

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

JPWR6

JL1

SXB2A

USB2/3
MH10

MH12

JIPMB1

SP1

USB6/7 (3.0)

SXB2B

USB8 (3.0)

LE3
LE4

M.2-H_2 PCI-E 3.0 x4
M.2-H_1 PCI-E 3.0 x4

JTPM1

JNVI2C1

CPU

JRK1

FANC

FAND

JOH1

JF1

LE2

JPWR6
JL1

FAN4 FAN3

FAN2 FAN1

Notes:

• See Chapter 2 for detailed information on jumpers, I/O ports, and JF1 front panel con-

nections.

• " " indicates the location of Pin 1.

• Jumpers/LED indicators not indicated are used for testing only.

• Use only the correct type of onboard CMOS battery as specied by the manufacturer. Do

not install the onboard battery upside down to avoid possible explosion.

11

Super X11SPG-TF User's Manual

Quick Reference Table

Jumper Description Default Setting

JBT1 CMOS Clear Open (Normal)

JPG1 VGA Enable/Disable Pins 1-2 (Enabled)

JPME2 ME Manufacturing Mode Pins 1-2 (Normal)

JPTG1 LAN Enable/Disable Pins 1-2 (Enabled)

JWD1 Watchdog Timer Pins 1-2 (Reset)

LED Description Status

LE1 Unit Identier (UID) LED Solid Blue: Unit Identied

LE2 Onboard Power LED Solid Green: Power On

LE3, LE4 M.2 LED Blinking Green: Device Working

LEDM1 BMC Heartbeat LED Blinking Green: BMC Normal

Connector Description

BT1 Onboard Battery

COM2 COM Header

FAN1 ~ FAN4 CPU/System Fan Headers

FANA ~ FAND GPU Fan Headers

IPMI_LAN Dedicated IPMI LAN Port

I-SATA4 ~ I-SATA7 Intel® PCH SATA 3.0 Ports (with RAID 0, 1, 5, 10)

I-SGPIO2, S-SGPIO1

JD1 Speaker/Power LED Indicator (Pins 1-3: Power LED, Pins 4-7: Speaker)

JF1 Front Control Panel Header

JIPMB1 4-pin BMC External I2C Header (for an IPMI card)

JL1 Chassis Intrusion Header

JNVI2C1 NVMe I2C Header

JOH1 Overheat LED Indicator

JPI2C1 Power I2C System Management Bus (SMB) Header

JPWR5 20-pin Main Power Connector

JPWR6 8-pin Power Connector for GPU

JRK1 Intel RAID Key Header

JSD1, JSD2 SATA DOM Power Connectors

JSTBY1 Standby Power Header

JTPM1 Trusted Platform Module/Port 80 Connector

JUIDB1 Unit Identier (UID) Switch

LAN1, LAN2

M.2-H_1, M.2-H_2 Dual M.2 PCI-E 3.0 x4 or SATA 3.0 Slots (Supports M-Key 2280)

Serial Link General Purpose I/O Connection Headers (I-SGPIO: SATA use; S-SGPIO: sSATA

use)

10GbE LAN Ports

Note: Table is continued on the next page.

12

Connector Description

MH10, MH12 M.2 Mounting Holes

SLOT3 Middle CPU PCI-E 3.0 x16 Slot

SP1 Internal Speaker/Buzzer

S-SATA0, S-SATA1 SATA 3.0 Ports with SATA DOM Power

SXB1A, SXB1B Left PCI-E 3.0 x16 GPU Slot

SXB2A, SXB2B Right PCI-E 3.0 x16 GPU Slot

USB0, USB1 Back Panel Universal Serial Bus (USB) 2.0 Ports

USB2/3 Front Accessible USB 2.0 Header

USB4/5 Back Panel USB 3.0 Ports

USB6/7 Front Accessible USB 3.0 Header

USB8 USB 3.0 Type-A Header

VGA VGA Port

Chapter 1: Introduction

13

Super X11SPG-TF User's Manual

Motherboard Features

Motherboard Features

CPU

• Supports an Intel® Xeon 81xx/61xx/51xx/41xx/31xx and 82xx/62xx/52xx/42xx/32xx series (Socket P0-LGA3647)

processor with a thermal design power (TDP) of up to 205W and 28 cores

Note: The X11SPG-TF motherboard does not support FPGA or Fabric processors.

Memory

• Up to 384GB of RDIMM, 768GB of LRDIMM, and 1.5TB of 3DS LRDIMM DDR4 (288-pin) ECC memory with speeds of

up to 2933MHz in six memory slots

Note 1: Memory speed support depends on the processors used in the system.

Note 2: 2933MHz memory is supported by the 82xx/62xx series processors only.

DIMM Size

• Up to 256GB at 1.2V

Note 1: Memory capacity and frequency is CPU dependent.

Note 2: For the latest CPU/memory updates, please refer to our website at http://www.supermicro.com/products/

motherboard.

Chipset

• Intel C621

Expansion Slots

• Three (3) PCI-Express 3.0 x16 Slots (CPU Slot 3, SXB1A/SXB1B Slot, SXB2A/SXB2B Slot)

• Two (2) M.2 for PCI-Express 3.0 x4 or SATA 3.0 Slot (Supports M-Key 2280)

Network

• Intel Ethernet Controller X550 for 10G BASE-T Ports

• One (1) Dedicated IPMI LAN located on the rear I/O panel

Baseboard Management Controller (BMC)

• ASpeed AST2500 BMC

Graphics

• Graphics controller via ASpeed AST2500 BMC

Note: The table above is continued on the next page.

14

Chapter 1: Introduction

Motherboard Features

I/O Devices

• Serial (COM) Port • One (1) front accessible serial port header (COM2)

• SATA 3.0

• Video (VGA) Port • One (1) VGA connection on the rear I/O panel

Peripheral Devices

• Two (2) USB 2.0 ports on the rear I/O panel (USB0, USB1)

• Two (2) USB 3.0 ports on the rear I/O panel (USB4/5)

• One (1) front accessible USB 2.0 header with two (2) USB connections (USB2/3)

• One (1) front accessible USB 3.0 header with two (2) USB connections (USB6/7)

• One (1) USB 3.0 Type-A header (USB8)

BIOS

• 256Mb AMI BIOS

®

SPI Flash UEFI BIOS

• ACPI 6.0, Plug and Play (PnP), PCI F/W 3.0, BIOS rescue hot-key, SPI dual/quad speed support, riser Card auto detection

support, SMBIOS 3.0 or later, real time clock (RTC) wakeup

• Four (4) SATA 3.0 ports with RAID 0, 1, 5, 10 (I-SATA4~7)

• Two (2) S-SATA 3.0 ports with RAID 0, 1, 5, 10 (S-SATA0~1)

Power Management

• ACPI power management

• Power button override mechanism

• Wake-on-LAN

• Power-on mode for AC power recovery

• Power supply monitoring

System Health Monitoring

• Onboard voltage monitoring for +1.8V, +3.3V, +5V, +12V, +3.3V stdby, +5V stdby, VBAT, PCH temperature, system

temperature, and memory temperature

• 5 CPU switch phase voltage regulator

• CPU thermal trip support

• Platform Environment Control Interface (PECI)/TSI

Fan Control

• Fan status monitoring via IPMI connections

• Three cooling zones

• Multi-fan speed control support through onboard BMC

• Eight (8) 4-pin fan headers

System Management

• Trusted Platform Module (TPM) support

• SuperDoctor® 5

• Watchdog, Non-maskable Interrupt (NMI), RoHs

• Chassis intrusion header and detection (Note: Please connect a cable from the Chassis Intrusion header at JD1 to the

chassis to receive an alert via IPMI)

• Server Platform Service

Note: The table above is continued on the next page.

15

Super X11SPG-TF User's Manual

LED Indicators

• CPU/system overheat LED

• Powe state indicator LED

• Fan failed LED

• UID/remote UID

• HDD activity LED

• LAN activity LED

Dimensions

• 7.71" (W) x 16.64" (L) (195.8mm x 422.7mm)

Note 1: The CPU maximum thermal design power (TDP) is subject to chassis and

heatsink cooling restrictions. For proper thermal management, please check the chas-

sis and heatsink specications for proper CPU TDP sizing.

Motherboard Features

Note 2: For IPMI conguration instructions, please refer to the Embedded IPMI Con-

guration User's Guide available at http://www.supermicro.com/support/manuals/.

Note 3: It is strongly recommended that you change BMC log-in information upon initial
system power-on. The manufacture default username is ADMIN and the password is

ADMIN. For proper BMC conguration, please refer to https://www.supermicro.com/

products/nfo/les/IPMI/Best_Practices_BMC_Security.pdf.

16

Figure 1-3.

System Block Diagram

#C-1

#B-1

#A-1

VCCP0

VCCP0 12v

VR13

5+1 PHASE

205W

Chapter 1: Introduction

#F-1

#E-1

#D-1

LAN1
RJ45

LAN2
RJ45

IPMI
RJ45

DDR4

BMC Boot Flash

PCI-E X16

Right GPU

PCI-E X16

LEFT GPU

PCI-E X16

LAN3

RTL8211E-VB-CG

SPI

DDRIV

PCI-E X16 G3

PCI-E X16 G3

PCI-E X16 G3

M.2 SSD

M.2 SSD

Intel

X550 (10G)

RGRMII

BMC

AST2500

UP TO

2666/2933

RMII/NCSI

PCI-E X4 G3

PCI-E X4 G3

PCIE X4 G3

PCI-E X1 G2

USB 2.0

ESPI

ESPI
Header

SPI

SNB CORE
DDR-IV

#3

#2

#8~11

#12~15

#0~3

#5

#7 USB2.0

PECI:30

SOCKET ID:0

#1

PCH

(C621)

Switch

DMI3

DMI3

USB2.0 #3,4

USB2.0 #0,1

USB3.0 #3,4
USB2.0 #8,9 &

USB3.0 #6
USB2.0 #10 &

USB3.0 #1,2
USB2.0 #13,14 &

SPI

SPI

6.0 Gb/S

6.0 Gb/S

USB 2.0

USB 2.0

USB 3.0

UP TO

DDRIV

2666/2933

#7

#6

#5

#4

SATA

SATA-DOM

#1

#0

sSATA

Front USB2.0 x 2

USB

Front USB3.0 x 2

Type A USB3.0

Rear USB3.0 x 2

Rear USB2.0 x 2

USB

USB

USBUSB

VGA CONN

COM2
Header

Temp Sensor

EMC1402-1 *2 at diff SMBUS

TPM HEADER

Debug Card

BIOS

FRONT PANEL

SYSTEM POWER

FAN SPEED

CTRL

Note 1: This is a general block diagram and may not exactly represent the features

on your motherboard. See the previous pages for the actual specications of your

motherboard.

Note 2: 2933 MHz Memory is only supported by the 82xx/62xx series processors.

17

Super X11SPG-TF User's Manual

1.2 Processor and Chipset Overview

Built upon the functionality and capability of the Intel® Xeon 81xx/61xx/51xx/41xx/31xx and
82xx/62xx/52xx/42xx/32xx series (Socket P0-LGA3647) processor and the Intel C621 chipset,

the X11SPG-TF motherboard provides system performance, power e󰀩ciency, and feature

sets to address the needs of next-generation computer users.

With the support of the new Intel Microarchitecture 14nm Process Technology, the X11SPG-TF
dramatically increases system performance for a multitude of server applications.

The Intel C621 chipset provides Enterprise SMbus support, including the following features:

• DDR4 288-pin memory support

• Support for Management Engine (ME)

• Support of SMBus speeds of up to 400KHz for BMC connectivity

• Improved I/O capabilities to high-storage-capacity congurations

• SPI Enhancements

• Intel Node Manager 3.0 for advanced power monitoring, capping and management for BMC

enhancement (see note below).

• BMC supports remote management, virtualization, and the security package for enterprise

platforms

Note: Note Manager support depends on the power supply used in your system.

New features supported by the 82xx/62xx/52xx/42xx/32xx series processors include
the following:

• Higher performance for a variety of workloads per-core performance increase

• Vector Neural Network Instructions (VNNI) support to accelerate AI/Deep Learning work-

loads

• Intel Speed Select Technology with support by boosting performance on critical cores in

CPU based on on workload needs **

** - support on select SKUs

18

Chapter 1: Introduction

1.3 Special Features

Recovery from AC Power Loss

The Basic I/O System (BIOS) provides a setting that determines how the system will respond
when AC power is lost and then restored to the system. You can choose for the system to

remain powered o󰀨 (in which case you must press the power switch to turn it back on), or

for it to automatically return to the power-on state. See the Advanced BIOS Setup section
for this setting. The default setting is Last State.

1.4 System Health Monitoring

Onboard Voltage Monitors

An onboard voltage monitor will scan the voltages of the onboard chipset, memory, CPU,
and battery continuously. Once a voltage becomes unstable, a warning is given, or an error

message is sent to the screen. The user can adjust the voltage thresholds to dene the

sensitivity of the voltage monitor.

Fan Status Monitor with Firmware Control

The system health monitor embedded in the BMC chip can check the RPM status of the
cooling fans. The CPU and chassis fans are controlled via lPMI.

Environmental Temperature Control

System Health sensors monitor temperatures and voltage settings of onboard processors
and the system in real time via the IPMI interface. Whenever the temperature of the CPU or

the system exceeds a user-dened threshold, system/CPU cooling fans will be turned on to

prevent the CPU or the system from overheating.

Note: To avoid possible system overheating, please be sure to provide adequate air-

ow to your system.

System Resource Alert

This feature is available when used with SuperDoctor 5® in the Windows OS or in the Linux
environment. SuperDoctor is used to notify the user of certain system events. For example,

you can congure SuperDoctor to provide you with warnings when the system temperature,
CPU temperatures, voltages and fan speeds go beyond a predened range.

19

Super X11SPG-TF User's Manual

1.5 ACPI Features

ACPI stands for Advanced Conguration and Power Interface. The ACPI specication denes
a exible and abstract hardware interface that provides a standard way to integrate power

management features throughout a computer system, including its hardware, operating

system and application software. This enables the system to automatically turn on and o󰀨

peripherals such as CD-ROMs, network cards, hard disk drives and printers.

In addition to enabling operating system-directed power management, ACPI also provides a
generic system event mechanism for Plug and Play, and an operating system-independent

interface for conguration control. ACPI leverages the Plug and Play BIOS data structures,

while providing a processor architecture-independent implementation that is compatible with
the appropriate operating systems.

1.6 Power Supply

As with all computer products, a stable power source is necessary for proper and reliable
operation. It is even more important for processors that have high CPU clock rates where
noisy power transmission is present.

The X11SPG-TF motherboard accommodates a 20-pin main power supply. In addition, one
12V 8-pin power connector is supported to provide the required power to the GPU add-on card.

It is strongly recommended that you use a high quality power supply that meets ATX power

supply Specication 2.02 or above. It must also be SSI compliant. (For more information,

please refer to the website at http://www.ssiforum.org/).

1.7 Serial Port

The X11SPG-TF motherboard supports one serial communication connection. COM Port 2
can be used for input/output. The UART provides legacy speeds with a baud rate of up to

115.2 Kbps as well as an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which
support high-speed serial communication devices.

20

Chapter 2: Installation

Chapter 2

Installation

2.1 Static-Sensitive Devices

Electrostatic Discharge (ESD) can damage electronic com ponents. To avoid damaging your
system board, it is important to handle it very carefully. The following measures are generally

su󰀩cient to protect your equipment from ESD.

Precautions

• Use a grounded wrist strap designed to prevent static discharge.

• Touch a grounded metal object before removing the board from the antistatic bag.

• Handle the motherboard by its edges only; do not touch its components, peripheral chips,

memory modules or gold contacts.

• When handling chips or modules, avoid touching their pins.

• Put the motherboard and peripherals back into their antistatic bags when not in use.

• For grounding purposes, make sure that your computer chassis provides excellent conduc-

tivity between the power supply, the case, the mounting fasteners and the motherboard.

• Use only the correct type of onboard CMOS battery. Do not install the onboard battery

upside down to avoid possible explosion.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage. When unpacking
the motherboard, make sure that the person handling it is static protected.

21

Super X11SPG-TF User's Manual

2.2 Processor and Heatsink Installation

The processor (CPU) and processor carrier should be assembled together rst to form

the processor carrier assembly. This will be attached to the heatsink to form the processor
heatsink module (PHM) before being installed onto the CPU socket.

Notes:

• Use ESD protection.

• Unplug the AC power cord from all power supplies after shutting down the system.

• Check that the plastic protective cover is on the CPU socket and none of the socket pins

are bent. If they are, contact your retailer.

• When handling the processor, avoid touching or placing direct pressure on the LGA lands

(gold contacts). Improper installation or socket misalignment can cause serious damage
to the processor or CPU socket, which may require manufacturer repairs.

• Thermal grease is pre-applied on a new heatsink. No additional thermal grease is needed.

• Refer to the Supermicro website for updates on processor support.

• All graphics in this manual are for illustrations only. Your components may look di󰀨erent.

The Intel Xeon 81xx/61xx/51xx/41xx/31xx and 82xx/62xx/52xx/42xx/32xx Series Processor

Non-Fabric Model

22

Chapter 2: Installation

Overview of the Processor Carrier Assembly

The processor carrier assembly contains the Intel Xeon Non-Fabric (Non-F) processor and
a processor carrier.

1. Non-F Processor

2. Processor Carrier

Overview of the CPU Socket

The CPU socket is protected by a plastic protective cover.

1. Plastic Protective Cover

2. CPU Socket

23

Super X11SPG-TF User's Manual

Overview of the Processor Heatsink Module

The Processor Heatsink Module (PHM) contains a heatsink, a processor carrier, and the
Intel Xeon Non-Fabric (Non-F) processor.

1. Heatsink with Thermal Grease

2. Processor Carrier

3. Non-F Processor

Processor Heatsink Module

Bottom View

24

Chapter 2: Installation

Creating the Non-F Model Processor Carrier Assembly

To install a Non-F model processor into the processor carrier, follow the steps below:

1. Hold the processor with the LGA lands (gold contacts) facing up. Locate the small, gold
triangle in the corner of the processor and the corresponding hollowed triangle on the
processor carrier. These triangles indicate pin 1. See the images below.

2. Using the triangles as a guide, carefully align and place Point A of the processor into

Point A of the carrier. Then gently ex the other side of the carrier for the processor to t

into Point B.

3. Examine all corners to ensure that the processor is rmly attached to the carrier.

CPU (Upside Down)
with CPU LGA Lands up

Align Point A of the CPU and
Point A of the Processor Carrier

Align CPU Pin 1

B

Align Point B of the CPU and
Point B of the Processor Carrier

A

Pin 1

B

A

Processor Carrier
(Upside Down)

Allow carrier to
latch onto CPU

B

A

Allow carrier to
latch onto CPU

Processor Carrier Assembly (Non-F Model)

Pin 1

25

Super X11SPG-TF User's Manual

Assembling the Processor Heatsink Module

After creating the processor carrier assembly for the Non-F model processor, mount it onto
the heatsink to create the processor heatsink module (PHM):

1. Note the label on top of the heatsink, which marks the heatsink mounting holes as 1,
2, 3, and 4. If this is a new heatsink, the thermal grease has been pre-applied on the
underside. Otherwise, apply the proper amount of thermal grease.

2. Turn the heatsink over with the thermal grease facing up. Hold the processor carrier
assembly so the processor's gold contacts are facing up, then align the triangle on the
assembly with hole 1 of the heatsink. Press the processor carrier assembly down. The
plastic clips of the assembly will lock outside of holes 1 and 2, while the remaining clips
will snap into their corresponding holes.

3. Examine all corners to ensure that the plastic clips on the processor carrier assembly

are rmly attached to the heatsink.

Triangle on the CPU

Triangle on the
Processor Carrier

Plastic clips 1 and 2 lock
outside the heatsink’s
mounting holes

Non-Fabric Processor Carrier Assembly

(Upside Down)

Heatsink

(Upside Down)

2

2

1

1

Remaining plastic clips snap

into the other corner holes

2

of the heatsink

1

26

Chapter 2: Installation

Preparing the CPU Socket for Installation

This motherboard comes with a plastic protective cover installed on the CPU socket. Remove
it from the socket to install the Processor Heatsink Module (PHM). Gently pull up one corner
of the plastic protective cover to remove it.

CPU Socket with Plastic Protective Cover

Remove the plastic protective

cover from the CPU socket.

Do not touch or bend

the socket pins.

Socket Pins

27

Super X11SPG-TF User's Manual

Installing the Processor Heatsink Module

After assembling the Processor Heatsink Module (PHM), install the PHM onto the CPU socket:

1. Align hole 1 of the heatsink with the printed triangle on the CPU socket. See the left
image below.

2. Make sure all four holes of the heatsink are aligned with the socket before gently placing
the heatsink on top.

3. With a T30 Torx-bit screwdriver, gradually tighten screws #1 - #4 to ensure even
pressure. The order of the screws is shown on the label on top of the heatsink. To
avoid damaging the processor or socket, do not use a force greater than 12 lbf-in when
tightening the screws.

4. Examine all corners to ensure that the PHM is rmly attached to the socket.

Oval C

Oval D

Small Guide Post

Large Guide Post

Printed Triangle

Mounting the Processor Heatsink Module
onto the CPU socket (on the motherboard)

#1

Use a torque
of 12 lbf-in

T30 Torx Screwdriver

#4

#2

#3

Tighten the screws in
the sequence of 1, 2, 3, 4

28

Chapter 2: Installation

Removing the Processor Heatsink Module

Before removing the processor heatsink module (PHM) from the motherboard, unplug the
AC power cord from all power supplies after shutting down the system. Then follow the steps
below:

1. Use a T30 Torx-bit screwdriver to loosen the four screws in a backwards sequence of
#4, #3, #2, and #1.

2. Gently lift the PHM upwards to remove it from the socket.

#1

Remove the screws in

the sequence of 4, 3, 2, 1

#4

#2

#3

Printed Triangle on Motherboard

CPU Socket

After removing the screws,

lift the Processor Heatsink
Module off the CPU socket.

29

Super X11SPG-TF User's Manual

2.3 Motherboard Installation

All motherboards have standard mounting holes to t di󰀨erent types of chassis. Make sure

that the locations of all the mounting holes for both the motherboard and the chassis match.
Although a chassis may have both plastic and metal mounting fasteners, metal ones are
highly recommended because they ground the motherboard to the chassis. Make sure that

the metal stando󰀨s click in or are screwed in tightly.

Tools Needed

Phillips

Screwdriver

(1)

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

JPI2C1

Phillips Screws

(7)

USB1

Aspeed

AST2500

X11SPG-TF

Intel
C621

SAN MAC

JPTG1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

VGA

JPG1

JSTBY1

REV: 1.01

DESIGNED IN USA

BT1

DIMMD1

FAN3

LAN1

MH12

BIOS LICENSE

IPMI_LAN

USB4/5(3.0)

USB2/3

JIPMB1

USB6/7(3.0)

JP4

LE3
LE4

DIMMA1

FAN2

+

SP1

USB8(3.0)

DIMMB1

DIMMC1

FAN1

SXB2A

SXB2B PCI-E 3.0 X16

JP3

JTPM1

JNVI2C1

FANC

FAND

JOH1

ON

JF1

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

JPWR6

JL1

Stando󰀨s (7)

Only if Needed

JRK1

Location of Mounting Holes

Note: 1) To avoid damaging the motherboard and its components, please do not use

a force greater than 8 lbf-in on each mounting screw during motherboard installation.

2) Some components are very close to the mounting holes. Please take precaution­ary measures to avoid damaging these components when installing the motherboard
to the chassis.

30

Chapter 2: Installation

Installing the Motherboard

1. Install the I/O shield into the back of the chassis, if applicable.

2. Locate the mounting holes on the motherboard. See the previous page for the location.

3. Locate the matching mounting holes on the chassis. Align the mounting holes on the
motherboard against the mounting holes on the chassis.

4. Install stando󰀨s in the chassis as needed.

5. Install the motherboard into the chassis carefully to avoid damaging other motherboard
components.

6. Using the Phillips screwdriver, insert a pan head #6 screw into a mounting hole on the
motherboard and its matching mounting hole on the chassis.

7. Repeat Step 5 to insert #6 screws into all mounting holes.

8. Make sure that the motherboard is securely placed in the chassis.

Note: Images displayed are for illustration only. Your chassis or components might

look di󰀨erent from those shown in this manual.

31

Super X11SPG-TF User's Manual

2.4 Memory Support and Installation

Note: Check the Supermicro website for recommended memory modules.

Important: Exercise extreme care when installing or removing DIMM modules to pre-

vent any possible damage.

Memory Support

The X11SPG-TF supports up to 384GB of RDIMM, 768GB of LRDIMM, and 1.5TB of 3DS
LRDIMM DDR4 (288-pin) ECC memory with speeds of up to 2933MHz in six memory slots.
Refer to the table below for additional memory information.

Note: 2933MHz memory is only supported by the 82xx/62xx series processors.

1 CPU, 6-DIMM Slots

Number of DIMMs Memory Population Sequence

1 DIMMA1

2 DIMMA1 / DIMMD1

3 DIMMC1 / DIMMB1 / DIMMA1

4 DIMMB1 / DIMMA1 / DIMMD1 / DIMME1

(Unbalanced: Not Recommended)

5

6 DIMMC1 / DIMMB1 / DIMMA1 / DIMMD1 / DIMME1 / DIMMF1

DIMMC1 / DIMMB1 / DIMMA1 / DIMMD1 / DIMME1

DDR4 Memory Support for 81xx/61xx/51xx/41xx/31xx Platform

Speed (MT/s), Voltage (V),

DIMM Capacity

DIMM Type

RDIMM SRx4 8GB 16GB

RDIMM SRx8 4GB 8GB

RDIMM DRx8 8GB 16GB

RDIMM DRx4 16GB 32GB

RDIMM 3DS

LRDIMM QRx4 32GB 64GB

LRDIMM 3DS

Ranks Per DIMM

and Data Width

QRx4 N/A 2H-64GB

8Rx4 N/A 4H-128GB

QRx4 N/A 2H-64GB

8Rx4 N/A 4H-128GB

(GB)

DRAM Density 1DPC 1DPC 2DPC

4Gb 8Gb 1.2V 1.2V 1.2V

Slot Per Channel (SPC),

and DIMM Per Channel (DPC)

1 Slot Per

Channel

2666 2666 2666

2 Slots Per Channel

32

Chapter 2: Installation

DDR4 Memory Support for 82xx/62xx/52xx/42xx/32xx Platform

DIMM Capacity

DIMM Type

RDIMM SRx4 4GB 8GB 16GB

RDIMM SRx8 8GB 16GB 32GB

RDIMM DRx8 8GB 16GB 32GB

RDIMM DRx4 16GB 32GB 64GB

RDIMM 3DS

LRDIMM QRx4 32GB 64GB 128GB

LRDIMM 3DS

Ranks Per DIMM

and Data Width

4Gb 8Gb 16GB 1.2V 1.2V 1.2V

QRx4 N/A 2H-64GB 2H-128GB

8Rx4 N/A 4H-128GB 4H-256GB

QRx4 N/A 2H-64GB 2H-128GB

8Rx4 N/A 4H-128GB 4H-256GB

(GB)

DRAM Density 1DPC 1DPC 2DPC

Note 1: 2933MHz memory is supported only by the 82xx/62xx series processors.

Speed (MT/s), Voltage (V),

Slot Per Channel (SPC),

and DIMM Per Channel (DPC)

1 Slot Per

Channel

2933 2933 2666

2 Slots Per Channel

Note 2: Refer to the Memory Conguration User Guide for the X11 UP/DP/MP Moth-

erboards on the Supermicro website for detailed information on memory support for
this motherboard.

* 4Gb DRAM density is only supported on speeds up to 2666MT/s.

33

Super X11SPG-TF User's Manual

General Guidelines for Optimizing Memory Performance

• Always use DDR4 memory of the same type, size and speed.

• Mixed DIMM speeds can be installed. However, all DIMMs will run at the speed of the

slowest DIMM.

• The motherboard will support odd-numbered modules (one or three modules installed).

However, to achieve the best memory performance, a balanced memory population is
recommended.

USB1

Intel

C621

JPTG1

JWD1

JBT1

USB0

JPCK1

JD1

JP2

JPME2

M.2-H_1 PCI-E 3.0 X4

JP1

CPU

LAN2

LAN1

Intel

X550

MH12

MH10

M.2-H_2 PCI-E 3.0 X4

IPMI_LAN

USB4/5(3.0)

USB2/3

JIPMB1

USB6/7(3.0)

JP4

USB8(3.0)

LE3
LE4

SXB2A

+

SP1

SXB2B PCI-E 3.0 X16

JP3

JTPM1

JNVI2C1

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

DESIGNED IN USA

+

BT1

JSD2

JSD1

S-SATA0

S-SATA1

VGA

Aspeed

AST2500

JPG1

REV: 1.01

X11SPG-TF

DIMMF1

DIMME1

DIMMD1

JPI2C1

JPWR5

DIMMF1

FAN4

DIMME1

FAN3

DIMMD1

SAN MAC

34

IPMI CODE

MAC CODE

DIMMA1

DIMMB1

DIMMC1

BAR CODE

JRK1

FANC

FAND

JOH1

ON

FAN2

DIMMB1

FAN1

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMC1

JL1

JF1

LE2

JPWR6

BIOS LICENSE

DIMMA1

FANA

FANB

I-SATA7

I-SATA6

I-SATA5

I-SATA4

USB1

USB0

DIMM Installation

1. Insert the desired number of DIMMs
into the memory slots based on the
Recommended Memory Population Guide
table on page 32.

2. Push the release tabs outwards on both
ends of the DIMM slot to unlock it.

3. Align the key of the DIMM module with the
receptive point on the memory slot.

4. Align the notches on both ends of the
module against the receptive points on the
ends of the slot.

5. Press the notches on both ends of the
module straight down into the slot until the
module snaps into place.

6. Press the release tabs to the lock positions
to secure the DIMM module into the slot.

JUIDB1

LE1

SXB1A

CPU SLOT3 PCI-E 3.0 X16

SXB1B PCI-E 3.0 X16

JSD1

S-SATA0

S-SGPIO1

I-SGPIO2

JPWR5

DIMMF1

FAN4

JPI2C1

COM2

VGA

LEDM1

JSTBY1

REV: 1.01

DESIGNED IN USA

+

BT1

JSD2

S-SATA1

DIMME1

DIMMD1

FAN3

Chapter 2: Installation

JPTG1

JPCK1

LAN2

IPMI_LAN

LAN1

USB4/5(3.0)

Intel
C621

JWD1

JBT1

JD1

JP1

IPMI CODE

MAC CODE

JPME2

CPU

Intel
X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

USB2/3

MH12

JIPMB1

USB6/7(3.0)

JP4

USB8(3.0)

LE3
LE4

BIOS LICENSE

DIMMB1

DIMMA1

FAN2

FAN1

Aspeed

AST2500

JPG1

X11SPG-TF

SAN MAC

SP1

+

SXB2A

DIMMC1

ON

LEDLED12LEDFAIL

JL1

SXB2B PCI-E 3.0 X16

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

JF1

LE2

NMIXPWRHDDNICNICUIDPSRSTPWR

JPWR6

DIMM Removal

Press both release tabs on the ends of the
DIMM socket to unlock it. Once the DIMM
module is loosened, remove it from the
memory slot.

Release Tabs

Notches

Press both notches

straight down into

the memory slot.

35

Super X11SPG-TF User's Manual

JPI2C1

2.5 Rear I/O Ports

See Figure 2-1 below for the locations and descriptions of the various I/O ports on the rear
of the motherboard.

USB1

Aspeed

AST2500

X11SPG-TF

Intel
C621

SAN MAC

JPTG1

JWD1

JBT1

USB0

JPCK1

JD1

JP2

JPME2

M.2-H_1 PCI-E 3.0 X4

JP1

CPU

IPMI CODE

MAC CODE

LAN2

Intel
X550

MH10

M.2-H_2 PCI-E 3.0 X4

BAR CODE

LAN1

MH12

BIOS LICENSE

IPMI_LAN

USB4/5(3.0)

USB2/3

JIPMB1

USB6/7(3.0)

JP4

LE3
LE4

DIMMA1

FAN2

+

SP1

USB8(3.0)

DIMMB1

FAN1

SXB2A

DIMMC1

JL1

JTPM1

JNVI2C1

FANC

FAND

ON

JF1

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

SXB2B PCI-E 3.0 X16

JP3

JRK1

JOH1

JPWR6

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

DESIGNED IN USA

+

BT1

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

JPG1

REV: 1.01

DIMMD1

Figure 2-1. I/O Port Locations and Denitions

1

2

4

5

6

7

3

# Description # Description # Description

1 Dedicated IPMI LAN 4 LAN1 7 USB1

2 USB5 (3.0) 5 LAN2 8 VGA Port

3 USB4 (3.0) 6 USB0 9 UID Switch

36

98

Chapter 2: Installation

JPI2C1

USB1

LAN Ports

Two Gigabit Ethernet ports (LAN1, LAN2) are located on the I/O back panel. In addition, a
dedicated IPMI LAN is located above USB4/5. All of these ports accept RJ45 cables. Please
refer to the LED Indicator section for LAN LED information.

LAN Port

Pin Denition

Pin# Denition Pin# Denition

1 TD0- 11 P3V3_Dual

2 TD0+ 12 Act LED (Yellow)

3 TD1- 13

4 TD1+ 14

Link 1000

(Amber)

Link 100 LED

(Green)

5 TD2- 15 GND

6 TD2+ 16 GND

7 TD3- 17 GND

8 TD3+ 18 GND

9 COMMCT

10 GND

Pin# Denition Pin# Denition

9 19 GND

10 TD0+ 20

11 TD0- 21

12 TD1+ 22

13 TD1- 23 SGND

14 TD2+ 24 SGND

15 TD2- 25 SGND

16 TD3+ 26 SGND

17 TD3-

IPMI LAN

Pin Denition

Act LED

(Yellow)

Link 100 LED

(Green)

Link 1000 LED

(Amber)

18 GND

12 3

Aspeed

AST2500

JPG1

X11SPG-TF

Intel

C621

SAN MAC

JPTG1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. LAN1

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMC1

DIMMB1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. LAN2

3. IPMI LAN

JUIDB1

LE1

COM2

VGA

SXB1A

CPU SLOT3 PCI-E 3.0 X16

LEDM1

SXB1B PCI-E 3.0 X16

+

JSD1

S-SATA0

S-SGPIO1

I-SGPIO2

JPWR5

DIMMF1

FAN4

JSTBY1

REV: 1.01

DESIGNED IN USA

BT1

JSD2

S-SATA1

DIMME1

DIMMD1

FAN3

I-SATA4

I-SATA5

I-SATA6

I-SATA7

FANA

FANB

37

Super X11SPG-TF User's Manual

JPI2C1

I-SATA7

I-SATA5

I-SATA4

Universal Serial Bus (USB) Ports

There are two USB 2.0 ports (USB0, USB1) and two USB 3.0 ports (USB4/5) located on
the I/O back panel. The motherboard also has one front access USB 2.0 header (USB2/3)
and one front access USB 3.0 header (USB6/7). The USB8 header is USB 3.0 Type-A. The
onboard headers can be used to provide front side USB access with a cable (not included).

Back Panel USB 0/1 (2.0)

Pin Denitions

Pin# Denition Pin# Denition

1 +5V 5 +5V

2 USB_N 6 USB_N

3 USB_P 7 USB_P

4 GND 8 GND

Pin# Denition Pin# Denition

1 +5V 2 +5V

3 USB_N 4 USB_N

5 USB_P 6 USB_P

7 GND 8 GND

Front Panel USB 2/3 (2.0)

Pin Denitions

9 Key 10 NC

Back Panel USB 4/5 (3.0)

Pin Denitions

Pin# Denition Pin# Denition

A1 VBUS B1 Power

A2 D- B2 USB_N

A3 D+ B3 USB_P

A4 GND B4 GND

A5 Stda_SSRX- B5 USB3_RN

A6 Stda_SSRX+ B6 USB3_RP

A7 GND B7 GND

A8 Stda_SSTX- B8 USB3_TN

A9 Stda_SSTX+ B9 USB3_TP

12

USB1

VGA

Aspeed

AST2500

JPG1

JSTBY1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel
C621

DIMMD1

SAN MAC

USB0

JPTG1

JPCK1

JD1

JWD1

JPME2

JP1

JBT1

CPU

IPMI CODE

MAC CODE

JUIDB1

LE1

COM2

SXB1A

CPU SLOT3 PCI-E 3.0 X16

LEDM1

SXB1B PCI-E 3.0 X16

+

JSD2

JSD1

I-SATA6

S-SATA0

S-SATA1

S-SGPIO1

I-SGPIO2

FANA

FANB

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

4

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

USB2/3

3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

5

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

6

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMC1

DIMMB1

DIMMA1

JPWR6

FAN2

FAN1

JL1

Pin# Denition Pin# Denition

1

2

3

4

5

6

7

8

9

10 x

Front Panel USB 6/7 (3.0)

Pin Denitions

VBUS 19 Power

Stda_SSRX- 18 USB3_RN

Stda_SSRX+ 17 USB3_RP

GND 16 GND

Stda_SSTX- 15 USB3_TN

Stda_SSTX+ 14 USB3_TP

GND 13 GND

D- 12 USB_N

D+ 11 USB_P

Type A USB 8 (3.0)

Pin Denitions

Pin# Denition Pin# Denition

1 VBUS 5 SSRX-

2 USB_N 6 SSRX+

3 USB_P 7 GND

4 GND 8 SSTX-

9 SSTX+

1. USB0

2. USB1

3. USB2/3

4. USB4/5

5. USB6/7

6. USB8

38

Chapter 2: Installation

JPI2C1

Unit Identier Switch/UID LED Indicator

A Unit Identier (UID) switch and an LED Indicator are located on the motherboard. The UID

switch is located at JUIDB1, which is next to the VGA port on the back panel. The UID LED
(LE1) is located next to the UID switch. When you press the UID switch, the UID LED will

be turned on. Press the UID switch again to turn o󰀨 the LED indicator. The UID Indicator
provides easy identication of a system unit that may be in need of service.

Note: UID can also be triggered via IPMI on the motherboard. For more information
on IPMI, please refer to the IPMI User's Guide posted on our website at http://www.
supermicro.com.

UID Switch

Pin Denitions

Pin# Denition

1 GND

Color Status

Blue: On Unit Identied

UID LED

Pin Denitions

2 GND

3 Button In

4 Button In

VGA Port

A video (VGA) port is located next to USB1 on the I/O back panel. Refer to the board layout
below for the location.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

1 2

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

3

VGA

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. UID Switch

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. UID LED

3. VGA

39

Super X11SPG-TF User's Manual

I-SATA7

I-SATA5

2.6 Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally located on a

control panel at the front of the chassis. These connectors are designed specically for use
with Supermicro chassis. See the gure below for the descriptions of the front control panel

buttons and LED indicators.

USB1

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA6

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

FAN4

JPI2C1

VGA

LEDM1

JPG1

JSTBY1

REV: 1.01

DESIGNED IN USA

BT1

DIMME1

DIMMD1

FAN3

JPTG1

Aspeed

AST2500

X11SPG-TF

Intel

C621

SAN MAC

JWD1

JBT1

USB0

JPCK1

JD1

JP2

JPME2

M.2-H_1 PCI-E 3.0 X4

JP1

CPU

IPMI CODE

MAC CODE

LAN2

Intel

X550

MH10

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

DIMMA1

FAN2

DIMMB1

FAN1

LEDLED12LEDFAIL

DIMMC1

JL1

JF1

LE2

NMIXPWRHDDNICNICUIDPSRSTPWR

JPWR6

BIOS LICENSE

Figure 2-2. JF1 Header Pins

1 2

PWR

Power Button

Reset

Reset Button

3.3V

UID LED

3.3V Stby

3.3V Stby

UID SW

3.3V

X

NMI

19

Ground

Ground

Power Fail LED

OH/Fan Fail LED

NIC2 Active LED

NIC1 Active LED

HDD LED

PWR LED

X

Ground

20

40

Chapter 2: Installation

Power Button

The Power Button connection is located on pins 1 and 2 of JF1. Momentarily contacting both

pins will power on/o󰀨 the system. This button can also be congured to function as a suspend
button (with a setting in the BIOS - see Chapter 4). To turn o󰀨 the power when the system

is in suspend mode, press the button for 4 seconds or longer. Refer to the table below for

pin denitions.

Power Button

Pin Denitions (JF1)

Pins Denition

1 Signal

2 GND

Reset Button

The Reset Button connection is located on pins 3 and 4 of JF1. Attach it to a hardware reset

switch on the computer case to reset the system. Refer to the table below for pin denitions.

Reset Button

Pin Denitions (JF1)

Pins Denition

3 Reset

4 GND

1 2

PWR

Reset

Power Button

Reset Button

3.3V

UID LED

3.3V Stby

3.3V Stby

UID SW

Ground

Ground

Power Fail LED

OH/Fan Fail LED

NIC2 Active LED

NIC1 Active LED

HDD LED

1

2

1. PWR Button

2. Reset Button

3.3V

NMI

PWR LED

X

19

20

X

Ground

41

Super X11SPG-TF User's Manual

Power Fail LED

The Power Fail LED connection is located on pins 5 and 6 of JF1. Refer to the table below

for pin denitions.

Power Fail LED

Pin Denitions (JF1)

Pin# Denition

5 3.3V

6 PWR Supply Fail

Overheat (OH)/Fan Fail

Connect an LED cable to pins 7 and 8 of the Front Control Panel to use the Overheat/Fan
Fail LED connections. The LED on pin 8 provides warnings of overheating or fan failure.

Refer to the tables below for pin denitions.

PWR

Reset

OH/Fan Fail Indicator

Status

State Denition

O󰀨 Normal

On Overheat

Flashing Fan Fail

Power Button

Reset Button

3.3V

UID LED

3.3V Stby

3.3V Stby

1 2

Ground

Ground

Power Fail LED

OH/Fan Fail LED

NIC2 Active LED

NIC1 Active LED

OH/Fan Fail LED

Pin Denitions (JF1)

Pin# Denition

7 Blue LED

8 OH/Fan Fail LED

1. Power Fail LED

2. OH/Fan Fail LED

1

2

UID SW

3.3V

NMI

HDD LED

PWR LED

X

19

20

X

Ground

42

Chapter 2: Installation

NIC1/NIC2 (LAN1/LAN2)

The Network Interface Controller (NIC) LED connection for LAN port 1 is located on pins 11
and 12 of JF1, and the LED connection for LAN port 2 is on Pins 9 and 10. Attach the NIC

LED cables here to display network activity. Refer to the table below for pin denitions.

LAN1/LAN2 LED

Pin Denitions (JF1)

Pins Denition

9/11 Vcc

10/12

NIC2 Active LED/

NIC1 Active LED

HDD LED/UID Switch

The HDD LED/UID Switch connection is located on pins 13 and 14 of JF1. Attach a cable
to pin 14 to show hard drive activity status. Attach a cable to pin 13 to use the UID switch.

Refer to the table below for pin denitions.

PWR

Reset

Power Button

Reset Button

3.3V

UID LED

3.3V Stby

3.3V Stby

UID SW

1 2

HDD LED/UID Switch

Pin Denitions (JF1)

Pin# Denition

13 3.3V Stdby/UID SW

14 HDD Active

Ground

Ground

Power Fail LED

OH/Fan Fail LED

NIC2 Active LED

NIC1 Active LED

HDD LED

3

1. NIC2 LED

2. NIC1 LED

3. HDD LED

1

2

3.3V

NMI

PWR LED

X

19

20

X

Ground

43

Super X11SPG-TF User's Manual

Power LED

The Power LED connection is located on pins 15 and 16 of JF1. Refer to the table below

for pin denitions.

Power LED

Pin Denitions (JF1)

Pins Denition

15 3.3V

16 PWR LED

NMI Button

The non-maskable interrupt (NMI) button header is located on pins 19 and 20 of JF1. Refer

to the table below for pin denitions.

PWR

Reset

Power Button

Reset Button

3.3V

UID LED

3.3V Stby

1 2

Pins Denition

19 Control

20 GND

Ground

Ground

Power Fail LED

OH/Fan Fail LED

NIC2 Active LED

NMI Button

Pin Denitions (JF1)

1. PWR LED

2. NMI

3.3V Stby

UID SW

3.3V

NMI

2

NIC1 Active LED

HDD LED

PWR LED

X

19

20

X

Ground

1

44

Chapter 2: Installation

JPI2C1

FANB

I-SATA7

I-SATA6

I-SATA5

I-SATA4

USB1

USB0

2.7 Connectors

Power Connections

Main Power and GPU Power Connectors

The 20-pin main power connector (JPWR5) is used to provide power to the motherboard,
while the 8-pin GPU power connector (JPWR6) can be connected to power the GPU card.

These power connectors meet the SSI EPS 12V specication. See the tables below for pin
denitions.

Main Power 20-pin Connector

Pin Denitions

Pin# Denition Pin# Denition

11 PS_ON_N 1 GND

12 P5V_STBY 2 GND

Pin# Denition

1 - 4 GND

5 - 8 P12V (12V Power)

8-pin Power

Pin Denitions

13 GND 3 GND

14 GND 4 GND

15 GND 5 GND

16 NC 6 NC

17 P12V 7 P12V

18 P12V 8 P12V

19 P12V 9 P12V

20 P12V 10 P12V

Required Connection

JUIDB1

LE1

COM2

VGA

JPTG1

Aspeed

AST2500

JPG1

JSTBY1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel
C621

DIMMD1

SAN MAC

JWD1

JBT1

JPCK1

JD1

IPMI CODE

MAC CODE

JPME2

JP1

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. 20-Pin Main PWR

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMC1

DIMMB1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2

2. 8-Pin GPU PWR

SXB1A

CPU SLOT3 PCI-E 3.0 X16

LEDM1

SXB1B PCI-E 3.0 X16

+

JSD2

JSD1

S-SATA0

S-SATA1

S-SGPIO1

I-SGPIO2

FANA

JPWR5

DIMMF1

1

DIMME1

FAN4

FAN3

45

Super X11SPG-TF User's Manual

JPI2C1

Headers

Fan Headers

There are eight 4-pin fan headers (FAN1~4, FANA~D) on the motherboard. All these 4-pin
fan headers are backwards compatible with the traditional 3-pin fans. However, fan speed
control is available for 4-pin fans only by Thermal Management via the IPMI 2.0 interface.

Refer to the table below for pin denitions.

Fan Header

Pin Denitions

Pin# Denition

1 GND (Black)

2 2.5A/+12V (Red)

3 Tachometer

4 PWM_Control

USB1

Aspeed

AST2500

JPG1

X11SPG-TF

Intel

C621

SAN MAC

JPTG1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. FAN1

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

2. FAN2

3. FAN3

4. FAN4

5. FANA

6. FANB

7. FANC

JTPM1

8. FAND

JNVI2C1

JRK1

FANC

7

FAND

JOH1

8

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMC1

DIMMB1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2

1

JUIDB1

LE1

COM2

VGA

SXB1A

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

REV: 1.01

DESIGNED IN USA

SXB1B PCI-E 3.0 X16

+

BT1

JSD2

JSD1

I-SATA4

I-SATA5

I-SATA6

S-SATA0

S-SATA1

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

5

FANB

6

JPWR5

DIMMF1

DIMME1

DIMMD1

FAN4

FAN3

3

4

46

Chapter 2: Installation

JPI2C1

SGPIO Headers

There are two Serial Link General Purpose Input/Output (I-SGPIO2, S-SGPIO1) headers
located on the motherboard. I-SGPIO is for SATA use, while S-SGPIO is for sSATA use. Refer

to the tables below for pin denitions.

SGPIO Header

Pin Denitions

Pin# Denition Pin# Denition

1 NC 2 NC

3 GND 4 Data

5 Load 6 GND

7 Clock 8 NC

NC = No Connection

Disk-On-Module Power Connector

Two power connectors for SATA DOM (Disk-On-Module) devices are located at JSD1 and
JSD2. Connect appropriate cables here to provide power support for your Serial Link DOM
devices.

DOM Power

Pin Denitions

Pin# Denition

1 5V

2 GND

3 GND

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

2

S-SGPIO1

I-SGPIO2

FANA

FANB

1

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

4

3

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. I-SGPIO2

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. S-SGPIO1

3. JSD1 (DOM PWR)

4. JSD2 (DOM PWR)

47

Super X11SPG-TF User's Manual

JPI2C1

COM Header

There is one COM header (COM2) on the motherboard. Refer to the table below for pin

denitions.

COM Header

Pin Denitions

Pin# Denition Pin# Denition

1 DCD 6 DSR

2 RXD 7 RTS

3 TXD 8 CTS

4 DTR 9 RI

5 GND 10 N/A

Intel RAID Key Header

The JRK1 header allows the user to enable RAID functions for NVMe connections. Refer to

the table below for pin denitions.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

1

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

Intel RAID Key Header

Pin Denitions

Pin# Dention

1 GND

2 PU 3.3V Stdby

3

4

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

GND

PCH RAID KEY

1. COM2

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

2

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. Intel RAID Key

48

Chapter 2: Installation

JPI2C1

TPM/Port 80 Header

A Trusted Platform Module (TPM)/Port 80 header is located at JTPM1 to provide TPM support
and Port 80 connection. Use this header to enhance system performance and data security.

Refer to the table below for pin denitions. Please go to the following link for more information

on the TPM: http://www.supermicro.com/manuals/other/TPM.pdf.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

Trusted Platform Module Header

Pin Denitions

Pin# Denition Pin# Denition

1 +3.3V 2 SPI_CS#

3 RESET# 4 SPI_MISO

5 SPI_CLK 6 GND

7 SPI_MOSI 8 NC

9 +3.3V Stdby 10 SPI_IRQ#

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

1. TPM Header

49

Super X11SPG-TF User's Manual

JPI2C1

Standby Power

The Standby Power header is located at JSTBY1 on the motherboard. You must have a card
with a Standby Power connector and a cable to use this feature. Refer to the table below

for pin denitions.

Standby Power

Pin Denitions

Pin# Denition

1 +5V Standby

2 GND

3 No Connection

Internal Speaker/Buzzer

The Internal Speaker/Buzzer (SP1) is used to provide audible indications for various beep

codes. Refer to the table below for pin denitions.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

Aspeed

AST2500

JPG1

1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

Internal Buzzer

Pin Denitions

Pin# Denition

1 Pos (+) Beep In

2 Neg (-) Alarm Speaker

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. Standby Power

USB2/3

MH12

+

JIPMB1

2

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. Internal Speaker

50

Chapter 2: Installation

JPI2C1

Power SMB (I2C) Header

The Power System Management Bus (I2C) connector (JPI2C1) monitors the power supply,

fan, and system temperatures. Refer to the table below for pin denitions.

Power SMB Header

Pin Denitions

Pin# Denition

1 Clock

2 Data

3 PMBUS_Alert

4 GND

5 +3.3V

NVMe I2C Header

Connector JNVI2C1 is a management header for the Supermicro AOC NVMe PCI-E peripheral
cards. Please connect the I2C cable to this connector.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

1

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. Power SMB Header

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

2

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. NVMe I2C Header

51

Super X11SPG-TF User's Manual

JPI2C1

Chassis Intrusion

A Chassis Intrusion header is located at JL1 on the motherboard. Connect the appropriate
cable from JL1 to the chassis to be alerted of chassis intrusion (via IPMI) when the system

case is opened. Refer to the table below for pin denitions.

Chassis Intrusion

Pin Denitions

Pin# Denition

1 Intrusion Input

2 GND

4-pin BMC External I2C Header

A System Management Bus header for IPMI 2.0 is located at JIPMB1. Connect the appropriate
cable here to use the IPMB I2C connection on your system. Refer to the table below for pin

denitions.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

External I2C Header

Pin Denitions

Pin# Denition

1 Data

2 GND

3 Clock

4 No Connection

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. Chassis Intrusion

USB2/3

MH12

+

JIPMB1

2

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

1

2. BMC External Header

52

Chapter 2: Installation

JPI2C1

Power LED/Speaker

Pins 1-3 of JD1 are used for power LED indication, and pins 4-7 are for the speaker. Please
note that the speaker connector pins (4-7) are used with an external speaker. If you wish to
use the onboard speaker, you should close pins 6-7 with a cap. Refer to the tables below

for pin denitions.

PWR LED Connector

Pin Denitions

Pin# Signal

1 JD1_PIN1

2 FP_PWR_LED

3 FP_PWR_LED

Speaker Connector

Pin Denitions

Pin# Signal

4 P5V

5 Key

6 R_SPKPIN_N

7 R_SPKPIN

M.2 Slot

The X11SPG-TF motherboard has two M.2 slots. M.2 was formerly known as Next Generation
Form Factor (NGFF) and serves to replace mini PCI-E. M.2 allows for a variety of card sizes,

increased functionality, and spatial e󰀩ciency. The M.2 socket on the motherboard supports

PCI-E 3.0 x4 (32 Gb/s) SSD cards in the 2280 and 22110 form factors. It can also support
SATA devices.

USB1

Aspeed

AST2500

JPG1

X11SPG-TF

Intel

C621

SAN MAC

JPTG1

JWD1

JBT1

JPCK1

1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. Speaker Header

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. Dual M.2 Slots

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

REV: 1.01

DESIGNED IN USA

BT1

DIMMD1

53

Super X11SPG-TF User's Manual

JPI2C1

SATA Ports

The X11SPG-TF has six SATA 3.0 ports (I-SATA4~7, S-SATA0~1) supported by the Intel C621
chipset. These SATA ports support RAID 0, 1, 5, and 10. SATA ports provide serial-link signal
connections, which are faster than the connections of Parallel ATA.

Note: Supermicro SuperDOMs are yellow SATADOM connectors with power pins built
in and do not require separate external power cables. These connectors are backwards
compatible with non-Supermicro SATADOMS that require an external power supply.

Overheat/Fan Fail LED Header

The JOH1 header is used to connect an LED indicator to provide warnings of chassis
overheating and fan failure. This LED will blink when a fan failure occurs. Refer to the tables

below for pin denitions.

Overheat LED Header

Status

State Denition

Solid Overheat

Blinking Fan Fail

Pin# Signal

1

Overheat LED

Pin Denitions

Pull high to +3.3V

power through 330-ohm

resistor

2 OH Active

USB1

Aspeed

AST2500

JPG1

X11SPG-TF

Intel

C621

SAN MAC

JPTG1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. I-SATA4

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

2. I-SATA5

3. I-SATA6

4. I-SATA7

5. S-SATA0

6. S-SATA1

7. Overheat/Fan Fail LED

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

7

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

Header

JUIDB1

LE1

COM2

VGA

SXB1A

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

REV: 1.01

DESIGNED IN USA

SXB1B PCI-E 3.0 X16

+

BT1

JSD2

JSD1

I-SATA4

1

2

3

4

5

S-SGPIO1

I-SGPIO2

JPWR5

S-SATA0

DIMMF1

FAN4

S-SATA1

6

DIMME1

FAN3

DIMMD1

I-SATA5

I-SATA6

I-SATA7

FANA

FANB

54

Chapter 2: Installation

2.8 Jumper Settings

How Jumpers Work

To modify the operation of the motherboard, jumpers can be used to choose between optional

settings. Jumpers create shorts between two pins to change the function of the connector.

Pin 1 is identied with a square solder pad on the printed circuit board. See the diagram
below for an example of jumping pins 1 and 2. Refer to the motherboard layout page for
jumper locations.

Note: On two-pin jumpers, "Closed" means the jumper is on and "Open" means the
jumper is o󰀨 the pins.

Connector

Pins

Jumper

Setting

3 2 1

3 2 1

CMOS Clear

JBT1 is used to clear CMOS, which will also clear any passwords. Instead of pins, this jumper

consists of contact pads to prevent accidentally clearing the contents of CMOS.

To Clear CMOS

1. First power down the system and unplug the power cord(s).

2. Remove the cover of the chassis to access the motherboard.

3. Remove the onboard battery from the motherboard.

4. Short the CMOS pads with a metal object such as a small screwdriver for at least four
seconds.

5. Remove the screwdriver (or shorting device).

6. Replace the cover, reconnect the power cord(s), and power on the system.

Note: Clearing CMOS will also clear all passwords.

Do not use the PW_ON connector to clear CMOS.

JBT1 contact pads

55

Super X11SPG-TF User's Manual

Watchdog

Watchdog (JWD1) is a system monitor that can reboot the system when a software application
hangs. Close pins 1-2 to reset the system if an application hangs. Close pins 2-3 to generate
a non-maskable interrupt (NMI) signal for the application that hangs. Refer to the table below

for jumper settings. The Watchdog must also be enabled in the BIOS.

Watchdog

Jumper Settings

Jumper Setting Denition

Pins 1-2 Reset

Pins 2-3 NMI

Open Disabled

VGA Enable/Disable

Jumper JPG1 allows the user to enable the onboard VGA connector. The default setting is

pins 1-2 to enable the connection. Refer to the table below for jumper settings.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

2

+

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

FAN4

JPI2C1

VGA

AST2500

LEDM1

JPG1

JSTBY1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

JSD2

DIMME1

DIMMD1

FAN3

Aspeed

C621

SAN MAC

VGA Enable/Disable

Jumper Settings

Jumper Setting Denition

Pins 1-2 Enabled

Pins 2-3 Disabled

USB1

USB0

JPTG1

JPCK1

LAN2

Intel

X550

1

MH10

JD1

JP2

JWD1

JPME2

M.2-H_1 PCI-E 3.0 X4

Intel

M.2-H_2 PCI-E 3.0 X4

JP1

JBT1

CPU

IPMI CODE

BAR CODE

MAC CODE

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. Watchdog

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. VGA Enable

56

Chapter 2: Installation

JPI2C1

ME Manufacturing Mode

Close pins 2-3 of jumper JPME2 to bypass SPI ash security and force the system to operate
in the manufacturing mode, which will allow the user to ash the system rmware from a
host server for system setting modications. Refer to the table below for jumper settings.

The default setting is Normal.

Manufacturing Mode

Jumper Settings

Jumper Setting Denition

Pins 1-2 Normal

Pins 2-3 Manufacturing Mode

10Gb LAN Enable/Disable

JPTG1 allows you to enable or disable the 10Gb LAN. The default setting is Enabled.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

2

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

1

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

10Gb LAN Enable/Disable

Jumper Settings

Jumper Setting Denition

Pins 1-2 Enabled

Pins 2-3 Disabled

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. Manufacturing Mode

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. 10G LAN Enable

57

Super X11SPG-TF User's Manual

2.9 LED Indicators

LAN LEDs

Two LAN ports (LAN 1 and LAN 2) are located on the I/O back panel of the motherboard.
Each Ethernet LAN port has two LEDs. The green LED indicates activity, while the other Link

LED may be green, amber, or o󰀨 to indicate the speed of the connection. Refer to the tables

below for more information.

LAN1/2 Activity LED (Right)

LED State

Color Status Denition

Green Flashing Active

LED Color Denition

Green 10 Gbps

LAN1/2 Link LED (Left)

LED State

Yellow/Amber 1 Gbps

O󰀨 100 Mbps

Unit ID LED

A rear UID LED indicator (LE1) is located near the UID switch on the I/O back panel. This

UID indicator provides easy identication of a system unit that may need service.

UID LED

LED Indicator

LED Color Denition

Blue: On Unit Identied

2

USB0

JP2

JPME2

M.2-H_1 PCI-E 3.0 X4

JP1

CPU

LAN2

Intel

X550

MH10

M.2-H_2 PCI-E 3.0 X4

BAR CODE

1

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. LAN 1 LED

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. LAN 2 LED

3. UID LED

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

3

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

+

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

FAN4

JPI2C1

VGA

AST2500

LEDM1

JPG1

JSTBY1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

JSD2

DIMME1

DIMMD1

FAN3

Aspeed

C621

SAN MAC

USB1

JPTG1

JPCK1

JD1

JWD1

Intel

JBT1

IPMI CODE

MAC CODE

58

Chapter 2: Installation

JPI2C1

IPMI LAN LEDs

In addition to LAN1 and LAN2, an IPMI LAN is also located on the I/O back panel. The amber
LED on the right indicates activity, while the green LED on the left indicates the speed of the
connection. Refer to the table below for more information.

IPMI LAN

Activity LEDLink LED

Link (left)

IPMI LAN LEDs

Color/State Denition

Green: Solid

Amber: Solid

100 Mbps

1Gbps

Activity (Right) Amber: Blinking Active

M.2 LED

Two M.2 LEDs are located at LE3 and LE4 on the motherboard. When LE3 and LE4 are
blinking, M.2 functions normally. Refer to the table below for more information.

M.2 LED State

LED Color Denition

Green: Blinking Device Working

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

JP2

M.2-H_1 PCI-E 3.0 X4

LAN2

Intel

X550

MH10

M.2-H_2 PCI-E 3.0 X4

BAR CODE

1

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

1. Dedicated IPMI LAN LED

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

2

LE3
LE4

JP3

3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. LE3 (M.2 LED)

3. LE4 (M.2 LED)

59

Super X11SPG-TF User's Manual

JPI2C1

Onboard Power LED

The Onboard Power LED is located at LE2 on the motherboard. When this LED is on, the

system is on. Be sure to turn o󰀨 the system and unplug the power cord before removing or

installing components. Refer to the table below for more information.

Onboard Power LED Indicator

LED Color Denition

System O󰀨

O󰀨

(power cable not

connected)

Green System On

BMC Heartbeat LED

A BMC Heartbeat LED is located at LEDM1 on the motherboard. When LEDBMC is blinking,
the BMC is functioning normally. Refer to the table below for more information.

SXB1A

SXB1B PCI-E 3.0 X16

I-SATA4

I-SATA5

I-SATA6

I-SATA7

S-SGPIO1

I-SGPIO2

FANA

FANB

JUIDB1

LE1

COM2

2

CPU SLOT3 PCI-E 3.0 X16

LEDM1

JSTBY1

+

JSD2

JSD1

S-SATA0

S-SATA1

JPWR5

DIMMF1

DIMME1

FAN4

FAN3

VGA

Aspeed

AST2500

JPG1

REV: 1.01

DESIGNED IN USA

X11SPG-TF

BT1

Intel

C621

DIMMD1

SAN MAC

JPTG1

USB1

JWD1

JBT1

JPCK1

JD1

JP1

IPMI CODE

MAC CODE

USB0

JPME2

CPU

LAN2

Intel

X550

MH10

JP2

M.2-H_1 PCI-E 3.0 X4

M.2-H_2 PCI-E 3.0 X4

BAR CODE

BMC Heartbeat LED Indicator

LED Color Denition

Green:

Blinking

SXB2A

IPMI_LAN

LAN1

USB4/5(3.0)

BMC Normal

1. Onboard Power LED

USB2/3

MH12

+

JIPMB1

SP1

USB6/7(3.0)

JP4

SXB2B PCI-E 3.0 X16

USB8(3.0)

LE3
LE4

JP3

JTPM1

JNVI2C1

JRK1

FANC

FAND

JOH1

ON

JF1

BIOS LICENSE

LE2

LEDLED12LEDFAIL

NMIXPWRHDDNICNICUIDPSRSTPWR

1

DIMMB1

DIMMC1

DIMMA1

JPWR6

FAN2

FAN1

JL1

2. BMC Heartbeat LED

60

Chapter 3: Troubleshooting

Chapter 3

Troubleshooting

3.1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all of the
procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/
or ‘Returning Merchandise for Service’ section(s) in this chapter. Always disconnect the AC
power cord before adding, changing or installing any non hot-swap hardware components.

Before Power On

1. Make sure that there are no short circuits between the motherboard and chassis.

2. Disconnect all ribbon/wire cables from the motherboard, including those for the keyboard
and mouse.

3. Remove all add-on cards.

4. Install the CPU (making sure it is fully seated) and connect the front panel connectors to
the motherboard.

No Power

1. Make sure that there are no short circuits between the motherboard and the chassis.

2. Make sure that the ATX power connectors are properly connected.

3. Check that the 115V/230V switch, if available, on the power supply is properly set.

4. Turn the power switch on and o󰀨 to test the system, if applicable.

5. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.

61

Super X11SPG-TF User's Manual

No Video

1. If the power is on, but you have no video, remove all add-on cards and cables.

2. Use the speaker to determine if any beep codes are present. Refer to Appendix A for
details on beep codes.

3. Remove all memory modules and turn on the system (if the alarm is on, check the

specs of memory modules, reset the memory or try a di󰀨erent one).

System Boot Failure

If the system does not display POST (Power-On-Self-Test) or does not respond after the
power is turned on, check the following:

1. Check for any error beep from the motherboard speaker.

• If there is no error beep, try to turn on the system without DIMM modules installed. If there

is still no error beep, replace the motherboard.

• If there are error beeps, clear the CMOS settings by unplugging the power cord and con-

tacting both pads on the CMOS clear jumper (JBT1). Refer to Section 2.8 in Chapter 2.

2. Remove all components from the motherboard, especially the DIMM modules. Make
sure that system power is on and that memory error beeps are activated.

3. Turn on the system with only one DIMM module installed. If the system boots, check for
bad DIMM modules or slots by following the Memory Errors Troubleshooting procedure

in this chapter.

Memory Errors

When a no-memory beep code is issued by the system, check the following:

1. Make sure that the memory modules are compatible with the system and are properly
installed. See Chapter 2 for installation instructions. (For memory compatibility, refer
to the "Tested Memory List" link on the motherboard's product page to see a list of
supported memory.)

2. Check if di󰀨erent speeds of DIMMs have been installed. It is strongly recommended that
you use the same RAM type and speed for all DIMMs in the system.

3. Make sure that you are using the correct type of ECC DDR4 modules recommended by
the manufacturer.

4. Check for bad DIMM modules or slots by swapping a single module among all memory
slots and check the results.

62

Chapter 3: Troubleshooting

Losing the System's Setup Conguration

1. Make sure that you are using a high-quality power supply. A poor-quality power supply
may cause the system to lose the CMOS setup information. Refer to Chapter 2 for
details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.

3. If the above steps do not x the setup conguration problem, contact your vendor for
repairs.

When the System Becomes Unstable

A. If the system becomes unstable during or after OS installation, check the following:

1. CPU/BIOS support: Make sure that your CPU is supported and that you have the latest
BIOS installed in your system.

2. Memory support: Make sure that the memory modules are supported by testing the
modules using memtest86 or a similar utility.

Note: Click on the "Tested Memory List" link on the motherboard's product page to
see a list of supported memory.

3. HDD support: Make sure that all hard disk drives (HDDs) work properly. Replace the
bad HDDs with good ones.

4. System cooling: Check the system cooling to make sure that all heatsink fans and CPU/
system fans, etc., work properly. Check the hardware monitoring settings in the IPMI
to make sure that the CPU and system temperatures are within the normal range. Also
check the front panel Overheat LED and make sure that it is not on.

5. Adequate power supply: Make sure that the power supply provides adequate power to
the system. Make sure that all power connectors are connected. Please refer to our
website for more information on the minimum power requirements.

6. Proper software support: Make sure that the correct drivers are used.

B. If the system becomes unstable before or during OS installation, check the following:

1. Source of installation: Make sure that the devices used for installation are working
properly, including boot devices such as CD/DVD.

2. Cable connection: Check to make sure that all cables are connected and working
properly.

63

Super X11SPG-TF User's Manual

3. Using the minimum conguration for troubleshooting: Remove all unnecessary

components (starting with add-on cards rst), and use the minimum conguration (but

with the CPU and a memory module installed) to identify the trouble areas. Refer to the
steps listed in Section A above for proper troubleshooting procedures.

4. Identifying bad components by isolating them: If necessary, remove a component in
question from the chassis, and test it in isolation to make sure that it works properly.
Replace a bad component with a good one.

5. Check and change one component at a time instead of changing several items at the
same time. This will help isolate and identify the problem.

6. To nd out if a component is good, swap this component with a new one to see if the
system will work properly. If so, then the old component is bad. You can also install the
component in question in another system. If the new system works, the component is
good and the old system has problems.

64

Chapter 3: Troubleshooting

3.2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, please note that as
a motherboard manufacturer, Supermicro also sells motherboards through its channels, so it

is best to rst check with your distributor or reseller for troubleshooting services. They should
know of any possible problems with the specic system conguration that was sold to you.

1. Please go through the Troubleshooting Procedures and Frequently Asked Questions
(FAQ) sections in this chapter or see the FAQs on our website (http://www.supermicro.

com/FAQ/index.php) before contacting Technical Support.

2. BIOS upgrades can be downloaded from our website (http://www.supermicro.com/

ResourceApps/BIOS_IPMI_Intel.html).

3. If you still cannot resolve the problem, include the following information when contacting
Supermicro for technical support:

• Motherboard model and PCB revision number

• BIOS release date/version (This can be seen on the initial display when your system rst

boots up.)

• System conguration

4. An example of a Technical Support form is on our website at http://www.supermicro.com/

RmaForm/.

• Distributors: For immediate assistance, please have your account number ready when

placing a call to our Technical Support department. We can be reached by email at sup-

[e-mail].

65

Super X11SPG-TF User's Manual

3.3 Frequently Asked Questions

Question: What type of memory does my motherboard support?

Answer: The motherboard supports DDR4 ECC RDIMM, LRDIMM, or 3DS LRDIMM modules.

To enhance memory performance, do not mix memory modules of di󰀨erent speeds and sizes.

Please follow all memory installation instructions given on Section 2-4 in Chapter 2.

Question: How do I update my BIOS?

Answer: It is recommended that you do not upgrade your BIOS if you are not experiencing

any problems with your system. Updated BIOS les are located on our website at http://

www.supermicro.com/ResourceApps/BIOS_IPMI_Intel.html. Please check our BIOS warning

message and the information on how to update your BIOS on our website. Select your

motherboard model and download the BIOS le to your computer. Also, check the current

BIOS revision to make sure that it is newer than your BIOS before downloading. Please

unzip the BIOS le onto a bootable USB device. Run the batch le using the format FLASH.
BAT lename.rom from your bootable USB device to ash the BIOS. Then, your system will

automatically reboot.

Warning: Do not shut down or reset the system while updating the BIOS to prevent possible
system boot failure!

Note: The SPI BIOS chip used on this motherboard cannot be removed. Send your
motherboard back to our RMA Department at Supermicro for repair. For BIOS Recovery
instructions, please refer to the AMI BIOS Recovery Instructions posted at http://www.

supermicro.com/support/manuals/.

66

Chapter 3: Troubleshooting

3.4 Battery Removal and Installation

Battery Removal

To remove the onboard battery, follow the steps below:

1. Power o󰀨 your system and unplug your power cable.

2. Using a tool such as a pen or a small screwdriver, push the battery lock outwards to
unlock it. Once unlocked, the battery will pop out from the holder.

3. Remove the battery.

Proper Battery Disposal

Warning: Please handle used batteries carefully. Do not damage the battery in any way; a

damaged battery may release hazardous materials into the environment. Do not discard a used

battery in the garbage or a public landll. Please comply with the regulations set up by your

local hazardous waste management agency to dispose of your used battery properly.

Battery Installation

1. To install an onboard battery, follow steps 1 and 2 above and continue below:

2. Identify the battery's polarity. The positive (+) side should be facing up.

3. Insert the battery into the battery holder and push it down until you hear a click to
ensure that the battery is securely locked.

Warning: When replacing a battery, be sure to only replace it with the same type.

OR

67

Super X11SPG-TF User's Manual

3.5 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required before any
warranty service will be rendered. You can obtain service by calling your vendor for a
Returned Merchandise Authorization (RMA) number. When returning the motherboard to
the manufacturer, the RMA number should be prominently displayed on the outside of the
shipping carton, and the shipping package is mailed prepaid or hand-carried. Shipping and
handling charges will be applied for all orders that must be mailed when service is complete.
For faster service, you can also request a RMA authorization online (http://www.supermicro.

com/RmaForm/).

This warranty only covers normal consumer use and does not cover damages incurred in
shipping or from failure due to the alternation, misuse, abuse or improper maintenance of
products.

During the warranty period, contact your distributor rst for any product problems.

68

Chapter 4: BIOS

Chapter 4

UEFI BIOS

4.1 Introduction

This chapter describes the AMIBIOS™ Setup utility for the motherboard. The BIOS is stored

on a chip and can be easily upgraded using a ash program.

Note: Due to periodic changes to the BIOS, some settings may have been added
or deleted and might not yet be recorded in this manual. Please refer to the Manual

Download area of our website for any changes to the BIOS that may not be reected

in this manual.

Starting the Setup Utility

To enter the BIOS Setup Utility, hit the <Delete> key while the system is booting-up. (In
most cases, the <Delete> key is used to invoke the BIOS setup screen. There are a few
cases when other keys are used, such as <F1>, <F2>, etc.) Each main BIOS menu option
is described in this manual.

The Main BIOS screen has two main frames. The left frame displays all the options that can

be congured. “Grayed-out” options cannot be congured. The right frame displays the key

legend. Above the key legend is an area reserved for a text message. When an option is
selected in the left frame, it is highlighted in white. Often a text message will accompany it.
(Note that the BIOS has default text messages built in. We retain the option to include, omit,
or change any of these text messages.) Settings printed in Bold are the default values.

A " " indicates a submenu. Highlighting such an item and pressing the <Enter> key will
open the list of settings within that submenu.

The BIOS setup utility uses a key-based navigation system called hot keys. Most of these
hot keys (<F1>, <F2>, <F3>, <Enter>, <ESC>, <Arrow> keys, etc.) can be used at any time
during the setup navigation process.

69

Super X11SPG-TF User's Manual

4.2 Main Setup

When you rst enter the AMI BIOS setup utility, you will enter the Main setup screen. You can

always return to the Main setup screen by selecting the Main tab on the top of the screen.
The Main BIOS setup screen is shown below and the following items will be displayed:

System Date/System Time

Use this option to change the system date and time. Highlight System Date or System Time
using the arrow keys. Enter new values using the keyboard. Press the <Tab> key or the arrow

keys to move between elds. The date must be entered in MM/DD/YYYY format. The time

is entered in HH:MM:SS format.

Note: The time is in the 24-hour format. For example, 5:30 P.M. appears as 17:30:00.
The date's default value is the BIOS build date after RTC reset.

Supermicro X11SPG-TF

BIOS Version

This item displays the version of the BIOS ROM used in the system.

Build Date

This item displays the date when the version of the BIOS ROM used in the system was built.

70

CPLD Version

This item displays the Complex Programmable Logic Device version.

Memory Information

Total Memory

This item displays the total size of memory available in the system.

Chapter 4: BIOS

71

Super X11SPG-TF User's Manual

4.3 Advanced Setup Congurations

Use the arrow keys to select the Advanced menu and press <Enter> to access the submenu
items:

Warning: Take caution when changing the Advanced settings. An incorrect value, a very high
DRAM frequency, or an incorrect DRAM timing setting may make the system unstable. When
this occurs, revert to default manufacturer settings.

Boot Feature

Quiet Boot

Use this feature to select the screen display between the POST messages and the OEM logo
upon bootup. Select Disabled to display the POST messages. Select Enabled to display the
OEM logo instead of the normal POST messages. The options are Disabled and Enabled.

Option ROM Messages

Use this feature to set the display mode for the Option ROM. Select Keep Current to display
the current AddOn ROM setting. Select Force BIOS to use the Option ROM display set by
the system BIOS. The options are Force BIOS and Keep Current.

Bootup NumLock State

Use this feature to set the Power-on state for the <Numlock> key. The options are On and O󰀨.

72

Chapter 4: BIOS

Wait For "F1" If Error

Use this feature to force the system to wait until the "F1" key is pressed if an error occurs.
The options are Disabled and Enabled.

INT19 (Interrupt 19) Trap Response

Interrupt 19 is the software interrupt that handles the boot disk function. When this item is
set to Immediate, the ROM BIOS of the host adapters will "capture" Interrupt 19 at bootup
immediately and allow the drives that are attached to these host adapters to function as
bootable disks. If this item is set to Postponed, the ROM BIOS of the host adapters will not
capture Interrupt 19 immediately and allow the drives attached to these adapters to function
as bootable devices at bootup. The options are Immediate and Postponed.

Re-try Boot

If this item is enabled, the BIOS will automatically reboot the system from a specied boot

device after its initial boot failure. The options are Disabled, Legacy Boot, and EFI Boot.

Install Windows 7 USB Support

Enable this feature to use the USB keyboard and mouse during the Windows 7 installation
since the native XHCI driver support is unavailable. Use a SATA optical drive as a USB drive.
USB CD/DVD drives are not supported. Disable this feature after the XHCI driver has been
installed in Windows. The options are Disabled and Enabled.

Port 61h Bit-4 Emulation

Select Enabled to enable the emulation of Port 61h bit-4 toggling in SMM (System Management
Mode). The options are Disabled and Enabled.

Power Conguration

Watch Dog Function

If enabled, the Watch Dog Timer will allow the system to reset or generate NMI based on
jumper settings when it is expired for more than ve minutes. The options are Disabled and
Enabled.

Restore on AC Power Loss

Use this feature to set the power state after a power outage. Select Stay Off for

the system power to remain o󰀨 after a power loss. Select Power On for the system

power to be turned on after a power loss. Select Last State to allow the system to
resume its last power state before a power loss. The options are Stay O󰀨, Power On,
and Last State.

73

Super X11SPG-TF User's Manual

Power Button Function

This feature controls how the system shuts down when the power button is pressed. Select 4

Seconds Override for the user to power o󰀨 the system after pressing and holding the power
button for 4 seconds or longer. Select Instant O󰀨 to instantly power o󰀨 the system as soon

as the user presses the power button. The options are Instant O󰀨 and 4 Seconds Override.

CPU Conguration

The following CPU information will display:

• Processor BSP Revision

• Processor Socket

• Processor ID

• Processor Frequency

• Processor Max Ratio

• Processor Min Ratio

• Microcode Revision

• L1 Cache RAM

• L2 Cache RAM

• L3 Cache RAM

• Processor 0 Version

Hyper-Threading (ALL) (Available when supported by the CPU)

Select Enable to support Intel Hyper-threading Technology to enhance CPU performance.
The options are Disable and Enable.

Cores Enabled

Set a numeric value to enable the number of cores. (Please refer to the Intel website for more
information.) Enter 0 to enable all cores.

Monitor/MWAIT

Select Enabled to enable the Monitor/Mwait instructions. The Monitor instructions monitors a
region of memory for writes, and Mwait instructions instruct the CPU to stop until the monitored
region begins to write. The options are Auto, Disable, and Enable.

74

Chapter 4: BIOS

Execute Disable Bit (Available if supported by the OS & the CPU)

Select Enable to enable the Execute-Disable Bit, which will allow the processor to designate
areas in the system memory where an application code can execute and where it cannot,

thus preventing a worm or virus from ooding illegal codes to overwhelm the processor or

damage the system during an attack. The options are Disable and Enable. (Refer to the
Intel® and Microsoft® websites for more information.)

Intel Virtualization Technology

Use this feature to enable the Vanderpool Technology. This technology allows the system to
run several operating systems simultaneously. The options are Disable and Enable.

PPIN Control

Select Unlock/Enable to use the Protected Processor Inventory Number (PPIN) in the system.
The options are Unlock/Disable and Unlock/Enable.

Hardware Prefetcher (Available when supported by the CPU)

If set to Enable, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Disable
and Enable.

Adjacent Cache Prefetch (Available when supported by the CPU)

The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enable. The
options are Enable and Disable.

DCU Streamer Prefetcher (Available when supported by the CPU)

Select Enable to enable the DCU (Data Cache Unit) Streamer Prefetcher which will stream
and prefetch data and send it to the Level 1 data cache to improve data processing and
system performance. The options are Disable and Enable.

DCU IP Prefetcher (Available when supported by the CPU)

Select Enable for DCU (Data Cache Unit) IP Prefetcher support, which will prefetch IP
addresses to improve network connectivity and system performance. The options are Enable
and Disable.

LLC Prefetch

If set to Enable, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L3 cache to improve CPU performance. The options are Disable
and Enable.

Extended APIC

Select Enable to activate APIC (Advanced Programmable Interrupt Controller) support. The
options are Disable and Enable.

75

Super X11SPG-TF User's Manual

AES-NI

Select Enable to use the Intel Advanced Encryption Standard (AES) New Instructions (NI) to
ensure data security. The options are Disable and Enable.

Advanced Power Management Conguration

Power Technology

This feature allows the user to congure CPU power management settings. The options

are Disable, Energy E󰀩cient, and Custom.

*If the item above is set to Custom, the following items will be displayed:

Power Performance Tuning

This feature allows the user to set whether the operating system or the BIOS controls
the Energy Performance BIAS (EPB). The options are OS Controls EPB and BIOS
Controls EPB.

*If the item above is set to BIOS Controls EPB, the following item will be displayed:

ENERGY_PERF_BIAS_CFG Mode

The Energy Perfomance BIAS (EPB) feature allows the user to congure CPU power

and perfomance settings. Select Maximum Performance to set the highest performance.

Select Performance to optimize performance over energy e󰀩ciecy. Select Balanced

Perfomance to priortize performance optimization while conserving energy. Select Bal­anced Power to prioritize energy conservation while maintaining good performance.

Select Power to optimize energy e󰀩cency over performance. The options are Maximum

Performance, Performance, Balanced Performance, Balanced Power, and Power.

CPU P State Control

This feature allows the user to congure the following CPU power settings:

SpeedStep (Pstates)

Intel SpeedStep Technology allows the system to automatically adjust processor voltage

and core frequency to reduce power consumption and heat dissipation. The options are
Disable and Enable.

76

Chapter 4: BIOS

EIST PSD Funtion

This feature allows the user to choose between Hardware and Software to control the
processor's frequency and performance (P-state). In HW_ALL mode, the processor hard­ware is responsible for coordinating the P-state, and the OS is responsible for keeping the
P-state request up to date on all Logical Processors. In SW_ALL mode, the OS Power
Manager is responsible for coordinating the P-state, and must initiate the transition on
all Logical Processors. In SW_ANY mode, the OS Power Manager is responsible for
coordinating the P-state and may initiate the transition on any Logical Processors. The
options are HW_ALL, SW_ALL, and SW_ANY.

Turbo Mode

This feature will enable dynamic control of the processor, allowing it to run above stock
frequency. The options are Disable and Enable.

Hardware PM State Control

Hardware P-States

This setting allows the user to select between OS and hardware-controlled P-states.
Selecting Native Mode allows the OS to choose a P-state. Selecting Out of Band Mode
allows the hardware to autonomously choose a P-state without OS guidance. Selecting
Native Mode with No Legacy Support functions as Native Mode with no support for older
hardware. The options are Disable, Native Mode, Out of Band Mode, and Native Mode
with No Legacy Support.

CPU C State Control

Autonomous Core C-State

Enabling this setting allows the hardware to autonomously choose to enter a C-state
based on power consumption and clock speed. The options are Disable and Enable.

CPU C6 Report

Select Enable to allow the BIOS to report the CPU C6 State (ACPI C3) to the operating

system. During the CPU C6 State, the power to all cache is turned o󰀨. The options are

Disable, Enable, and Auto.

Enhanced Halt State (C1E)

Select Enable to use Enhanced Halt State technology, which will signicantly reduce the

CPU's power consumption by reducing its clock cycle and voltage during a Halt state.
The options are Disable and Enable.

77

Super X11SPG-TF User's Manual

Package C State Control

Package C State

This feature allows the user to set the limit on the C State package register. The options
are C0/C1 State, C2 State, C6 (Non Retention) State, C6 (Retention) State, No Limit,
and Auto.

CPU T State Control

Software Controlled T-States

Use this feature to enable Software Controlled T-States. The options are Disable and
Enable.

Chipset Conguration

Warning: Setting the wrong values in the following features may cause the system to malfunc­tion.

North Bridge

This feature allows the user to congure the following North Bridge settings.

UPI Conguration

The following UPI information will display:

• Number of CPU

• Number of Active UPI Link

• Current UPI Link Speed

• Current UPI Link Frequency

• UPI Global MMIO Low Base / Limit

• UPI Global MMIO High Base / Limit

• UPI Pci-e Conguration Base / Size

Degrade Precedence

Use this feature to set degrade precedence when system settings are in conict. Select

Topology Precedence to degrade Features. Select Feature Precedence to degrade Topol­ogy. The options are Topology Precedence and Feature Precedence.

78

Chapter 4: BIOS

Link L0p Enable

Select Enable for the QPI to enter the L0p state for power saving. The options are Dis­able, Enable, and Auto.

Link L1 Enable

Select Enable for the QPI to enter the L1 state for power saving. The options are Dis­able, Enable, and Auto.

IO Directory Cache (IODC)

IO Directory Cache is an 8-entry cache that stores the directory state of remote IIO writes
and memory lookups, and saves directory updates. Use this feature to lower cache to
cache (C2C) transfer latencies. The options are Disable, Auto, Enable for Remote InvItoM
Hybrid Push, InvItoM AllocFlow, Enable for Remote InvItoM Hybrid AllocNonAlloc, and
Enable for Remote InvItoM and Remote WViLF.

SNC

Sub NUMA Clustering (SNC) is a feature that breaks up the Last Level Cache (LLC) into
clusters based on address range. Each cluster is connected to a subset of the memory
controller. Enabling SNC improves average latency and reduces memory access conges­tion to achieve higher performance. Select Auto for 1-cluster or 2-clusters depending on
IMC interleave. Select Enable for Full SNC (2-clusters and 1-way IMC interleave). The
options are Disable, Enable, and Auto.

XPT Prefetch

XPT Prefetch is a feature that speculatively makes a copy to the memory controller of
a read request being sent to the LLC. If the read request maps to the local memory ad­dress and the recent memory reads are likely to miss the LLC, a speculative read is sent
to the local memory controller. The options are Disable and Enable.

KTI Prefetch

KTI Pretech is a feature that enables memory read to start early on a DDR bus, where
the KTI Rx path will directly create a Memory Speculative Read command to the memory
controller. The options are Disable and Enable.

Locate/Remote Threshold

This feature allows the user to set the threshold for the Interrupt Request (IRQ) signal,
which handles hardware interruptions. The options are Disable, Auto, Low, Medium,
and High.

79

Super X11SPG-TF User's Manual

Stale AtoS

This feature optimizes A to S directory. When all snoop responses found in directory A
are found to be RspI, then all data is moved to directory S and is returned in S-state.
The options are Disable, Enable, and Auto.

LLC Dead Line Alloc

Select Enable to optimally ll dead lines in LLC. Select Disable to never ll dead lines in

LLC. The options are Disable, Enable, and Auto.

Isoc Mode

Isochronous (Isoc) mode allows time-sensitive processes to be given priority. The options
are Disable, Enable, and Auto.

Memory Conguration

Enforce POR

Select POR (Plan of Record) to enforce POR restrictions on DDR4 frequency and volt­age programming. The options are POR and Disable.

PPR Type

Use this feature to set the Post Package Repair type. The options are Auto, Hard PPR,
Soft PPR, and PPR Disabled.

Memory Frequency

Use this feature to set the maximum memory frequency for onboard memory modules.
The options are Auto, 1866, 2000, 2133, 2400, 2600, 2666, and 2933.

Data Scrambling for DDR4

Use this feature to enable or disable data scrambling for DDR4 memory. The options
are Auto, Disable, and Enable.

tCCD_L Relaxation

Select Auto to get TCDD settings from SPD (Serial Presence Detect) and implement into
memory RC code to improve system reliability. Select Disable for TCCD to follow Intel
POR. The options are Disable and Auto.

2X REFRESH

Use this feature to select the memory controller refresh rate to 2x refresh mode. The
options are Auto and Enable.

80

Chapter 4: BIOS

Page Policy

This feature allows the user to determine the desired page mode for IMC. When Auto is
selected, the memory controller will close or open pages based on the current operation.
Closed policy closes that page after reading or writing. Adaptive is similar to open page

policy, but can be dynamically modied. The options are Auto, Closed, and Adaptive.

IMC Interleaving

This feature allows the user to congure Integrated Memory Controller (IMC) Interleaving

settings. The options are Auto, 1-way Interleave, and 2-way Interleave.

Memory Topology

This item displays the information of onboard memory modules as detected by the
BIOS.

Memory RAS Conguration

Static Virtual Lockstep Mode

Select Enable to run the system's memory channels in lockstep mode to minimize
memory access latency. The options are Disable and Enable.

Mirror Mode

This feature allows memory to be mirrored between two channels, providing 100%
redundancy. The options are Disable, Mirror Mode 1LM, and Mirror Mode 2LM.

Memory Rank Sparing

Select Enable to enable memory-sparing support for memory ranks to improve memory
performance. The options are Disable and Enable.

Correctable Error Threshold

Use this item to specify the threshold value for correctable memory error logging, which
sets a limit on the maximum number of events that can be logged in the memory error
log at a given time. The default setting is 100.

Intel Run Sure

Use this feature to enable Intel Run Sure technology. The options are Disable and
Enable.

81

Super X11SPG-TF User's Manual

SDDC Plus One

Single device data correction +1 (SDDC Plus One) organizes data in a single bundle
(x4/x8 DRAM). If any or all the bits become corrupted, corrections occur. The x4 con­dition is corrected on all cases. The x8 condition is corrected only if the system is in
Lockstep Mode. The options are Disable and Enable.

ADDDC Sparing

Adaptive Double Device Data Correction (ADDDC) Sparing detects when the prede­termined threshold for correctable errors is reached, copying the contents of the failing
DIMM to spare memory. The failing DIMM or memory rank will then be disabled. The
options are Disable and Enable.

Patrol Scrub

Patrol Scrub is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this item is set to Enable, the IO hub will read and write back one cache
line every 16K cycles if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub will be scrubbed every day. The
options are Disable and Enable.

Patrol Scrub Interval

This feature allows you to decide how many hours the system should wait before the
next complete patrol scrub is performed. Use the keyboard to enter a value from 0-24.
The default setting is 24.

IIO Conguration

EV DFX Features

When this feature is set to Enable, the EV_DFX Lock Bits that are located on a proces­sor will always remain clear during electric tuning. The options are Disable and Enable.

CPU1 Conguration

IOU0 (II0 PCIe Br1)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU1 (II0 PCIe Br2)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

82

Chapter 4: BIOS

IOU2 (II0 PCIe Br3)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

CPU1 SLOT4 PCI-E 3.0 X16

Link Speed

Use this item to select the link speed for the PCI-E port specied by the user. The

options are Auto, Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

The following information will also be displayed:

• PCI-E Port Link Status

• PCI-E Port Link Max

• PCI-E Port Link Speed

PCI-E Port Max Payload Size

Selecting Auto for this feature will enable the motherboard to automatically detect
the maximum Transaction Layer Packet (TLP) size for the connected PCI-E device,

allowing for maximum I/O e󰀩ciency. Selecting 128B or 256B will designate maximum

packet size of 128 or 256. The options are 128B, 256B, and Auto.

IOAT Conguration

Disable TPH

Transparent Huge Pages (TPH) is a Linux memory management system that enables
communication in larger blocks (pages). Enabling this feature will increase perfor­mance. The options are No and Yes.

Prioritize TPH

Use this feature to enable Prioritize TPH support. The options are Enable and Disable.

Relaxed Ordering

Select Enable to enable Relaxed Ordering support, which will allow certain transac­tions to violate the strict-ordering rules of PCI bus for a transaction to be completed
prior to other transactions that have already been enqueued. The options are Disable
and Enable.

83

Super X11SPG-TF User's Manual

Intel® VT for Directed I/O (VT-d)

Intel® VT for Directed I/O (VT-d)

Select Enable to use Intel Virtualization Technology for Direct I/O VT-d support by
reporting the I/O device assignments to the VMM (Virtual Machine Monitor) through

the DMAR ACPI tables. This feature o󰀨ers fully-protected I/O resource sharing across

Intel platforms, providing greater reliability, security and availability in networking and
data-sharing. The options are Enable and Disable.

ACS Control

Select Enable for Access Control Services (ACS) extended capability support to en­hance system performance. The options are Enable and Disable.

Interrupt Remapping

Use this feature to enable Interrupt Remapping support, which detects and controls
external interrupt requests. The options are Enable and Disable.

PassThrough DMA

Use this feature to allow devices such as network cards to access the system memory
without using a processor. Select Enable to use the Non-Isoch VT_D Engine Pass
Through Direct Memory Access (DMA) support. The options are Enable and Disable.

ATS

Use this feature to enable Non-Isoch VT-d Engine Address Translation Services (ATS)
support. ATS translates virtual addresses to physical addresses. The options are En-

able and Disable.

Posted Interrupt

Use this feature to enable VT_D Posted Interrupt. The options are Enable and Disable.

Coherency Support (Non-Isoch)

Use this feature to maintain setting coherency between processors or other devices.
Select Enable for the Non-Isoch VT-d engine to pass through DMA to enhance system
performance. The options are Enable and Disable.

Intel® VMD Technology

Note: After you’ve enabled VMD on a PCI-E slot of your choice, this PCI-E slot
will be dedicated for NVMe storage devices use only, and it will no longer sup­port PCI-E devices of other functionalities. To re-activate this slot for PCI-E use,
please disable VMD.

84

Chapter 4: BIOS

Intel® VMD for Volume Management Device on CPU

VMD Cong for PStack0

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

*If the item above is set to Enable, the following items will be available for

conguration:

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 1A~1D. The options
are Disable and Enable.

VMD Cong for PStack1

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

*If the item above is set to Enable, the following items will be available for

conguration:

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 2A~2D. The options
are Disable and Enable.

VMD Cong for PStack2

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

*If the item above is set to Enable, the following items will be available for

conguration:

CPU SLOT3 PCI-E 3.0 x16 VMD (Available when the device is detected by the
system)

Select Enable to use the Intel Volume Management Device Technology for this spe-

cic root port. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 3A~3D. The options
are Disable and Enable.

85

Super X11SPG-TF User's Manual

PCI-E Completion Timeout Disable

Use this feature to enable PCI-E Completion Timeout support for electric tuning. The
options are Yes, No, and Per-Port.

South Bridge

The following USB information will display:

• USB Module Version

• USB Devices

Legacy USB Support

This feature enables support for USB 2.0 and older. The options are Enabled, Disabled,
and Auto.

XHCI Hand-o󰀨

When this feature is disabled, the motherboard will not support USB 3.0. The options are

Enabled and Disabled.

Port 60/64 Emulation

This feature allows legacy I/O support for USB devices like mice and keyboards. The options
are Enabled and Disabled.

PCIE PLL SSC

Use this feature to enable PCI-E phase-locked loop (PLL) spread spectrum clocking (SSC).
The options are Disable and Enable.

Server ME Conguration

The following General ME Conguration will display:

• Oper. Firmware Version

• Backup Firmware Version

• Recovery Firmware Version

• ME Firmware Status #1

• ME Firmware Status #2

• Current State

• Error Code

86

Chapter 4: BIOS

PCH SATA Conguration

When this submenu is selected, the AMI BIOS automatically detects the presence of the SATA
devices that are supported by the Intel PCH chip and displays the following items:

SATA Controller

This item enables or disables the onboard SATA controller supported by the Intel PCH chip.
The options are Disable and Enable.

Congure SATA as

Select AHCI to congure a SATA drive specied by the user as an AHCI drive. Select RAID
to congure a SATA drive specied by the user as a RAID drive. The options are AHCI and

RAID.

SATA HDD Unlock

This feature allows the user to remove any password-protected SATA disk drives. The options
are Enable and Disable.

Aggressive Link Power Management

When this item is set to Enable, the SATA AHCI controller manages the power usage of the
SATA link. The controller will put the link in a low power mode during extended periods of I/O
inactivity, and will return the link to an active state when I/O activity resumes. The options
are Disable and Enable.

*If the item "Congure SATA as" above is set to RAID, the following items will be avail­able for conguration:

SATA RSTe Boot Info

Select Enable to provide full int13h support for the devices attached to SATA controller. The
options are Disable and Enable.

SATA RAID Option ROM/UEFI Driver

Select UEFI to load the EFI driver for system boot. Select Legacy to load a legacy driver for
system boot. The options are Disable, EFI, and Legacy.

SATA Port 0/4/5/6/7

This item displays the information detected on the installed SATA drive on the particular SATA
port.

• Model number of drive and capacity

• Software Preserve Support

87

Super X11SPG-TF User's Manual

Port 0/4/5/6/7 Hot Plug

Set this item to Enable for hot plug support, which will allow the user to replace a SATA
drive without shutting down the system. The options are Disable and Enable.

Port 0/4/5/6/7 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to initialize the device. The
options are Disable and Enable.

Port 0/4/5/6/7 SATA Device Type

Use this item to specify if the SATA port specied by the user should be connected to a Solid

State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid State Drive.

PCH sSATA Conguration

When this submenu is selected, the AMI BIOS automatically detects the presence of the SATA
devices that are supported by the Intel PCH chip and displays the following items:

sSATA Controller

This item enables or disables the onboard sSATA controller supported by the Intel PCH chip.
The options are Enable and Disable.

Congure sSATA as

Select AHCI to congure an sSATA drive specied by the user as an AHCI drive. Select RAID
to congure an sSATA drive specied by the user as a RAID drive. The options are AHCI

and RAID.

SATA HDD Unlock

This feature allows the user to remove any password-protected SATA disk drives. The options
are Disable and Enable.

Aggressive Link Power Management

When this item is set to Enable, the SATA AHCI controller manages the power usage of the
SATA link. The controller will put the link in a low power mode during extended periods of I/O
inactivity, and will return the link to an active state when I/O activity resumes. The options
are Disable and Enable.

*If the item "Congure sSATA as" above is set to RAID, the following items will display:

sSATA RSTe Boot Info

Select Enable to provide full int13h support for the devices attached to sSATA controller. The

options are Disable and Enable.

88

Chapter 4: BIOS

sSATA RAID Option ROM/UEFI Driver

Select UEFI to load the EFI driver for system boot. Select Legacy to load a legacy driver for
system boot. The options are Disable, EFI, and Legacy.

sSATA Port 0 ~ Port 2

This item displays the information detected on the installed sSATA drive on the particular
sSATA port.

• Model number of drive and capacity

• Software Preserve Support

Port 0 ~ Port 2 Hot Plug

Set this item to Enable for hot plug support, which will allow the user to replace a SATA
drive without shutting down the system. The options are Disable and Enable.

Port 0 ~ Port 2 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to initialize the device. The
options are Disable and Enable.

Port 0 ~ Port 2 sSATA Device Type

Use this item to specify if the SATA port specied by the user should be connected to a Solid

State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid State Drive.

PCIe/PCI/PnP Conguration

The following information will display:

• PCI Bus Driver Version

• PCI Devices Common Settings:

Above 4G Decoding (Available if the system supports 64-bit PCI decoding)

Select Enabled to decode a PCI device that supports 64-bit in the space above 4G Address.
The options are Disabled and Enabled.

SR-IOV Support

Use this feature to enable or disable Single Root IO Virtualization Support. The options are

Disabled and Enabled.

MMIO High Base

Use this item to select the base memory size according to memory-address mapping for the
IO hub. The options are 56T, 40T, 24T, 16T, 4T, 2T, and 1T.

89

Super X11SPG-TF User's Manual

MMIO High Granularity Size

Use this item to select the high memory size according to memory-address mapping for the
IO hub. The options are 1G, 4G, 16G, 64G, 256G, and 1024G.

Maximum Read Request

Use this item to select the Maximum Read Request size of the PCI-Express device, or select
Auto to allow the System BIOS to determine the value. The options are Auto, 128 Bytes, 256
Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.

MMCFG Base

Use this item to select the low base address for PCIE adapters to increase base memory.
The options are 1G, 1.5G, 1.75G, 2G, 2.25G. and 3G.

NVMe Firmware Source

Use this item to select the NVMe rmware to support booting. The options are Vendor

Dened Firmware and AMI Native Support. The default option, Vendor Dened Firmware,

is pre-installed on the drive and may resolve errata or enable innovative functions for the

drive. The other option, AMI Native Support, is o󰀨ered by the BIOS with a generic method.

VGA Priority

Use this feature to select VGA priority when multiple VGA devices are detected. Select On-

board to give priority to your onboard video device. Select O󰀨board to give priority to your

graphics card. The options are Onboard and O󰀨board.

M.2-H_1 PCI-E 3.0 x4 OPROM

Use this feature to select which rmware type to be loaded for the add-on card in this slot.

The options are Disabled, Legacy, and EFI.

M.2-H_2 PCI-E 3.0 x4 OPROM

Use this feature to select which rmware type to be loaded for the add-on card in this slot.

The options are Disabled, Legacy, and EFI.

CPU SLOT3 PCI-E 3.0 x16 OPROM

Use this feature to select which rmware type to be loaded for the add-on card in this slot.

The options are Disabled, Legacy, and EFI.

Bus Master Enable

This feature enables a device connected to the bus to intiate Direct Memory Access (DMA)
transactions. When DIsabled is selected, the PCI Bus Driver disables Bus Master Attribute
for Pre-Boot DMA Protection. When Enabled is selected, the PCI Bus Driver enables BUs
Master Atribute for DMA transactions. Some devices request Bus Master to be enabled for
operations. The options are Disabled and Enabled.

90

Chapter 4: BIOS

Onboard LAN Device

Select Enabled to enable the Onboard LAN device. The options are Enabled and Disabled.

Onboard LAN1 Option ROM

Use this feature to select which rmware function to be loaded for LAN Port1 used for system

boot. The options are Disabled, Legacy, and EFI.

Onboard LAN2 Option ROM

Use this feature to select which rmware function to be loaded for LAN Port2 used for system

boot. The options are Disabled, Legacy, and EFI.

Onboard Video Option ROM

Use this item to select the Onboard Video Option ROM type. The options are Disabled,
Legacy, and EFI.

Network Stack Conguration

Network Stack

Select Enabled to enable PXE (Preboot Execution Environment) or UEFI (Unied Extensible

Firmware Interface) for network stack support. The options are Enabled and Disabled.

IPv4 PXE Support

Select Enabled to enable IPv4 PXE boot support. The options are Disabled and Enabled.

IPv4 HTTP Support

Select Enabled to enable IPv4 HTTP boot support. The options are Disabled and Enabled.

IPv6 PXE Support

Select Enabled to enable IPv6 PXE boot support. The options are Disabled and Enabled.

IPv6 HTTP Support

Select Enabled to enable IPv6 HTTP boot support. The options are Disabled and Enabled.

PXE Boot Wait Time

Use this option to specify the wait time to press the ESC key to abort the PXE boot. Press
"+" or "-" on your keyboard to change the value. The default setting is 0.

Media Detect Count

Use this option to specify the number of times media will be checked. Press "+" or "-" on
your keyboard to change the value. The default setting is 1.

91

Super X11SPG-TF User's Manual

Super IO Conguration

The following Super IO information will display:

• Super IO Chip AST2500

Serial Port 1 Conguration

This submenu allows the user to congure the settings of Serial Port 1.

Serial Port 1

Select Enabled to enable the selected onboard serial port. The options are Disabled and

Enabled.

Device Settings

This item displays the status of a serial part specied by the user.

Change Settings

This feature species the base I/O port address and the Interrupt Request address of a
serial port specied by the user. Select Auto to allow the BIOS to automatically assign the

base I/O and IRQ address.

The options for Serial Port 1 are Auto, (IO=2F8h; IRQ=3;), (IO=3F8h; IRQ=3;), (IO=3E8h;
IRQ=3;), and (IO=2E8h; IRQ=3;).

Serial Port 1 Attribute

Select SOL to use COM Port 1 as a Serial Over LAN (SOL) port for console redirection.
The options are SOL and COM.

Serial Port Console Redirection

SOL/COM1 Console Redirection

Select Enabled to enable console redirection support for a serial port specied by the user.

The options are Enabled and Disabled.

*If the item above is set to Enabled, the following items will become available for

conguration:

SOL/COM1 Console Redirection Settings

Use this feature to specify how the host computer will exchange data with the client
computer, which is the remote computer used by the user.

92

Chapter 4: BIOS

Terminal Type

This feature allows the user to select the target terminal emulation type for Console
Redirection. Select VT100 to use the ASCII Character set. Select VT100+ to add color
and function key support. Select ANSI to use the Extended ASCII Character Set. Select
VT-UTF8 to use UTF8 encoding to map Unicode characters into one or more bytes. The
options are VT100, VT100+, VT-UTF8, and ANSI.

Bits Per Second

Use this feature to set the transmission speed for a serial port used in Console Redirection.
Make sure that the same speed is used in the host computer and the client computer. A
lower transmission speed may be required for long and busy lines. The options are 9600,
19200, 38400, 57600 and 115200 (bits per second).

Data Bits

Use this feature to set the data transmission size for Console Redirection. The options are
7 Bits and 8 Bits.

Parity

A parity bit can be sent along with regular data bits to detect data transmission errors. Select
Even if the parity bit is set to 0, and the number of 1's in data bits is even. Select Odd if
the parity bit is set to 0, and the number of 1's in data bits is odd. Select None if you do
not want to send a parity bit with your data bits in transmission. Select Mark to add a mark
as a parity bit to be sent along with the data bits. Select Space to add a Space as a parity
bit to be sent with your data bits. The options are None, Even, Odd, Mark, and Space.

Stop Bits

A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard serial
data communication. Select 2 Stop Bits if slower devices are used. The options are 1 and 2.

Flow Control

Use this feature to set the ow control for Console Redirection to prevent data loss caused
by bu󰀨er overow. Send a "Stop" signal to stop sending data when the receiving bu󰀨er
is full. Send a "Start" signal to start sending data when the receiving bu󰀨er is empty. The

options are None and Hardware RTS/CTS.

VT-UTF8 Combo Key Support

Select Enabled to enable VT-UTF8 Combination Key support for ANSI/VT100 terminals.
The options are Disabled and Enabled.

93

Super X11SPG-TF User's Manual

Recorder Mode

Select Enabled to capture the data displayed on a terminal and send it as text messages
to a remote server. The options are Disabled and Enabled.

Resolution 100x31

Select Enabled for extended-terminal resolution support. The options are Disabled and

Enabled.

Legacy OS Redirection Resolution

Use this feature to select the number of rows and columns used in Console Redirection
for legacy OS support. The options are 80x24 and 80x25.

Putty KeyPad

This feature selects the settings for Function Keys and KeyPad used for Putty, which
is a terminal emulator designed for the Windows OS. The options are VT100, LINUX,
XTERMR6, SC0, ESCN, and VT400.

Redirection After BIOS POST

Use this feature to enable or disable legacy console redirection after BIOS POST. When
set to BootLoader, legacy console redirection is disabled before booting the OS. When set
to Always Enable, legacy console redirection remains enabled when booting the OS. The
options are Always Enable and BootLoader.

Legacy Console Redirection

Legacy Serial Redirection Port

Use this feature to select a COM port to display redirection of Legacy OS and Legacy OPROM
messages. The default option is SOL/COM1.

Serial Port for Out-of-Band Management / Windows Emergency Management
Services (EMS) Console Redirection

Select Enabled to use a COM port selected by the user for EMS Console Redirection. The
options are Enabled and Disabled.

*If the item above is set to Enabled, the following items will become available for

conguration:

EMS Console Redirection Settings

This feature allows the user to specify how the host computer will exchange data with the
client computer, which is the remote computer used by the user.

94

Chapter 4: BIOS

Out-of-Band Mgmt Port

The feature selects a serial port in a client server to be used by the Microsoft Windows
Emergency Management Services (EMS) to communicate with a remote host server. The
default option is SOL/COM1.

Terminal Type

Use this feature to select the target terminal emulation type for Console Redirection.
Select VT100 to use the ASCII character set. Select VT100+ to add color and function
key support. Select ANSI to use the extended ASCII character set. Select VT-UTF8 to use
UTF8 encoding to map Unicode characters into one or more bytes. The options are VT100,
VT100+, VT-UTF8, and ANSI.

Bits Per Second

This item sets the transmission speed for a serial port used in Console Redirection. Make
sure that the same speed is used in the host computer and the client computer. A lower
transmission speed may be required for long and busy lines. The options are 9600, 19200,
57600, and 115200 (bits per second).

Flow Control

Use this item to set the ow control for Console Redirection to prevent data loss caused
by bu󰀨er overow. Send a "Stop" signal to stop sending data when the receiving bu󰀨er
is full. Send a "Start" signal to start sending data when the receiving bu󰀨er is empty. The

options are None, Hardware RTS/CTS, and Software Xon/Xo󰀨.

Data Bits, Parity, Stop Bits

ACPI Settings

WHEA Support

Select Enabled to support the Windows Hardware Error Architecture (WHEA) platform and
provide a common infrastructure for the system to handle hardware errors within the Windows
OS environment to reduce system crashes and to enhance system recovery and health
monitoring. The options are Disabled and Enabled.

High Precision Event Timer

Select Enabled to activate the High Precision Event Timer (HPET) that produces periodic
interrupts at a much higher frequency than a Real-time Clock (RTC) does in synchronizing
multimedia streams, providing smooth playback and reducing the dependency on other
timestamp calculation devices, such as an x86 RDTSC Instruction embedded in the CPU.
The High Performance Event Timer is used to replace the 8254 Programmable Interval Timer.
The options are Disabled and Enabled.

95

Super X11SPG-TF User's Manual

Trusted Computing

The X11SPG-TF supports TPM 1.2 and 2.0. The following Trusted Platform Module (TPM)
information will display if a TPM 2.0 module is detected:

• Vendor Name

• Firmware Version

Security Device Support

If this feature and the TPM jumper on the motherboard are both set to Enabled, onboard

security devices will be enabled for TPM (Trusted Platform Module) support to enhance data
integrity and network security. Please reboot the system for a change on this setting to take
e󰀨ect. The options are Disable and Enable.

• Active PCR Bank

• SHA256 PCR Bank

*If the item above is set to Enable, "SHA256 PCR Bank" will become available for

conguration:

SHA256 PCR Bank

Use this item to disable or enable the SHA256 Platform Conguration Register (PCR) bank

for the installed TPM device. The options are Disabled and Enabled.

Pending Operation

Use this item to schedule a TPM-related operation to be performed by a security device for
system data integrity. Your system will reboot to carry out a pending TPM operation. The
options are None and TPM Clear.

Platform Hierarchy

Use this item to disable or enable platform hierarchy for platform protection. The options are
Disabled and Enabled.

Storage Hierarchy

Use this item to disable or enable storage hieararchy for cryptographic protection. The options
are Disabled and Enabled.

Endorsement Hierarchy

Use this item to disable or enable endorsement hierarchy for privacy control. The options are
Disabled and Enabled.

96

Chapter 4: BIOS

PH Randomization

Use this item to disable or enable Platform Hiearchy (PH) Randomization. The options are

Disabled and Enabled.

SMCI Bios-Based TPM Provision Support

Use this feature to enable the Supermicro TPM Provision support. The options are Disabled
and Enabled.

TXT Support

Intel Trusted Execution Technology (TXT) helps protect against software-based attacks and

ensures protection, condentiality, and integrity of data stored or created on the system. Use

this feature to enable or disable TXT Suppport. The options are Disabled and Enabled.

HTTP Boot Conguration

HTTP BOOT Conguration

Http Boot One Time

Use this feature to create the HTTP boot option. The options are Disabled and Enable.

Input the description

Highlight the feature and press enter to create a description.

Boot URI

Highlight the feature and press enter to create a boot URI.

TLS Authentication Conguration

This submenu allows the user to congure Transport Layer Security (TLS) settings.

Server CA Conguration

Enroll Certication

Enroll Certication Using File

Use this feature to enroll certication from a le.

Certication GUID

Use this feature to enroll to input the certication GUID.

Commit Changes and Exit

Use this feature to enroll to save all changes and exit TLS settings.

97

Super X11SPG-TF User's Manual

Discard Changes and Exit

Use this feature to enroll to discard all changes and exit TLS settings.

Delete Certication

Use this feature to delete certication.

iSCSI Conguration

iSCSI Initiator Name

This feature allows the user to enter the unique name of the iSCSI Initiator in IQN format.

Once the name of the iSCSI Initiator is entered into the system, congure the proper settings

for the following items.

Add an Attempt

Delete Attempts

Change Attempt Order

Driver Health

Intel® DCPMM 1.0.0 3429 Driver

This feature provides health status for the drivers and controllers.

98

4.4 Event Logs

Use this feature to congure Event Log settings.

Chapter 4: BIOS

Change SMBIOS Event Log Settings

Enabling/Disabling Options

SMBIOS Event Log

Change this item to enable or disable all features of the SMBIOS Event Logging during system
boot. The options are Enabled and Disabled.

Erasing Settings

Erase Event Log

If No is selected, data stored in the event log will not be erased. Select Yes, Next Reset,
data in the event log will be erased upon next system reboot. Select Yes, Every Reset, data
in the event log will be erased upon every system reboot. The options are No, Yes, Next
reset, and Yes, Every reset.

When Log is Full

Select Erase Immediately for all messages to be automatically erased from the event log
when the event log memory is full. The options are Do Nothing and Erase Immediately.

99

Super X11SPG-TF User's Manual

SMBIOS Event Log Standard Settings

Log System Boot Event

This option toggles the System Boot Event logging to enabled or disabled. The options are
Disabled and Enabled.

MECI

The Multiple Event Count Increment (MECI) counter counts the number of occurences that
a duplicate event must happen before the MECI counter is incremented. This is a numeric
value. The default value is 1.

METW

The Multiple Event Time Window (METW) denes the number of minutes that must pass

between duplicate log events before MECI is incremented. This is in minutes, from 0 to 99.
The default value is 60.

Note: After making changes on a setting, be sure to reboot the system for the changes

to take e󰀨ect.

View SMBIOS Event Log

Select this submenu and press enter to see the contents of the SMBIOS event log. The
following categories will be displayed: Date/Time/Error Code/Severity.

100