ST STVM100 User Manual
Features
2
■ I
C interface, slave address: 1001111
■ 7-bit adjustable sink current output
■ 2.25 V to 3.6 V logic supply voltage V
■
AVDD operating voltages
– 4.5 V to 20 V for V
– 4.5 V to 13 V for V
■ EEPROM for storing the optimum V
■ Guaranteed monotonic output over operating
from 2.6 V to 3.6 V
DD
from 2.25 V to 3.6 V
DD
DD
COM
setting
range
■ 400 kHz maximum interface bus speed
■ Operating temperature: –40 °C to 85 °C
■ Available in an 8-pin 3 mm x 3 mm TDFN8 or
3 mm x 3 mm TSSOP8 package
Applications
■ TFT-LCD panels
■ e-paper and e-book displays
Description
The STVM100 is a programmable VCOM
adjustment solution for thin-film transistor (TFT)
liquid-crystal displays (LCDs) to remove “flickers”.
It is also used in e-paper and e-book applications
to avoid the "ghosting" effect (residual pixels after
display refresh). It can replace a mechanical
potentiometer, so that the factory operator can
physically view the front screen when performing
the VCOM adjustment. This significantly reduces
labor costs, increases reliability, and enables
automation.
Table 1. Device summary
STVM100
I2C LCD/e-paper VCOM calibrator
TDFN8 (3 mm x 3 mm) (DC)
TSSOP8 (3 mm x 3 mm) (DS)
The STVM100 provides a digital I
control the sink current output (I
drives an external resistive voltage divider, which
can then be applied to an external V
Three external resistors R
1
mine the highest and lowest value of the V
An increase in the output sink current will lower
the voltage on the external divider so that the
V
can be adjusted by 128 steps within this
COM
range. Once the desired V
COM
achieved, it can be stored in the internal
EEPROM that will be automatically recalled during each power-up.
The STVM100 is available in an 8-pin,
3 mm x 3 mm TDFN8 or 3 mm x 3 mm TSSOP8
package.
2
C interface to
). This output
OUT
COM
, R2, and R
setting is
buffer.
SET
deter-
COM
.
Order code Optimum temperature range Package Packing
STVM100DC6E –40 °C to 85 °C TDFN8 ECOPACK
STVM100DS6F –40 °C to 85 °C TSSOP8 ECOPACK
December 2009 Doc ID 13236 Rev 8 1/27
®
package, tubes
®
package, tape and reel
www.st.com
1
Contents STVM100
Contents
1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2-wire bus characteristics and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 V
power supply ramp-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DD
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27 Doc ID 13236 Rev 8
STVM100 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Bit P read and write mode values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. TDFN8 3 x 3 x 0.75 mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . . . 23
Table 10. TSSOP8 – 8-lead, thin shrink small outline, 3 mm x 3 mm, mech. data . . . . . . . . . . . . . . . 24
Table 11. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 13236 Rev 8 3/27
List of figures STVM100
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Connections diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Read/write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. R
Figure 9. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. V
Figure 11. AV
Figure 12. VDD supply current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. AV
Figure 14. I
Figure 15. Total unadjusted error vs. DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Differential non-linearity vs. DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Integral non-linearity vs. DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. AV
Figure 19. Full scale-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Full scale-down response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. TDFN8 3 x 3 x 0.75 mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . . . 23
Figure 22. TSSOP8 – 8-lead, thin shrink small outline, 3 mm x 3 mm, mech. data. . . . . . . . . . . . . . . 24
, R2, and R
1
supply current vs. V
DD
supply current vs. AV
DD
supply current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DD
error vs. temperature (STVM100 at middle scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OUT
power-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DD
connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SET
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DD
DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4/27 Doc ID 13236 Rev 8
STVM100 Device overview
1 Device overview
Figure 1. Logic diagram
V
DD
SDA
SCL
STVM100
WP
GND
Table 2. Pin names and functions
Name Type Function
(1)
OUT Analog
AV
DD
Supply
Adjustable sink current output pin.
See Section 3: Application information on page 11.
High-voltage analog supply.
Bypass to GND with a 0.1 µF capacitor.
WRITE protectection.
WP Input
Active-low. To enable write operations to the DAC or to the EEPROM
writing, connect to 0.7 VDD or greater. Internally pulled down by a 130 kΩ
resistor.
GND Supply ground.
V
DD
Supply
SDA Input/Output I
SCL Input I
System power supply input.
Bypass to GND with a 0.1 µF capacitor.
2
C serial data input/output.
2
C serial clock input.
AV
OUT
SET
DD
AI12272
Maximum sink current adjustment point.
SET Analog
1. See SET pin function in this table for the maximum adjustable sink current setting.
Connect a resistor from SET to GND to set the maximum adjustable sink
current of the OUT pin. The maximum adjustable sink current is equal to
AVDD /20 divided by R
(see Figure 4 on page 6).
SET
Doc ID 13236 Rev 8 5/27
Device overview STVM100
Figure 2. Connections diagram
Figure 3. Block diagram
SDA
SCL
WP
Interface
V
I2C
DD
OUT
AV
GND
DD
WP
7
7
1
2
3
4
AV
DD
DAC
EEPROM
Block
GND
19R
R
SET
8
SCL
7
SDA
6
V
5
DD
AI12273
OUT
+
–
SET
AI12274
Figure 4. Hardware hookup
3.3V
MCU
2
C Interface
I
SDA
STVM100
SCL
WP
V
DD
V
DD
GND
0.1µF
AV
OUT
SET
DD
R
AV
SET
DD
0.1µF
R
1
+
R
2
–
VCOM
AI12275
6/27 Doc ID 13236 Rev 8
STVM100 Device operation
2 Device operation
The STVM100 operates as a slave device on the serial bus. Access is obtained by
implementing a start condition, followed by the 7-bit slave address (1001111), and the
eighth bit for READ/WRITE identification. The volatile DAC register and non-volatile
EEPROM values can be read out or written in.
2.1 2-wire bus characteristics and conditions
This bus is intended for communication between different ICs. It consists of two lines:
● a bi-directional data signal (SDA).
● a clock signal (SCL).
The SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor. The following protocols have been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line while the clock line is high will be interpreted as control
signals.
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the data line state from high-to-low while the clock is high indicate the start
condition.
2.1.3 Stop data transfer
A change in the data line state from low-to-high while the clock is high indicates the stop
condition.
Doc ID 13236 Rev 8 7/27
Device operation STVM100
2.1.4 Data valid
The data on the SDA line must be stable during the high period of the clock. The high or low
state of the data line can only change when the clock signal on the SCL line is low (see
Figure 5). The data on the line may be changed during the clock signal low period. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges transmission with
a ninth bit.
By definition, the device that gives out a message is called “transmitter”, the device that gets
the message is called “receiver”. The device that controls the message is called the
“master”. The devices controlled by the master are called “slave” devices.
Figure 5. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
8/27 Doc ID 13236 Rev 8
STVM100 Device operation
2.1.5 Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level signal put on the bus by the receiver, whereas the master generates an extra
acknowledge-related clock pulse (see Figure 6). A slave receiver which is addressed is
obliged to generate an acknowledge signal after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges transmissions has to pull down the SDA line during the
acknowledge clock pulse in such a way, that the SDA line is a stable low during the high
period of the acknowledge-related clock pulse. The setup and hold times must be taken into
account. A master receiver must signal an end of transmitted data to the slave transmitter
by not generating an acknowledge on the last byte that has been clocked out of the slave. In
this case, the transmitter must leave the data line high to enable the master to generate the
stop condition.
Figure 6. Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
SCL FROM
MASTER
START
12 89
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
MSB LSB
AI00601
Doc ID 13236 Rev 8 9/27
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