ST STV8105 User Manual
®
STV8105
256 x 72 x 4-Bit OLED Passive Matrix Controller/Driver
PRODUCT PREVIEW
Description
(Bumped Die)
ORDER CODE:
Main Features
■ Supports Monochrome OLED Passive
Matrices in different formats:
● 256×72 Black & White
● 256×72×2-bits/4 levels of gray
● 256×72×4-bits/16 levels of gray
● 256×36×6-bits/64 levels of gray
● 128×72×6-bits/64 levels of gray
■ On-chip DC/DC Step-up Converter
■ Display Power Supply up to 25V
■ Device Power Supply: 3.0 to 3.6V
■ Low-power Consumption Suitable for
Battery-operated Systems
■ Column Source Current capability: 800µA,
max.
■ Row Sink Current capability: 110mA, max.
STV8105
The STV8105 is a low-power, controller/driver
“combo” IC for OLED displays. The STV8105
supports 256 columns by 72 rows with 16 levels of
gray for monochrome and 2 x 128 columns by 72
rows with 16 lev els of gray f or “two” color displa ys. It
can control a display of 128 columns by 72 rows or
256 columns by 36 rows with 64 levels of gray in
monochrome mode.
The STV8105 provides all necessary functions in a
single chip, including on-chip supply control and
bias current generators, resulting in a minimum of
external components and in very low-power
consumption.
The STV8105 communicates with the system via
fully configurable interfaces (parallel or serial) to
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ease interfacing with the host microcontroller. The
STV8105 has a set of command and control
registers that can be addressed by these interfaces.
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SERIAL PARALLEL
INTERFACE INTERFACE
■ On-chip Oscillator
■ Programmable Gamma Correction
■ Programmable Display Multiplexing
■ Two Brightness Control registers of 128
steps each
■ 32 Step Dimmer Control
■ One Time Programmable (OTP) fuse ROM for
key configuration parameters
■ Dual Scan, Master/Slave Capability
■ Selectable 8-bit Parallel as well as Serial
Peripheral Interfaces
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This is target data for new product. Details are subject to change withou t notic e.
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REGISTERS
ROW
DRIVERS
STATUS
INSTRUCTION DECODER
DISPLAY RAM
256×72 4-bit
SCANNING CONTRO L
COLUMN DRIVERS
CONTROL
REGISTERS
CLOCK
GENERATOR
DC/DC
CONVERTOR
CURRENT
REFERENCES
STV8105
Contents
Chapter 1 General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Bumped Die Pad Description ...............................................................................................7
1.2 Pad Signal Description ............................................. ..... ...... ..... ................................. ..... .. ..12
1.3 Lead Pad Reference Chart ................................................................................................14
1.4 Mechanical Dimensions .....................................................................................................15
1.5 Functional Description ........................................................................................................16
Chapter 2 Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Interface Sequence ............................................................................................................17
2.2 Parallel Interface ................................................................................................................18
2.3 Serial Interface ...................................................................................................................20
2.4 Master/Slave Connection ...................................................................................................23
Chapter 3 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1 16 Level Gray Scale Mode Memory Map ...........................................................................26
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3.2 4 Level Gray Scale Mode Memory Map .............................................................................26
3.3 64 Level Gray Scale Mode 1 Memory Map ........................................................................28
3.4 64 Level Gray Scale Mode 2 Memory Map ........................................................................29
3.5 Monochrome Mode Memory Map ......................................................................................30
3.6 Display RAM Loading .........................................................................................................32
Chapter 4 Dot-Matrix Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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Chapter 5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Chapter 6 Master/Slave and Primary/Secondary Operation . . . . . . . . . . . . . . . . . . . . . . .37
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Chapter 7 B rightness Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Chapter 8 DC/DC Step-up Converter with VF Detection . . . . . . . . . . . . . . . . . . . . . . . . . .41
8.1 General Description ...........................................................................................................41
8.2 Detailed Description ...........................................................................................................42
8.2.1 PWM Mode .............. ..... .................................... ..... ..... .................................... ..... ..... .. ........................................43
8.2.2 PFM Mode ..........................................................................................................................................................44
8.3 Compensation Network ................................................. ...... ..... ..... ................................. ....45
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STV8105
8.4 Soft Start ............................................ ..... ...... ..... ................................. ..... ...... ..... ...............46
8.5 Peak Current Detection ......................................................................................................47
Chapter 9 Column Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
9.1 Color Selection Modes ....................... ..... ...... ................................ ...... ..... ...... ....................48
9.2 Dimmer Control ..................................................................................................................49
9.3 Drive Control ......................................................................................................................50
9.4 Setup Period ......................................................................................................................51
9.5 Drive Period .......................................................................................................................52
9.5.1 16 Level Gray Scale Mode ..................................................................................................................................54
9.5.2 4 Level Gray Scale Mode ....................................................................................................................................55
9.5.3 64 Level Gray Scale Mode ..................................................................................................................................56
9.5.4 Monochrome Mode .............................................................................................................................................58
Chapter 10 Row Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
10.1 Row Drivers ........................................................................................................................59
10.2 Row Driver Scanning Modes ..............................................................................................59
10.2.1 Single Scanning Mode ........................................................................................................................................59
10.2.2 Dual Scanning Mode ..........................................................................................................................................60
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Chapter 11 OTP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11.1 Introduction ........................................................................................................................62
11.2 OTP Memory Programming ...............................................................................................62
11.3 A Short Routine for Programming the OTP ........................................................................63
Chapter 12 STV8105 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
12.1 Reset Configuration ...........................................................................................................64
12.2 Sleep Configuration ............................................................................................................64
Chapter 13 Command and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
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13.1 List of Commands Ordered by Command Code ................................................................66
13.2 Command Details Ordered by Command Code ................................................................68
Chapter 14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
14.1 Absolute Maximum Ratings ...............................................................................................91
14.2 Thermal Data .....................................................................................................................91
14.3 Recommended Operating Conditio ns ........................... ...... ................................ ...... .........91
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STV8105
14.3.1 DC Characteristics ..............................................................................................................................................91
14.3.2 Timing Generator ................................................................................................................................................92
14.3.3 Row Drivers ........................................................................................................................................................92
14.3.4 Column Drivers ...................................................................................................................................................93
14.3.5 Current Reference and Brightness Adjustment D/A Converter
14.3.6 DC/DC Converter ................................................................................................................................................93
14.3.7 Voltage Generators .............................................................................................................................................94
14.3.8 Reset Input .........................................................................................................................................................94
Chapter 15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
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STV8105 General Overview
1 General Overview
The STV8105 is a monochrom e , l ow-power co nt ro ll e r/ dri ver combo from STM i cr o ele ct ro ni c s’ family
of controllers for OLED displays. It has been developed to bring a flexible solution to applications
and systems based on OLED passi ve matr ic es.
STV8105 can be used with many different host micro-controllers. It supports a serial bus and a
The
parallel interface covering most of the possible application architectures. This provides easy access
to a set of command and control registers to properly program the
STV8105 includes a dual port Display RAM of 256 x 72 x 4-bits to support the full display
The
capabilities of 256 column and 72 row drivers with several display functions.
The on-chip DC/DC step-up converter generates the necessary supply voltage (18V, typically) for
all row and column drivers from the battery supply.
STV8105.
Processed in BCD technology, the
can source up to 800µA for columns and sink up to 110mA for rows with a display supply of up to
25V. Thanks to the high level of integration, the number of required external components is
drastically reduced.
STV8105 f eatures a low-power digital core and output drivers that
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General Overview STV8105
Figure 1: STV8105 Input/Output Diagram
RST
CLKIN
ROSC
COSC
SELCLK
MSEL[1]
MSEL[0]
P/S
DIN[7] (SIN)
DIN[6] (SCLI)
DIN[5:0]
CS1, CS2
SD/C
WR
HSYNCIN
VSYNCIN
VDD
STV8105
A
VPRG
VPP1, VPP2
VROW1, VROW2
VCOL1, VCOL2
COLUMNS
C1…C256
ROWS
R1…R72
DOUT[7] (SOUT)
DOUT[6] (SCLOUT)
DOUT[5:0]
CSOUT1, CSOUT2
SD/COUT
FT
WROUT
HSYNCOUT
VSYNCOUT
RCTRLA
RCTRLB
ROWDATA
SCLKOUT
R
D
TEST[3]
TEST[2:1]
GND
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GNDL
GNDSENSE
VDC
VHSENSE
VDRIVE
ISENSE
VSENSE
VCOMP
VF
TON/F
CMODE
VREF1, VREF2
STV8105 General Overview
1.1 Bumped Die Pad Description
Figure 2: Die Mechanical Data (Bump-side View)
TOP SIDE
C1
-TBDµm
C256
C255
TBDµm
C2
+TBDµm
R72
LEFT SIDE
R38 R37
R36
-TBDµm
-TBDµm
-TBDµm
-TBDµm
R34
+TBDµm
STV8105
(X=0.0, Y=0.0)
-TBDµm
R2
R4
Figure 3: Alignment Mark Positions (Bump-side View)
Interface
BOTTOM SIDE
-TBDµm
R3
R1
FT
+TBDµm
-TBDµm
+TBDµm
-TBD
R33
+TBDµm
A
-TBDµm
TOP SIDE
+TBDµm
R71
RIGHT SIDE
R35
-TBDµm
+TBDµm
LEFT SIDE
-TBDµm
R
Columns
(X=0.0, Y=0.0)
Rows
Rows
-TBDµm
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Interface
BOTTOM SIDE
Rows
+TBDµm
+TBDµm
Rows
RIGHT SIDE
-TBDµm
General Overview STV8105
Figure 4: Alignment Mark Mechanical Data
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
METAL X
TBDµm
COF Alignment Mark
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
TBDµm
METAL X
TBDµm
TBDµm
TBDµm
TBDµm
Die Positioning Mark
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STV8105 General Overview
Figure 5: Pad Position (Bump-Side View)
Left
ROW OUTPUTS
INPUTS
- - - -
R34
R32
R30
R4
R2
VROW2
VROW2
DUMMY
DUMMY
ROWDATA
RCTRLB
RCTRLA
SCLKOUT
VSYNCOUT
HSYNCOUT
CSOUT2
CSOUT1
OUT
WR
SD/COUT
DOUT[0]
DOUT[1]
DOUT[2]
DOUT[3]
DOUT[4]
DOUT[5]
DOUT[6]
DOUT[7]
VSENSE
VCOMP
ISENSE
VDC
VDC
VDRIVE
R36
= = =
BOTTOM SIDE
D
R38
= = =
LEFT HALF SIDE
R72
R70
C256
C255
C254
C253
COLUMN OUTPUT SIDE
TOP SIDE
STV8105
FT
A
R
C167
C168
C167
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General Overview STV8105
INPUTS
VDRIVE
VDRIVE
GNDSENSE
GNDSENSE
GNDL
GNDL
GNDL
GNDL
GND
GND
GND
GND
VPRG
VPRG
VPRG
VPRG
VPP2
VPP2
VHSENSE
VHSENSE
VPP1
VPP1
VCOL2
VCOL2
VCOL1
VCOL1
VF
BOTTOM SIDE
STV8105
0,0
+Y
FT
+X
A
C167
C166
C165
COLUMN OUTPUT SIDE
TOP SIDE
VREF2
VREF1
R
VDD
VDD
VDD
VDD
DUMMY
GND
P/S
TON/F
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D
C92
C91
C90
STV8105 General Overview
INPUTS
(95 I/O Pads)
ROW OUTPUTS
- - - -
TON/F
CMODE
SELCLK
MSEL[1]
MSEL[0]
VDD
TEST[3]
TEST[2]
TEST[1]
RST
DIN[7] (SIN)
DIN[6] (SCLI)
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
SD/C
WR
CS1
CS2
GND
VSYNCIN
HSYNCIN
CLKIN
ROSC
COSC
DUMMY
DUMMY
VROW1
VROW1
R1
R3
R31
R33R33
C90
C89
C88
STV8105
BOTTOM SIDE
COLUMN OUTPUT SIDE
FT
TOP SIDE
A
R
D
C3
= = =
R35
R37
R71
R69
C2
C1
= = =
RIGHT HALF SIDE
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Right
General Overview STV8105
1.2 Pad Signal Description
Table 1: STV8105 Pad Description (Sheet 1 of 2)
Ball Name Input/Output Description
C1-C256 O Column Driver Outputs
R1-R72 O Row Driver Outputs
CLKIN I External RC/Crystal connection or Clock input
Mode Select:
CMODE I
COSC O External RC oscillator, capacitor connection
“H”: Dual color mode
“L”: Single color mode
CS1
CS2
CSOUT1
CSOUT2
DIN[5:0] I
DIN[6] (SCLI) I
DIN[7] (SIN) I
DOUT[5:0] O
DOUT[6] (SCLOUT) O
DOUT[7] (SOUT) O
GND Supply Analog and Digital ground
GNDL Supply Column and Row driver ground
GNDSENSE Supply Ground for DC/DC Converter
I Chip Select 1 Input (Master Device Chip Select)
I Chip Select 2 Input (Slave Device Chip Select)
O Chip Select 1 Output
O Chip Select 2 Output
=”H”: Parallel Data Input
P/S
=”L”: Not used. Fix to “H” or “L”
P/S
=”H”: Parallel Data Input
P/S
P/S
=”L”: Serial Cl ock Input
=”H”: Parallel Data Input
P/S
P/S
=”L”: Serial Data Input
=”H”: Parallel Data Output
P/S
P/S
=”L”: Non Connection
=”H”: Parallel Data Output
P/S
=”L”: Serial Cl ock Output
P/S
=”H”: Parallel Data Output
P/S
P/S
=”L”: Serial Data Output
A
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FT
HSYNCIN I Horizont al SY NC Input
HSYNCOUT O Horizontal SYNC Output
ISENSE I Over current sense signal for external switching MOS transistor
MSEL[0] I
MSEL[1] I
P/S
RCTRLA O Reserved for Test
RCTRLB O
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I Parallel Interface or Serial Interface Select
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Master /Slave Select:
“H”: Master
“L”: Slave
Primary /Secondary Select:
“H”: Primary
“L”: Secondary
Pad RCTRLB is pulled “High” if a voltage fault is detected on the output of the
DC/DC converter.
STV8105 General Overview
Table 1: STV8105 Pad Description (Sheet 2 of 2)
Ball Name Input/Output Description
ROSC O External RC oscillator, resistor connection or Crystal connection
ROW DATA O Row Driver Data
RST
SCLKOUT O System Clock Output
SD/C
OUT O SD/C Output
SD/C
SELCLK I
TEST[2:1] I
TEST[3] I Reserved (internal pull-up)
TON/F
VCOL1 Supply Odd column supply
VCOL2 Supply Even column supply
VCOMP I/O Compensation pad for DC/DC converter, constant frequency PWM mode
VDC Supply Supply for gate drive output buffer
I System Reset Input
Display Data or Command:
I
I
SD/C=”H”: Display Data
SD/C
=”L”: Command
“H”: An internal oscillator (if MSEL[0]=”1”)
“L”: External clock used
Test Mode Select:
“H”: Test Mode OFF (internal pull-up)
“L”: Reserved modes
DC/DC Converter Mode Select
“H”: PFM constant t
“L”: PWM constant switching frequency mode
ON
mode
FT
VDD Supply Analog/Digital low-voltage controller supply
VDRIVE O Gate drive for external switchin g MOS transistor
VF I/O
VHSENSE I VH sense input
VPP1 Supply Odd column driver power supply
VPP2 Supply Even column dr iver power supply
VPRG Supply Non-volatile OTP memory program power supply
VREF1 I/O Referen ce Voltag e 1
VREF2 I/O Referen ce Voltag e 2
VROW1 Supply Odd row driver supply
VROW2 Supply Even row driver supply
VSENSE I Feedback signal
VSYNCIN I Vertical SYNC Input
VSYNCOUT O Vertical SYNC Output
WR
OUT O Write Pulse Output
WR
I Display Data and Command Write Pulse
Pad for storing the re sult of VF dete ction, i.e. the average of the voltage on column
outputs C1 and C256 measured during constant current drive
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General Overview STV8105
1.3 Lead Pad Reference Chart
The reference for the following tables is the center of the die (X = 0.0, Y = 0.0)
Table 2: Top Side (from left to right)
Pad Placements (center), µm Pad Dimensions, µm
Lead Pad Name
XYXY
C256 TBD TBD TBD TBD
----- ------- ------- ------- ------C2 TBD TBD
C1 TBD TBD
Table 3: Right Side (from top to bottom)
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
R71 TBD TBD
------- ------- ------- ------- ------R37 TBD TBD
R35 TBD TBD
Table 4: Bottom Side (from right to left)
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
A
FT
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
R33 TBD TBD
------- ------- ------- ------- -------
R1 ------- ------- ------- -------
VROW1 ------- ------- ------- -------
R
TBD TBD
D
------- ------- ------- ------- -------
------- ------- ------- ------- -------
VROW2 ------- ------- ------- -------
R2 ------- ------- ------- -------
------- ------- ------- ------- ------R34 ------- ------- ------- -------
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STV8105 General Overview
Table 5: Left Side (from bottom to top)
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
R36 TBD TBD
R38 TBD TBD
------- ------- ------- ------- ------R72 TBD TBD
1.4 Mechanical Dimensions
Table 6: Mechanical Dimensions
Description Dimension
Die Size (mm) TBD
Pad Pitch (µm) TBD
Pad Size (µm) TBD
Pad Heigh t (µm ) TBD
Wafer Thickness (µm) TBDµm
Bump Size (µm) TBDµm x TBDµm
Bump Characteristics gold, electrolytic
TBD TBD
TBD TBD
TBD TBD
FT
Bump Hardness 30-80Hv
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General Overview STV8105
1.5 Functional Description
The architecture of the STV8105 provides all of the functions required to drive OLED displays. The
block diagram below gives an overview of the different on-chip components, embedded functions
and their links.
Figure 6: STV8105 Block Diagram
SERIAL PARALLEL
INTERFACE INTERFACE
STATUS
REGISTERS
ROW
DRIVERS
INSTRUCTION DECODER
DISPLAY RAM
256×72 4-bit
CONTROL
REGISTERS
CLOCK
GENERATOR
FT
DC/DC
CONVERTER
SCANNING CONTROL
COLUMN DRIVERS
A
CURRENT
REFERENCES
R
The following rules are used in this datasheet to describe bit, bit-fields and registers:
- ROWDRVSEL is the name of a register,
- RDIR.ROWDRVSEL is the RDIR bit of register ROWDRVSEL,
- RMODE.ROWDRVSEL is the RMODE bit-field of register ROWDRVSEL.
Refer to Chapter 13: Command and Control Registers on page 65 for details of the various
registers.
The various functions of the STV8105 are described in the following sections, starting with the bus
interfaces.
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STV8105 Bus Interfaces
2 Bus Interfaces
The parallel interface and serial interface are selected using a P/S pad.
The parallel interface is active when P/S
The serial input pads SIN and SCLI are shared with DIN7 and DIN6, respectively.
Buffered versions of the serial signals, for cascading purposes, are output on pads SOUT and
SCLOUT and shared with DOUT7 and DOUT6, respectively.
The parallel interface pads DIN[7:0], CS1
CSOUT1
CS1
CS2
, CSOUT2, and WROUT.
and CSOUT1 are chip select signals for the Primary-Master and Secondary-Master devices.
and CSOUT2 are chip select signals for the Primary-Slave and Secondary-Slave devices.
Figure 7: Buffering of Bus Interface Signals
Internal Circuits
DIN[7] (SIN) DOUT[7] (SOUT)
DIN[6] (SCLI) DOUT[6] (SCLOUT)
DIN[5:0] DOUT[5:0]
=”H”; the serial interface when P/S =”L”.
, CS2 and WR are buff ered and sent out on DOUT[7:0],
FT
CS1
CS2
WR
SD/C
D
2.1 Interface Sequen ce
After Reset or Power ON, an interface is in the state of waiting for a Command Address and Display
RAM Data.
After receiving the Command Address, the interface is in the state of waiting for Command Data.
When Command Data is received while in the receive Command Data state, the interface returns to
the receive Command Address state.
When Display RAM Data is received while in the receive Command Data state, the interface also
returns to the receive Command Address state.
A
R
CSOUT1
CSOUT2
WROUT
SD/COUT
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Bus Interfaces STV8105
When the Serial Interface is selected, the output buffer for the interface signals is cleared when CS1
and CS2
2.2 Parallel Interface
The parallel interface is active when pad P/S is "High".
are both "High".
When writing parallel data, the WR
Data is interpreted as a command if SD/C
"High".
When transmitting a command, the command address is sent first followed by command data.
A command is decided by a 2-byte access: a command code followed by a data byte.
When there is a Display RAM access with SD/C
of a command, the STV8105 enters the state where it is waiting for a Command Address.
CS1, CS2
WR
pad is asserted while CS1 and CS2 are both "Low".
is "Low"; it is interpreted as Display RAM data if SD/C is
set “High” but without respecting the “2-byte nature”
Figure 8: Parallel Interface
FT
SD/C
DIN[7:0]
A
P/S = High Command Data
Command Address
(1 byte)
(1 byte)
Display RAM Data
(1 byte)
Command
(2 bytes)
R
Don’t care
D
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STV8105 Bus Interfaces
Figure 9: 8-bit Parallel Interface Timing Diagram
SD/C
CS1
CS2
WR
WR
DIN[7:0]
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Taw
Valid
Tcclw
Tcyc
Tds
Tah
Tcchw
Tdh
FT
Valid
SD/COUT
CSOUT1
CSOUT2
WROUT
DOUT[7:0]
VIH
VIL
Tdsdc
VIH
VIL
VIH
VIH
VIL
VIL
VIH
VIL
A
Valid
R
Tdcs
Tdwr
D
Tdd
Valid
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Bus Interfaces STV8105
Table 7: 8-bit Parallel Interface Timing
Symbol Parameter Test Conditions Min. Typ. Max. Units
Tah Address Hold Time WR 10 ns
Taw Address Setup Time WR
Tcyc System Cycle Time CS1
Tcclw Write Pulse Width WR
Tds Data Setup Time DIN[7:0] 60 ns
Tdh Data Hold Time DIN7:0] 10 ns
Tdsdc SD/C Output Delay SD/C
Tdcs CS Output Delay CSOUT1
Tdwr WR Output Delay WR
Tdd DATA Output DOUT[7:0] 30 ns
2.3 Serial Interface
The serial interface is active when P/S is "Low".
, CS2 200 ns
OUT 30 ns
, CSOUT2 30 ns
OUT 30 ns
0ns
60 ns
FT
Serial data is written in using DIN[7] (SIN) and DIN[6] (SCLI) while CS1
Data is interpreted as a command if SD/C
"High".
is "Low"; it is interpreted as Display RAM data if SD/C is
and CS2 are both "Low".
DIN[5:0] are not used; they should be tied either “High” or “Low”.
A
R
D
20/96 05-Sep-2005 Draft of Rev. 1 STMicroelectronics Confidential
STV8105 Bus Interfaces
Figure 10: Serial Interface
CS1, CS2
SD/C
D7 D0 D7 D0 D7 D0
DIN[7](SIN)
DIN[6](SCLI)
DIN[5:0]
Fixed High or Low
P/S = Low
Command Address
(1 byte)
R
D
Command
(2 bytes)
A
Command Data
(1 byte)
FT
Display RAM Data
(1 byte)
Don’t care
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Bus Interfaces STV8105
Figure 11: 4-wire Serial Interface Timing Diagram
Tcss Tcsh
CS1
CS2
SD/C
SCLI
SIN
VIH
VIL
VIH
VIL
VIH
VIL
Tslw
Tsas
TrTf
Tsds
Tsah
Valid
Tscyc
Tshw
Tsdh
Valid
FT
A
Table 8: 4-wire Serial Interface Timing
Symbol Parameter Test Conditions Min. Typ. Max. Units
Tscys Serial Clock Cycle 200 ns
Tshw Pulse Width (High) 90 ns
Tslw Pulse Width (Low) 90 ns
Tsas Address Setup Time 20 ns
Tsah Address Hold Time 20 ns
Tsds Data Setup Time 20 ns
Tsdh Data Hold Time 20 ns
Tcss CS-SCL Time 20 ns
Tcsh CS-SCL Time 20 ns
D
R
22/96 05-Sep-2005 Draft of Rev. 1 STMicroelectronics Confidential
STV8105 Bus Interfaces
2.4 Master/Slave Connection
Figure 12 below shows an example connection between two ICs for Master/Slave mode.
Figure 12: Master/Slave Mode
OLED Panel
From MPU
SCLKOUT
DIN[7:0]
CS1
CS2
WR
SD/C
STV8105 Master STV8105 Slave
DOUT[7:0]
CSOUT2
WROUT
SD/COUT
SCLKOUT
VSYNCOUT, HSYNCOUT
Figure 13: External IC Interface Timing Diagram
FT
VIH
VIL
A
VSYNCIN,
HSYNCIN
VSYNCOUT
HSYNCOUT
RCTRLA
RCTRLB
KDATA
VIH
VIL
R
Tdvso
Tdhso
Tdrca
Tdrcb
Tdrowdata
D
05-Sep-2005 Draft of Rev. 1 STMicroelectronics Confidential 23/96
Bus Interfaces STV8105
Table 9: External IC Interface Timing
Symbol Parameter Test Conditions Min. Typ. Max. Units
Tdvso VSYNCOUT Delay 20 ns
Tdhso HSYNCOUT Delay 20 ns
Tdrca RCTRLA Delay 20 ns
Tdrcb RCTRLB Delay 20 ns
Tdrowdata ROWDATA Delay 20 ns
R
D
FT
A
24/96 05-Sep-2005 Draft of Rev. 1 STMicroelectronics Confidential
STV8105 Display RAM
3 Display RAM
The STV8105 contains a Dual Port, 256 × 72 x 4-bit Display RAM. As shown in Figure 14 below,
Port A is for write only; Port B, read only.
It is possible to access any location thanks to X and Y, programmable pointers with ranges
corresponding to the selected display mode.
The X address is specified with the command RAMXSTART, the Y address with RAMYSTART.
The X and Y addresses can be automatically incremented with bits YINC and XINC of the
GSADDINC command. The GSMODE bit-field of this command is also used to select the display
mode and gray scale. See Section 13.2 for details.
Depending on the selected display mode, one, two or four pictures can be stored in the Display
RAM, and one or two colors can be controlled:
16 level gray scale mode: 256 × 72 × 4 bits - 1 picture - one/two colors
4 level gray scale mode: 256 × 72 × 2 bits - 2 pictures - one/two colors
64 level gray scale mode 1: 128 × 72 × 6 bits - 1 picture - one color
64 level gray scale mode 2: 256 × 36 × 6 bits - 1 picture - one color
Black and White, monochrome mode: 256 × 72 × 1 bit - 4 pictures - one/two colors
Figure 14: Dual Port Display RAM Composition
FT
Display RAM
MPU Write Only Driver Write Only
Port A
Dual-Port RAM
A
256× 72×4-bits
Port B
R
D
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Display RAM STV8105
3.1 16 Level Gray Scale Mode Memory Map
In this mode, the picture has 256 x 72 pixels, and the gray scale of each pixel is defined by the
corresponding 4-bit value stored in Display RAM. This mode is selected using field GSMODE of the
GSADDINC command. Only one picture can be stored in the Display RAM. The range of the
address pointers is 00h to 7Fh for X and 00h to 47h for Y. One byte loaded in Display RAM contains
data for two pixels.See Section 13.2 for details. The “two” color mode can be used; see Section
9.1: Color Selection Modes for details.
Figure 15: 16 Level Gray Scale Mode - Display RAM Organization
X =>
Y =>
Row 1
Row 2
Row 3
Row 71
Row 72
Y 00h, X 00h Y 00h, X 01h Y 00h, X 7Dh Y 00h, X 7Eh Y 00h, X 7Fh
Pxl 0, Pxl 1
Y 01h, X 00h
Col1 Col2 Col254 Col255 Col256
Pxl 0
Pxl 2, Pxl 3
Pxl 1 Pxl 255
Display Screen
Pxl 250, Pxl 251
Pxl 254Pxl 253
Pxl 252, Pxl 253
FT
Display RAM
Y 46h, X 00h
Y 47h, X 00h
A
Pxl 254, Pxl 255
Y 47h, X 7Fh
Col 1* Col 2* Col 3*
Row 1
3.2 4 Level Gray Scale Mode Memory Map
In this mode, the picture has 256 x 72 pixels. The gray scale of each pixel is defined by the
corresponding 2-bit value stored in Display RAM. This mode is selected using field GSMODE of the
GSADDINC command. Two pictures can be stored in the Display RAM. The range of the address
pointers is 00h to 3Fh for X and 00h to 8Fh for Y. One byte loaded in Display RAM contains data for
4 pixels. See Figure 16 for details. The “two” color mode can be used, see Section 9.1: Colo r
Selection Modes for details.
26/96 05-Sep-2005 Draft of Rev. 1 STMicroelectronics Confidential
Pixel 0 Pixel 1 Pixel 2
b3---b0, Byte 00h
Column to Pixel Mapping
b7---b4, Byte 00h
D
R
b3---b0, Byte 01h
Col 255*
Pixel 254
b3---b0, Byte 7Fh
* Default column mapping
Col 256*
Pixel 255
b7---b4, Byte 7Fh
STV8105 Display RAM
Figure 16: 4 Level Gray Scale Mode - Display RAM Organization
Display RAM
X =>
Y =>
Row 1
Row 2
Row 3
Row 71
Row 72
Y 00h, X 00h Y 00h, X 01h Y 00h, X 3Eh Y 00h, X 3Fh
Pxl 0, Pxl 3
Y 01h, X 00h
Y 46h, X 00h
Y 47h, X 00h
Y 48h, X 00h Y 48h, X 01h Y 48h, X 3Eh Y 48h, X 3Fh
Pxl 0, Pxl 3
Y 49h, X 00h
Col1 Col2 Col254 Col255 Col256
Pxl 0
Pxl 4, Pxl 7
Pxl 1 Pxl 255
Display Screen
Picture 1
Pxl 254Pxl 253
Pxl 248, Pxl 251
FT
Pxl 4, Pxl 7
Pxl 248, Pxl 251
A
Pxl 252, Pxl 255
Pxl 252, Pxl 255
Y 47h, X 3Fh
Row 1
Picture 2
R
Y 8Eh, X 00h
Y 8Fh, X 00h
Y 8Fh, X 3Fh
D
Col 1* Col 2* Col 3*
Pixel 0 Pixel 1 Pixel 2
b1---b0, Byte 00h
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b3---b2, Byte 00h
Column to Pixel Mapping
b5---b4, Byte 00h
Col 4*
Pixel 3
b7---b6, Byte 00h
Col 255*
Pixel 254
b5---b4, Byte 7Fh
* Default column mapping
Col 256*
Pixel 255
b7---b6, Byte 7Fh
Display RAM STV8105
3.3 64 Level Gray Scale Mode 1 Memory Map
In this mode, the picture has 128 x 72 pixels. The gray scale of each pixel is defined by the
corresponding 6-bit value stored in Display RAM. This mode is selected using field GSMODE of the
GSADDINC command. Only one picture can be stored in the Display RAM. The range of the
address pointers is 00h to 7Fh for X and 00h to 47h for Y. One byte loaded in the Display RAM
contains data for one pixel.
In this mode, column outputs C
“two” color mode, see Section 9.1: Color Selection Modes for details. For more information on using
this mode, refer to the description of command GSADDINC in Section 13.2.
Figure 17: 64 Level Gray Scale Mode 1 - Display RAM Organization
X =>
Y =>
Row 1
Row 2
Row 3
Row 71
Row 72
and Cn, must be connected together. It is not possible to use the
n+1
Col1 Col2 Col126 Col127 Col128
Pxl 0
Pxl 1 Pxl 127
Display Screen
Pxl 126Pxl 125
FT
Y 00h, X 00h Y 00h, X 01h Y 00h, X 7Dh Y 00h, X 7Eh Y 00h, X 7Fh
Pxl 0
Y 00h, X 00h
Pxl 1
Pxl 125
Pxl 126
Pxl 127
A
Display RAM
Y 46h, X 00h
Y 47h, X 00h
Col 1* Col 2* Col 3*
Row 1
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Pixel 0 Pixel 1 Pixel 2
b5---b0, Byte 00h
Column to Pixel Mapping
D
b5---b0, Byte 01h
128 columns, 72 rows
R
b5---b0, Byte 02h
Y 47h, X 7Fh
Col 127*
Pixel 126
b5---b0, Byte 7Eh
* Default column mapping
Col 128*
Pixel 127
b5---b0, Byte 7Fh
STV8105 Display RAM
3.4 64 Level Gray Scale Mode 2 Memory Map
In this mode, the picture has 256 x 36pixels, the gray scale of each pixel is defined by the
corresponding 6-bit value stored in Display RAM. This mode is selected using field GSMODE of the
GSADDINC command. Only one picture can be stored in the Display RAM. The range of the
address pointers is 00h to FFh for X, 00h to 23h for Y. One byte loaded in the Display RAM contains
data for one pixel.
The “two” color mode cannot be used, see Section 9.1: Color Selection Modes for detail. For more
information on using this mode, refer to the description of command GSADDINC in Section 13.2.
Figure 18: 64 Level Gray Scale Mode 2 - Display RAM Organization
X =>
Y =>
Row 1
Row 2
Row 3
Row 35
Row 36
Col1 Col2 Col254 Col255 Col256
Pxl 0
Pxl 1 Pxl 255
Display Screen
Pxl 254Pxl 253
FT
Y 00h, X 00h Y 00h, X 01h Y 00h, X FDh Y 00h, X FEh Y 00h, X FFh
Pxl 0
Y 00h, X 00h
Pxl 1
Pxl 253
Pxl 254
A
Display RAM
Y 22h, X 00h
R
Y 23h, X 00h
Pxl 255
Y 47h, X FFh
Col 1* Col 2* Col 3*
Row 1
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Pixel 0 Pixel 1 Pixel 2
b5---b0, Byte 00h
Column to Pixel Mapping
256 columns, 36 rows
D
b5---b0, Byte 01h
b5---b0, Byte 02h
Col 255*
Pixel 254
b5---b0, Byte FEh
* Default column mapping
Col 256*
Pixel 255
b5---b0, Byte FFh
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