ST STV8102 User Manual
®
128 x 64 OLED Passive Matrix Controller-Driver
Main Features
■ Support 128 x 64 Dot Matrix Panels
■ Embedded DC-DC Step-up Converter
STV8102
PRODUCT PREVIEW
I2C Parallel SPI
Interface Interface Interface
■ Display Power Supply up to 20V
■ Device Power Supply: 1.8V to 3.3V
■ Low-power Consumption Suitable for
Battery-operated systems
■ Column Source Current: 500µA (max.)
■ Row Sink Current: 64mA
■ On-chip Oscillator
■ Programmable Multiplexing Rate
■ Self Adaptive Panel Addressing Scheme
■ Powermizer
■ Brightness Control with Built-in Aging
Compensation
■ Built-in Display Pattern Generator
■ Selectable 8-bit Parallel Interface (68xx, 80xx
series), Serial Peripheral Interface and I²C
interface
■ Embedded 128 x 64 x 1-bit Graphic RAM
■ Row and Column Re-mapping
■ Screen Saver Mode
■ -40° to +85°C Operating Temperature
Driving Scheme
R
Status
Register
Row
Drivers
Screen
Saver
Pattern
Generator
Instruction
Decoder
Display RAM
64 X 128 bits
Self-adaptive
Scanning Control
Column Drivers
Control
Register
Clocks
Generator
Powermizer
Panel
Supply
Reference
Current
FT
Description
The STV8102 is a low-power controller chip for
Organic Light Emitting Diode (OLED) dot passive
matrix display systems. The STV8102 supports
A
black-and-white monochrome displays with a
definition of up to 128 columns and 64 rows.
The STV8102 provides all necessary functions in a
single chip, including on-chip OLED supply control
and bias current generators, resulting in a minimum
of external components and in very low-power
consumption.
The STV8102 communicates with the system via
fully configurable interfaces (parallel, serial or I
D
10 November 2004 Draft of Revision 1.7 ADCS 7476489 STMicroelectronics Confidential 1/65
This is preliminary information on a new product now in development . Details are subje ct to change without notice.
to ease interfacing with the host microcontroller.
The STV8102 has a set of control and status
registers that can be addressed by the interfaces.
2
C)
STV8102
Chapter 1 General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Bump Die Pad Description ...................................................................................................5
1.2 Pad Signal Descript ion . ..... ....................................... ............................................................6
1.3 Lead Pad Reference Chart ..................................................................................................7
1.4 Mechanical Dimensions .....................................................................................................15
1.5 Functional Description ........................................................................................................15
Chapter 2 Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.1 I²C Interface .......................................................................................................................16
2.2 Serial Interface ...................................................................................................................18
2.3 Parallel Interface ................................................................................................................21
Chapter 3 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1 RAM Writing .......................................................................................................................25
Chapter 4 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1 Normal Horizontal/Vertical Display .....................................................................................26
4.2 Mirrored Modes ................. ...... ..... ...... ...................................... ..........................................26
4.2.1 Mirrored Vertical ....................................... ..... .... ............................ ..... .... .............................................................26
4.2.2 Mirrored Horizontal ....................................... .... ..... ............................ .... ..... ........................................................27
4.2.3 Full Mirror ............................................................................................................................................................27
4.3 Display Panning .................................................................................................................28
4.4 Screen Saver .....................................................................................................................29
4.4.1 Limit-to-Limit .......................................................................................................................................................29
4.4.2 Bounce Only .......................................................................................................................................................30
4.4.3 Wrap Only ...........................................................................................................................................................31
4.4.4 Wrap and Bounce ...............................................................................................................................................32
4.5 Flash Mode ............ ...... ...................................... ...................................... ..........................33
4.6 Pattern Generator ..............................................................................................................34
R
A
FT
D
Chapter 5 Display Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.1 Row Driver .........................................................................................................................35
5.2 Column Driver .......................................................................... ..... .....................................36
5.2.1 Column Pre-charge/Discharge ...........................................................................................................................36
5.2.2 Active Period .......................................................... ..... ........................................................................................37
5.3 Optimization of the Column Driving Scheme .....................................................................37
5.4 Examples of the Row/Column Driving Waveforms ............................................................38
Chapter 6 Scanning Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
STMicroelectronics Confidential Draft of Revision 1.7 2/65
STV8102
Chapter 7 Power Supply Management - PowermizerTM . . . . . . . . . . . . . . . . . . . . . . . . . .42
Chapter 8 Oscillator – Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Chapter 9 STV8102 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
9.1 Reset Configuration ...........................................................................................................45
9.2 Display OFF Configuration .................................................................................................45
9.3 Example Configuration .......................................................................................................45
Chapter 10 Control and Status Registers Descri ption . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
10.1 Register Map ......................................................................................................................48
10.2 Register Description Ordered by Name .............................................................................49
Chapter 11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
11.1 Absolute Maximum Ratings ...............................................................................................61
11.2 Thermal Data .....................................................................................................................61
11.3 Recommend ed Op erat ing Conditio ns ...................... ..... ...... ..... ..........................................61
11.3.1 DC Characteristics ..............................................................................................................................................61
11.3.2 Timing Generator ................................................................................................................................................62
11.3.3 Row Drivers ........................................................................................................................................................62
11.3.4 Column Drivers ...................................................................................................................................................62
11.3.5 DC-to-DC Converter ...........................................................................................................................................63
11.3.6 Voltage Generator ...............................................................................................................................................63
Chapter 12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
A
FT
R
D
3/65 Draft of Revision 1.7 STMicroelectronics Confidential
STV8102 General Overview
1 General Overview
The STV8102 is a monochrome, black and white, low-power controller from STMicroelectronics’
family of controllers for OLED displays. It has been developed to bring a flexible solution to
applications and systems based on OLED passive matrixes.
The STV8102 is processed in 0.35µm BCD technology. The supply of the digital core of the
controller is typically 3.3V. The controller can operate with a display supply of up to 20V.
The device can be used with many different host microcontrollers. It supports two kinds of serial bus
and two parallel interfaces, covering most of the possible application architectures. This provides
easy access to the set of status and control registers to properly program the STV8102.
The STV8102 includes a display RAM of 128×64 bits to support the full display capabilities of the
128 column drivers and 64 row drivers with several display functions like mirroring, panning and
screen saver. These are described in more detail in Chapter 4: Display Modes.
Processed in BCD technology, the digital core consumes very little power even when the display
driver outputs are sourcing 500µA max for executing column commands or sinking 64mA max for
row commands. Thanks to a Powermizer
total power consumption of the STV8102 fits within the specification of several Nomadic
applications. With the STV8102, the number of external components is drastically reduced. See
Chapter 5: Display Addressing Scheme and Cha pter 7: Power Supply Management PowermizerTM for more details. Refer Chapter 11: Electrical Characteristics for the operating
ranges and timings of the various parameters and interfaces.
TM
supply control and Self-adaptive Scanning scheme,
EXT_CLK
RST
CS0
SEL0
SEL1
SDA
SCL
SDIN
SDOUT
SCLK
D0…D7
R/W-(WR)
E-(RD
SD/C
TEST_MODE
Figure 1: STV8102 Input/Output Diagram
VDD_D
VDD_A
FT
VDD_BG
A
STV8102
R
D
)
GND_D
GND_A
GND_BG
GND_COL
GND_SENSE
GND_SUB
Columns
C0...C127
Rows
R0
…
R63
VROW_OFF
VCOL_PRE
HSYNC
VSYNC
VHIGH
VDRIVE
VSENSE
VPP
VCAPA_HOLD
STMicroelectronics Confidential Draft of Revision 1.7 4/65
General Overview STV8102
1.1 Bump Die Pad Description
Figure 2: Die Description (Bump-side View)
TOP SIDE
8.58mm
128 pinsx64µm = 8.192mm
80µm
A1
A2
C0
C1
658.95µm
Columns
4245.3µm
128µm
C63
C64
(X=0.0, Y=0.0)
Columns
4245.3µm
C126
B1
B2
C127
80µm
LEFT SIDE
Host pads
13µm
1203.2µm
Dummy (A)
A8
Even Rows
R31
31x64µm = 1984µm
Display pads
Figure 3: COF Alignment and Die Positioning Marks
681µm
R1
VDD_BG
R0
74.7µm
Interface Pins
44 pins 4085.75µm
BOTTOM SIDE
VROW_OFF
R63
R62
31x64µm = 1984µm
FT
Dummy (B)
Odd Rows
B8
R32
1.45mm
1204.45µm
RIGHT SIDE
A
22µm
90µm
20µm
13µm
20µm
90µm
R
METAL X
METAL X
64µm
64µm
13µm
5/65 Draft of Revision 1.7 STMicroelectronics Confidential
13µm
COF Alignment Mark
D
13µm
20µm
22µm
90µm
64µm
13µm
64µm
13µm
Die Positioning Mark
90µm
20µm
13µm
STV8102 General Overview
1.2 Pad Signal Description
Table 1: STV8102 Pad Description (Sheet 1 of 2)
Ball Name Input/Output Description
CS0 IChip select
SD/C
-(WR) I 68XX Parallel interface: read/write or 80XX Parallel interface: write
R/W
) I 68XX Parallel interface: data enable or 80XX Parallel interface: read
E-(RD
D0 to D7 I/O Parallel interface 8 bit data bus (bi-directional pins)
SDOUT O Serial interface data output
SDIN I Serial interface data input
SCLK I Serial interface clock
SCL I I²C bus clock
SDA I/O I²C data input/output
RST
HSYNC O Horizontal synchronization triggering signal
VSYNC O Vertical synchronization triggerin g signal
I Interface data/command selection
I Hardware Reset pin
SEL1 I Interface mode selection
SEL0 I Interface mode selection
VDD_D Supply Low Voltage Digital Supply
VDD_A Supply Low Voltage Analog Supp ly
VDD_BG Supply Low Voltage Reference Supply
GND_D Supply Digital Ground
GND_SUB Supply Substrate Ground
GND_BG Supply Low Voltage Reference Ground
GND_A Supply Analog Ground
TEST_MODE I Must be grounded
GND_COL Supply Analog Ground f or Column Driver
GND_SENSE Supply Ground of current detection for Step-up Circuitry
VSENSE I Current detection of Step-up Circuitry
EXT_CLK I External Clock input
VCAPA_HOLD I Pre-charge supply filtering
VHIGH I High Voltage Step-up Circuit
VDRIVE O Control Signal for Output Voltage Generator
D
R
A
FT
VPP Supply High voltage Supply for Display Addressing
VCOL_PRE I Voltage reference for Column Electrode Pre-charge Sequence
VROW_OFF I Voltage reference for row electro de off-mode
C0 to C127 O OLED Column Driver Output
STMicroelectronics Confidential Draft of Revision 1.7 6/65
General Overview STV8102
Table 1: STV8102 Pad Description (Sheet 2 of 2)
Ball Name Input/Output Description
R0 to R63 O OLED Row Driver Output
1.3 Lead Pad Reference Chart
The reference for the following tables is the center of the die (X = 0.0, Y = 0.0)
Table 2: Top Side (from left to right) (Sheet 1 of 4)
Pad Placements (center), µm Pad Dimensions, µm
Lead Pad Name
XYXY
COL0 -4095.550 658.95 26.000 60.000
COL1 -4031.550 658.95 26.000 60.000
COL2 -3967.550 658.95 26.000 60.000
COL3 -3903.550 658.95 26.000 60.000
COL4 -3839.550 658.95 26.000 60.000
COL5 -3775.550 658.95 26.000 60.000
COL6 -3711.550 658.95 26.000 60.000
COL7 -3647.550 658.95 26.000 60.000
COL8 -3583.550 658.95 26.000 60.000
COL9 -3519.550 658.95 26.000 60.000
COL10 -3455.550 658.95 26.000 60.000
COL11 -3391.550 658.95 26.000 60.000
COL12 -3327.550 658.95 26.000 60.000
COL13 -3263.550 658.95 26.000 60.000
COL14 -3199.550 658.95 26.000 60.000
COL15 -3135.550 658.95 26.000 60.000
COL16 -3071.550 658.95 26.000 60.000
COL17 -3007.550 658.95 26.000 60.000
COL18 -2943.550 658.95 26.000 60.000
COL19 -2879.550 658.95 26.000 60.000
COL20 -2815.550 658.95 26.000 60.000
D
R
A
FT
COL21 -2751.550 658.95 26.000 60.000
COL22 -2687.550 658.95 26.000 60.000
COL23 -2623.550 658.95 26.000 60.000
COL24 -2559.550 658.95 26.000 60.000
COL25 -2495.550 658.95 26.000 60.000
COL26 -2431.550 658.95 26.000 60.000
7/65 Draft of Revision 1.7 STMicroelectronics Confidential
STV8102 General Overview
Table 2: Top Side (from left to right) (Sheet 2 of 4)
Pad Placements (center), µm Pad Dimensions, µm
Lead Pad Name
XYXY
COL27 -2367.550 658.95 26.000 60.000
COL28 -2303.550 658.95 26.000 60.000
COL29 -2239.550 658.95 26.000 60.000
COL30 -2175.550 658.95 26.000 60.000
COL31 -2111.550 658.95 26.000 60.000
COL32 -2047.550 658.95 26.000 60.000
COL33 -1983.550 658.95 26.000 60.000
COL34 -1919.550 658.95 26.000 60.000
COL35 -1855.550 658.95 26.000 60.000
COL36 -1791.550 658.95 26.000 60.000
COL37 -1727.550 658.95 26.000 60.000
COL38 -1663.550 658.95 26.000 60.000
COL39 -1599.550 658.95 26.000 60.000
COL40 -1535.550 658.95 26.000 60.000
COL41 -1471.550 658.95 26.000 60.000
COL42 -1407.550 658.95 26.000 60.000
COL43 -1343.550 658.95 26.000 60.000
COL44 -1279.550 658.95 26.000 60.000
COL45 -1215.550 658.95 26.000 60.000
COL46 -1151.550 658.95 26.000 60.000
COL47 -1087.550 658.95 26.000 60.000
COL48 -1023.550 658.95 26.000 60.000
COL49 -959.550 658.95 26.000 60.000
COL50 -895.550 658.95 26.000 60.000
COL51 -831.550 658.95 26.000 60.000
COL52 -767.550 658.95 26.000 60.000
COL53 -703.550 658.95 26.000 60.000
COL54 -639.550 658.95 26.000 60.000
D
R
A
FT
COL55 -575.550 658.95 26.000 60.000
COL56 -511.550 658.95 26.000 60.000
COL57 -447.550 658.95 26.000 60.000
COL58 -383.550 658.95 26.000 60.000
COL59 -319.550 658.95 26.000 60.000
COL60 -255.550 658.95 26.000 60.000
STMicroelectronics Confidential Draft of Revision 1.7 8/65
General Overview STV8102
Table 2: Top Side (from left to right) (Sheet 3 of 4)
Pad Placements (center), µm Pad Dimensions, µm
Lead Pad Name
XYXY
COL61 -191.550 658.95 26.000 60.000
COL62 -127.550 658.95 26.000 60.000
COL63 -63.550 658.95 26.000 60.000
COL64 64.450 658.95 26.000 60.000
COL65 128.450 658.95 26.000 60.000
COL66 192.450 658.95 26.000 60.000
COL67 256.450 658.95 26.000 60.000
COL68 320.450 658.95 26.000 60.000
COL69 384.450 658.95 26.000 60.000
COL70 448.450 658.95 26.000 60.000
COL71 512.450 658.95 26.000 60.000
COL72 576.450 658.95 26.000 60.000
COL73 640.450 658.95 26.000 60.000
COL74 704.450 658.95 26.000 60.000
COL75 768.450 658.95 26.000 60.000
COL76 832.450 658.95 26.000 60.000
COL77 896.450 658.95 26.000 60.000
COL78 960.450 658.95 26.000 60.000
COL79 1024.450 658.95 26.000 60.000
COL80 1088.450 658.95 26.000 60.000
COL81 1152.450 658.95 26.000 60.000
COL82 1216.450 658.95 26.000 60.000
COL83 1280.450 658.95 26.000 60.000
COL84 1344.450 658.95 26.000 60.000
COL85 1408.450 658.95 26.000 60.000
COL86 1472.450 658.95 26.000 60.000
COL87 1536.450 658.95 26.000 60.000
COL88 1600.450 658.95 26.000 60.000
D
R
A
FT
COL89 1664.450 658.95 26.000 60.000
COL90 1728.450 658.95 26.000 60.000
COL91 1792.450 658.95 26.000 60.000
COL92 1856.450 658.95 26.000 60.000
COL93 1920.450 658.95 26.000 60.000
COL94 1984.450 658.95 26.000 60.000
9/65 Draft of Revision 1.7 STMicroelectronics Confidential
STV8102 General Overview
Table 2: Top Side (from left to right) (Sheet 4 of 4)
Pad Placements (center), µm Pad Dimensions, µm
Lead Pad Name
XYXY
COL95 2048.450 658.95 26.000 60.000
COL96 2112.450 658.95 26.000 60.000
COL97 2176.450 658.95 26.000 60.000
COL98 2240.450 658.95 26.000 60.000
COL99 2304.450 658.95 26.000 60.000
COL100 2368.450 658.95 26.000 60.000
COL101 2432.450 658.95 26.000 60.000
COL102 2496.450 658.95 26.000 60.000
COL103 2560.450 658.95 26.000 60.000
COL104 2624.450 658.95 26.000 60.000
COL105 2688.450 658.95 26.000 60.000
COL106 2752.450 658.95 26.000 60.000
COL107 2816.450 658.95 26.000 60.000
COL108 2880.450 658.95 26.000 60.000
COL109 2944.450 658.95 26.000 60.000
COL110 3008.450 658.95 26.000 60.000
COL111 3072.450 658.95 26.000 60.000
COL112 3136.450 658.95 26.000 60.000
COL113 3200.450 658.95 26.000 60.000
COL114 3264.450 658.95 26.000 60.000
COL115 3328.450 658.95 26.000 60.000
COL116 3392.450 658.95 26.000 60.000
COL117 3456.450 658.95 26.000 60.000
COL118 3520.450 658.95 26.000 60.000
COL119 3584.450 658.95 26.000 60.000
COL120 3648.450 658.95 26.000 60.000
COL121 3712.450 658.95 26.000 60.000
COL122 3776.450 658.95 26.000 60.000
D
R
A
FT
COL123 3840.450 658.95 26.000 60.000
COL124 3904.450 658.95 26.000 60.000
COL125 3968.450 658.95 26.000 60.000
COL126 4032.450 658.95 26.000 60.000
COL127 4096.450 658.95 26.000 60.000
STMicroelectronics Confidential Draft of Revision 1.7 10/65
General Overview STV8102
Table 3: Right Side (from top to bottom)
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
DUMMY_B1 4245.300 600 60.000 26.000
DUMMY_B2 4245.300 520 60.000 26.000
DUMMY_B3 4245.300 60.65 60.000 26.000
DUMMY_B4 4245.300 -3.35 60.000 26.000
DUMMY_B5 4245.300 -67.35 60.000 26.000
DUMMY_B6 4245.300 -131.35 60.000 26.000
DUMMY_B7 4245.300 -540.45 60.000 26.000
DUMMY_B8 4245.300 -604.45 60.000 26.000
Table 4: Bottom Side (from righ t to left) (Sheet 1 of 4)
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
ROW32 4096.950 -681 26.000 60.000
ROW33 4032.950 -681 26.000 60.000
ROW34 3968.950 -681 26.000 60.000
ROW35 3904.950 -681 26.000 60.000
ROW36 3840.950 -681 26.000 60.000
ROW37 3776.950 -681 26.000 60.000
ROW38 3712.950 -681 26.000 60.000
ROW39 3648.950 -681 26.000 60.000
ROW40 3584.950 -681 26.000 60.000
A
FT
R
ROW41 3520.950 -681 26.000 60.000
ROW42 3456.950 -681 26.000 60.000
ROW43 3392.950 -681 26.000 60.000
ROW44 3328.950 -681 26.000 60.000
ROW45 3264.950 -681 26.000 60.000
D
ROW46 3200.950 -681 26.000 60.000
ROW47 3136.950 -681 26.000 60.000
ROW48 3072.950 -681 26.000 60.000
ROW49 3008.950 -681 26.000 60.000
ROW50 2944.950 -681 26.000 60.000
ROW51 2880.950 -681 26.000 60.000
ROW52 2816.950 -681 26.000 60.000
11/65 Draft of Revision 1.7 STMicroelectronics Confidential
STV8102 General Overview
Table 4: Bottom Side (from righ t to left) (Sheet 2 of 4)
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
ROW53 2752.950 -681 26.000 60.000
ROW54 2688.950 -681 26.000 60.000
ROW55 2624.950 -681 26.000 60.000
ROW56 2560.950 -681 26.000 60.000
ROW57 2496.950 -681 26.000 60.000
ROW58 2432.950 -681 26.000 60.000
ROW59 2368.950 -681 26.000 60.000
ROW60 2304.950 -681 26.000 60.000
ROW61 2240.950 -681 26.000 60.000
ROW62 2176.950 -681 26.000 60.000
ROW63 2112.950 -681 26.000 60.000
VROW_OFF 2048.950 -681 26.000 60.000
VROW_OFF 1984.950 -681 26.000 60.000
VCOL_PRE 1920.950 -681 26.000 60.000
VCOL_PRE 1856.950 -681 26.000 60.000
VPP 1792.950 -681 26.000 60.000
VPP 1728.950 -681 26.000 60.000
VDRIVE 1664.950 -681 26.000 60.000
VHIGH 1540.700 -681 26.000 60.000
VCAPA_HOLD 1476.700 -681 26.000 60.000
EXT_CLK 1376.700 -681 26.000 60.000
VSENSE 1274.700 -681 26.000 60.000
GND_SENSE 1168.700 -681 26.000 60.000
GND_COL 1064.900 -681 26.000 60.000
TEST_MODE 964.850 -681 26.000 60.000
GND_A 844.350 -681 26.000 60.000
GND_S 780.350 -681 26.000 60.000
GND_D 663.250 -681 26.000 60.000
D
R
A
FT
GND_D 563.200 -681 26.000 60.000
GND_BG 463.200 -681 26.000 60.000
VDD_A 363.200 -681 26.000 60.000
VDD_D 263.200 -681 26.000 60.000
SEL0 163.200 -681 26.000 60.000
SEL1 63.200 -681 26.000 60.000
STMicroelectronics Confidential Draft of Revision 1.7 12/65
General Overview STV8102
Table 4: Bottom Side (from righ t to left) (Sheet 3 of 4)
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
VSYNC -36.800 -681 26.000 60.000
HSYNC -136.800 -681 26.000 60.000
RST
SDA -336.800 -681 26.000 60.000
SCL -436.800 -681 26.000 60.000
SCLK -536.800 -681 26.000 60.000
SDIN -636.800 -681 26.000 60.000
SDOUT -736.800 -681 26.000 60.000
D0 -836.800 -681 26.000 60.000
D1 -936.800 -681 26.000 60.000
D2 -1036.800 -681 26.000 60.000
D3 -1136.800 -681 26.000 60.000
D4 -1236.800 -681 26.000 60.000
D5 -1336.800 -681 26.000 60.000
D6 -1436.800 -681 26.000 60.000
D7 -1536.800 -681 26.000 60.000
) -1636.800 -681 26.000 60.000
E-(RD
-(WR) -1736.800 -681 26.000 60.000
R/W
SD/C
-236.800 -681 26.000 60.000
FT
A
-1836.800 -681 26.000 60.000
CS0
VDD_BG -2036.800 -681 26.000 60.000
ROW0 -2111.500 -681 26.000 60.000
ROW1 -2175.500 -681 26.000 60.000
ROW2 -2239.500 -681 26.000 60.000
ROW3 -2303.500 -681 26.000 60.000
ROW4 -2367.500 -681 26.000 60.000
ROW5 -2431.500 -681 26.000 60.000
ROW6 -2495.500 -681 26.000 60.000
ROW7 -2559.500 -681 26.000 60.000
ROW8 -2623.500 -681 26.000 60.000
ROW9 -2687.500 -681 26.000 60.000
ROW10 -2751.500 -681 26.000 60.000
ROW11 -2815.500 -681 26.000 60.000
ROW12 -2879.500 -681 26.000 60.000
13/65 Draft of Revision 1.7 STMicroelectronics Confidential
-1936.800 -681 26.000 60.000
R
D
STV8102 General Overview
Table 4: Bottom Side (from righ t to left) (Sheet 4 of 4)
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
ROW13 -2943.500 -681 26.000 60.000
ROW14 -3007.500 -681 26.000 60.000
ROW15 -3071.500 -681 26.000 60.000
ROW16 -3135.500 -681 26.000 60.000
ROW17 -3199.500 -681 26.000 60.000
ROW18 -3263.500 -681 26.000 60.000
ROW19 -3327.500 -681 26.000 60.000
ROW20 -3391.500 -681 26.000 60.000
ROW21 -3455.500 -681 26.000 60.000
ROW22 -3519.500 -681 26.000 60.000
ROW23 -3583.500 -681 26.000 60.000
ROW24 -3647.500 -681 26.000 60.000
ROW25 -3711.500 -681 26.000 60.000
ROW26 -3775.500 -681 26.000 60.000
ROW27 -3839.500 -681 26.000 60.000
ROW28 -3903.500 -681 26.000 60.000
ROW29 -3967.500 -681 26.000 60.000
ROW30 -4031.500 -681 26.000 60.000
ROW31 -4095.500 -681 26.000 60.000
Table 5: Left Side (from bottom to top)
R
Pad Placements Pad Dimensions
Lead Pad Name
XYXY
DUMMY_A8 -4245.300 -603.2 60.000 26.000
DUMMY_A7 -4245.300 -539.2 60.000 26.000
DUMMY_A6 -4245.300 -131.35 60.000 26.000
DUMMY_A5 -4245.300 -67.35 60.000 26.000
D
A
FT
DUMMY_A4 -4245.300 -3.35 60.000 26.000
DUMMY_A3 -4245.300 60.65 60.000 26.000
DUMMY_A2 -4245.300 520 60.000 26.000
DUMMY_A1 -4245.300 600 60.000 26.000
STMicroelectronics Confidential Draft of Revision 1.7 14/65
General Overview STV8102
1.4 Mechanical Dimensions
Table 6: Mechanical Dimensions
Description Dimension
Die Size 8.73mm x 1.6mm
Pad Pitch 64µm (min.), 100µm (max)
Pad Siz e 26µm x 60µm
Wafer Thickness 450µm
Bump Size 40µm x 74µm x 20µm
Bump Characteristics gold, electrolytic
Bump Hardness 30 -80Hv
1.5 Functional Description
The architecture of the STV8102 provides all the functions to drive the OLED displays. The block
diagram gives an overview of the different on-chip components and their links.
Figure 4: STV8102 Block Diagram
I2C Parallel SPI
Interface Interface Interface
Status
Register
Row
Drivers
Screen
Saver
Pattern
Generator
D
Instruction
A
Decoder
Display RAM
64 X 128 bits
R
Self-adaptive
Scanning Control
Column Drivers
FT
Control
Register
Clocks
Generator
Powermizer
Panel
Supply
Reference
Current
The description of the STV8102 functions is given in the following sections, starting with the bus
interfaces.
15/65 Draft of Revision 1.7 STMicroelectronics Confidential
STV8102 Bus Interfaces
2 Bus Interfaces
The STV8102 is always set in a slave configuration whatever the bus choice (the host is always
providing the communication clock). For any kind of communication, the device has to be activated
first by correctly positioning the chip select pins.
Table 7: Chip Select Pins
CS0
0 Communications enabled
1 Interfaces disabled and rese t (device remains f unctional)
Moreover, each received data may be either a graphic data or a device instruction. That has to be
indicated on the SD/C
SD/C
0 Access to the registers (command &/or data)
1 Access to the display RAM (pixel data)
²
In I
C mode, the SD/C pin must be kept at “0”. To provide the widest flexibility and ease of use, the
STV8102 features four different solutions for interfacing with the host controller. The SEL1 and
SEL0 input pins select the appropriate interface as described in Table 9.
SEL1 SEL0 Interface
pin.
Table 8: Data/Instruction Selection
Table 9: Interface Selection
A
Note
Note
FT
00
01Serial
1 0 Parallel (68xx)
1 1 Parallel (80xx)
Non-selected interfaces are reset.
The definitions and the specifications of the signals and timing diagrams given in the following
sections provide functional information of the different interfaces.
2.1 I²C Interface
The I²C interface is compliant with the I²C bus specification and able to work in both Standard
(100kHz) and Fast Speed (400kHz) modes. The write address is 78h and the read address is 79h
for the register access, and 7Ah for RAM write. (No RAM read available).
STMicroelectronics Confidential Draft of Revision 1.7 16/65
²
C (Standard or Fast)
I
R
D
Bus Interfaces STV8102
This bus is intended for communication between ICs. It consists of two lines: one bi-directional for
data signals (SDA) and one input for clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via an active or passive pull-up.
During the communication, the SD/C
MASTER (data_out for transmitter)
Start
I²C Write Address (78h)
SCL
SDA
SD/C
CS0
SDA
SLAVE (data_out for receiver)
MASTER (data_out for transmitter)
SCL
SDA
SD/C
76543210
Start
I²C Write Address (7Ah)
76543210
pin must be kept grounded.
Figure 5: I²C Interface Timing Diagram for Register Write
Data_1 Data_2
76543210
ack
Figure 6: I²C Interface Timing Diagram for RAM Write
Data_1 Data_2
76543210
ack
76543210
ack
FT
76543210
76543210
76543210
Data_i
Data_i
Stop
ack
Stop
CS0
A
SDA
SLAVE (data_out for receiver)
Item Description Min. Typ. Max. Unit
Tscl_cycle 2.5
Tscl_low / Tscl _high 100/100 ns
Tscl_rise / Tscl_fall 15/15 ns
Tdatas / Tdatah Data setup & hold 100/100 ns
Tcs0s / Tcs0h Chip Select setup & hold 120/120 ns
ack
R
Table 10: I²C Interface Write Timing
D
ack
ack
ack
µs
17/65 Draft of Revision 1.7 STMicroelectronics Confidential
STV8102 Bus Interfaces
Figure 7: I²C Interface Read Timing Diagram (Register only)
MASTER (data_out for transmitter)
Start
I²C Read Address (79h)
SCL
SDA
SD/C
CS0
SDA
SLAVE (data_out for receiver)
Item Description Min. Typ. Max. Unit
76543210
ack
76543210
Table 11: I²C Interface Read Timing (Register only)
Status
Stop
nack
Tscl_cycle 2.5
Tscl_low / T scl_high 100/100 ns
Tscl_ri se / Tscl_fall 15/15 ns
Tdatas / Tdatah Data setup & hold 100/100 ns
Tcs0s / Tcs0h Chip Select setup & hold 120/120 ns
2.2 Serial Interface
The STV8102 serial interface is a bi-directional link between the display controller and the
application supervisor. It consists of three lines: SDIN for data input, SDOUT for data output, SCLK
for clock signal plus two control lines: CS0
The SDIN and SDOUT pins can be connected together.
During data transfer, the data line is sampled on the positive SCLK edge shifting bits 8 per 8 starting
from the chip selection.
Figure 8: Serial Peripheral Interface Timing Diagram (Write Mode)
MASTER (transmitter)
SCLK
SDIN
SD/C
76
FT
A
for chip sel ect and SD/ C for command or data selection.
R
Data_1 Data_2
D
54
3
2
1
0
76
54
µs
3
2
1
0
CS0
SDOUT
SLAVE (receiver)
STMicroelectronics Confidential Draft of Revision 1.7 18/65
Bus Interfaces STV8102
Figure 9: Serial Peripheral Interface Timing (Write Mode)
Tsclk_ fall
Tsclk_cycle
SCLK
Tsdins Tsdinh
SDIN
Tsdcs Tsdch
SD/C
Tcs0s Tcs0h
CS0
Table 12: Serial Peripheral Interface Timing (Write Mode)
Item Description Min. Typ. Max. Unit
Tsclk_cycle 250 ns
Tsclk_low /
Tsclk_high
Tsclk_rise / Tsclk_fall 15/15 ns
Tsclk_ highTsckl_ low Tsclk_ rise
100/100 ns
FT
Tsdins / Tsdinh SDIN setup & hold 100/100 ns
Tsdcs / Tsdch SD/C
Tcs0s / Tcs0h Chip Select setup & hold 150/150 ns
Figure 10: Serial Peripheral Interface Timing Diagram for Register Read (only)
MASTER (transmitter)
SCLK
SDIN
SD/C
CS0
SDOUT
SLAVE (receiver)
76
setup & hold 150/150 ns
A
Read Command Status
54
R
3
2
1
0
D
76
54
3
2
1
0
19/65 Draft of Revision 1.7 STMicroelectronics Confidential
STV8102 Bus Interfaces
Figure 11: Serial Peripheral Interface Timing Diagram for Register Read (only)
SCLK
SDOUT
CS0
SD/C
Tsclk_ high
Tsclk_cycle
Tsclk_ rise
Tsclkdatout
Bit 7
Tcs0datout
Tcs0s
= 0
Table 13: Serial Peripheral Interface Timing Diagram for Register Read (only)
Tsckl_ low
Tsclk_ fall
Tsclkdatout
Bit 6
FT
Item Description Min. Typ. Max. Unit
Tsclk_cycle 250 ns
Tsclkdathiz
Bit 0
Tcs0dathiz
Tsclk_low /
Tsclk_high
Tsclk_rise / Tsclk_fall 15/15 ns
Tsclkdatout
Tsclkdathiz
Tcs0datout
Tcs0dathiz
Tcs0s
Data output time after SCLK
falling edge
Data output Hiz state time after
SCLK falling edge
Data output time after CS0
edge
Data output Hiz state time after
rising edge
CS0
D
Chip Select setup before SCLK
rising edge
R
A
falling
100/100 ns
TBD 50 ns
TBD 50 ns
TBD 50 ns
TBD 50 ns
0ns
STMicroelectronics Confidential Draft of Revision 1.7 20/65
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