ST STV7622 User Manual
STV7622
DB1
DB2
DB3
DB4
DB5
DB6
BS1 BS2 DIR CLK1 CLK2 VDD
/STB1
/BLK
POC
OUT1 OUT2 OUT3 ….. …. OUT192
VSSSUB
VCC
Shift register direction
Data decoding
VSSLOG
TEST1
TEST2
VREF
10nF
RS1
RS2
FS1
FS2
Output control / EMI control
VPP
VSSP
Output buffer stage
/STB2
Latch
Q1 Q2 Q3 Q4 Q192
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
3/6/2x3-bit & RSDS
selection
192 output plasma display panel data driver
Preliminary Data
Features
■
192 high-voltage outputs
■
Output pad placements: I-shape
■
90V absolute maximum supply
■
EMI control features:
– SmartSlope
– ConstantSlope
– Spread Spectrum Jitter (SSJ)
■
Configurable data bus:
– 3, 6 or 2 × 3 bits
– TTL and LVCMOS compatible
– RSDS mode
– Single- or dual-edge clocking mode
– 60MHz clock frequency
■
3.3/5V CMOS logic compatible
■
- 60/+24mA source/sink output current
capability
■
BCD Process
■
Packaging according to customer request:
wafer, die, bumped die/wafer, TCP or COF
The input data bus is configured by dedicated
input pins:
●
BS1 and BS2: bus width select (3, 6,
2 × 3 bits or RSDS mode)
●
DIR input: shift register loading direction
The STV7622 output stage integrates several ST
patented functions aimed at reducing EMI without
compromising addressing speed or performance
of the PDP modules.
These functions mainly consist of:
●
SmartSlope: controls the output falling edge
speed /shape
●
ConstantSlope: controls the output rising
edge speed
●
Spread Spectrum Jitter (SSJ): controls the
spread of the output rising edge
The STV7622 is powered by a separate 70V
supply for the high-voltage outputs and a 5V
supply for the logic. All command input levels are
5V CMOS as well as 3.3V compatible.
Figure 1. Block diagram
Description
The STV7622 is a data driver for Plasma Display
Panels (PDP) designed in the ST’s proprietary
BCD high-voltage technology.
It controls up to 192 outputs via an input data bus
(3, 6 or 2 × 3-bits wide) operating at up to 60MHz.
This large number of outputs reduces the number
of connections between the controller board and
the data driver ICs.
The STV7622 contains a new logic input stage
that minimizes EMI resulting from the
transmission of high speed TTL or LVCMOS data
and clock signals. This new input stage is RSDS
compliant. It enables increasing the operating
frequency without compromising noise immunity.
May 2007 Rev 1 1/32
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
32
Contents STV7622
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Output stage description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1 Data input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.2 3 x 64-bit data bus, standard transmission (BS1 = H, BS2 = L) . . . . . . . . . 8
5.3 6 x 32-bit data bus, standard transmission (BS1 = L, BS2 = L) . . . . . . . . . 8
5.4 2 x 3 x 32-bit data bus, standard transmission (BS1 = H, BS2 = H) . . . . . 9
5.5 Differential transmission mode: RSDS (BS1 = L, BS2 = H) . . . . . . . . . . . 10
5.6 Power output block and EMI control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9 AC timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11 Pad dimensions and positions (in µm) . . . . . . . . . . . . . . . . . . . . . . . . . 22
12 Tested wafer disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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STV7622 Block diagram
DB1
DB2
DB3
DB4
DB5
DB6
BS1 BS2 DIR CLK1 CLK2 VDD
/STB1
/BLK
POC
OUT1 OUT2 OUT3 ….. …. OUT192
VSSSUB
VCC
Shift register direction
Data decoding
VSSLOG
TEST1
TEST2
VREF
10nF
RS1
RS2
FS1
FS2
Output control / EMI control
VPP
VSSP
Output buffer stage
/STB2
Latch
Q1 Q2 Q3 Q4 Q192
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
32-bit Shift register
3/6/2x3-bit & RSDS
selection
1 Block diagram
Figure 2. STV7622 block diagram
3/32
Pin description STV7622
2 Pin description
Table 1. Pin description
VPP Supply DC high-voltage supply of power outputs
VCC Supply Analog 5V supply
VDD Supply Digital 5V supply
VSSP Ground Ground for power outputs
VSSSUB Ground Substrate ground
VSSLOG Ground Ground for 5V logic
OUT1 to OUT192 Outputs Power outputs
DB1to DB6 Inputs Shift register inputs
/BLK Input Blanking input
POC Input Power output control input
DIR Input Selection of shift register direction
BS1 and BS2 Inputs Shift register configuration pins (3/6/2 × 3-bits and RSDS selection)
CLK1 and CLK2 Inputs Clock for data shift register
/STB1 and /STB2 Inputs Latch of data to power outputs
RS1 and RS2 Inputs Output rise time selection pins
Pin name Function Description
FS1 and FS2 Inputs Output “slow-slope” fall time selection pins
TEST1 Test pin Must be grounded
TEST2 Test pin Must be grounded
VREF Input
Filter for internal reference - must be connected to ground via a 10nF
capacitor
Note: Inputs /BLK, /STB1 and /STB2 are active Low.
4/32
STV7622 Output stage description
VCC VPP
Output control
Totem
pole
Output 1
to 192
VSSP
OUTn
Output stage
T1
T3
Rising edge
control
Falling edge
control
T4
T2
Delay
Rise time
RS1/RS2
Fall time
FS1/FS2
VCC
3 Output stage description
Figure 3. Output stage description
5/32
Pinout description STV7622
DB6
DB5
DB4
DB3
DB2
DB1
/STB2
/STB1
CLK2
CLK1
VDD3
/BLK
VSSLOG3
POC
VDD4
DUMMY
DUMMY
VREF
DUMMY
VSSLOG4
RS1
VDD5
RS2
VSSLOG5
FS2
VDD6
FS1
VSSLOG6
DIR
VDD7
BS1
VSSLOG7
BS2
VDD8
TEST1
TEST2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VSSP1
VSSP2
VSSP3
VPP1
VPP2
VPP3
DUMMY
VSSLOG1
VSSSUB1
VDD1
VCC1
VSSP4
VSSP5
VSSP6
VPP4
VPP5
VPP6
DUMMY
VSSLOG2
VSSSUB2
VDD2
VCC2
DUMMY
OUT192
OUT191
OUT190
OUT189
OUT188
OUT187
OUT186
OUT185
OUT184
OUT183
OUT182
OUT181
OUT180
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
Y
X
0/0
4 Pinout description
Figure 4. Pinout diagram
In the pinout diagram of Figure 4 above:
●
VDD1 to VDD8 are internally connected. It is not necessary to connect them together
on the tape carrier package (TCP) - the same applies to VCC1 and VCC2.
●
VSSLOG1 to VSSLOG2 are internally connected. It is not necessary to connect them
together on the TCP - the same for VSSSUB1 and VSSSUB2.
●
VSSLOG1 to VSSLOG7 are not internally connected to VSSSUB1 and VSSSUB2. We
recommend shorting them together very close to the die, either on the TCP or at the
TCP connector.
●
VDD1 to VDD8 are not internally connected to VCC1 and VCC2. For good test
coverage, they must not be shorted together on the TCP. In the application, VDD1 to
VDD8, VCC1 and VCC2 must be connected together at the TCP connector level.
●
TEST1 and TEST2 are used to test the device. For good test coverage, they must not
be shorted together on the TCP. In the application, TEST1 and TEST2 must be
6/32
grounded at the TCP connector level.
●
VREF must be connected to ground via a 10nF filter capacitor.
STV7622 Circuit description
5 Circuit description
The STV7622 includes all the logic and power circuits necessary to drive the column
electrodes of a Plasma Display Panel (PDP). A low-voltage logic block manages data
information, and a high-voltage block converts the low-voltage information stored in the logic
block into high-voltage signals applied to the display electrodes.
5.1 Data input block
The Data Bus is TTL- and LVCMOS-compatible and can also operate in an RSDS (Reduced
Swing Differential Signaling) mode. The maximum clock frequency is 60MHz.
The data input block consists of several shift registers operating in parallel to load the binary
values of the digital video. The number of cells in each shift register is defined by the BS pin
as described below in Table 2.
Table 2. BS1/BS2 truth table
BS1 BS2 Shift register configuration
L L 6 × 32 bits
H L 3 × 64 bits
L H RSDS mode
H H 2 × 3 × 32 bits (96 + 96)
For the 3 × 64 bit configuration, only pins DB1, DB2 and DB3 of the input data bus are used,
while for the 6 × 32 and 2 × 3 × 32 bit configurations all 6 bits of the input data bus input,
pins DB1 to DB6, are used.
The DIR input pin is used to select the shift register loading direction.
Data is shifted for each low-to-high transition of the clock signal (CLK1). The maximum
frequency of the clock is 60MHz, which is equivalent to a 360MHz serial shift register for a
6 × 32-bit arrangement.
When the /STB signal goes from high-to-low, data is transferred from the shift register to the
latch and to the power output stages. All output data is stored and held in the latch stage
when the latch input is pulled back High.
The core of the STV7622 is powered by 5V. All logic inputs can be driven either by 5V or
3.3V CMOS logic.
The tables in the following sections describe the position of the first data sampled by the first
rising edge of the CLK1 clock.
7/32
Circuit description STV7622
5.2 3 x 64-bit data bus, standard transmission (BS1 = H, BS2 = L)
The data bus is in 3-bit mode (DB1 to DB3 active) for BS1 = H and BS2 = L.
Data on DB1 is sampled by the first clock pulse and shifted from position 1 to position 190
after 64 clock pulses. The data is then applied to output 190, on the high-to-low transition of
/STB.
Table 3. 3 x 64-bit data bus transmission
BS1 BS2 DIR Input
Clock pulse number
Comment
Position 01 02 03 … 62 63 64
H L L
H L H
DB1
DB2
DB3
DB1
DB2
DB3
OUT
OUT
OUT
OUT
OUT
OUT
01
02
03
190
191
192
04
05
06
187
188
189
07
08
09
184
185
186
184
185
186
07
08
09
187
188
189
04
05
06
190
191
192
01
02
03
Left/Right
shift
Right/Left
shift
5.3 6 x 32-bit data bus, standard transmission (BS1 = L, BS2 = L)
The data bus is in 6-bit mode (DB1 to DB6 active) for BS1 = L and BS2 = L.
Table 4 below describes how data is shifted in the register.
Table 4. 6 x 32-bit data bus transmission
BS1 BS2 DIR Input
L L L
DB1
DB2
DB3
DB4
DB5
DB6
Position 01 02 03
Clock pulse number
OUT
OUT
OUT
OUT
OUT
OUT
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
…
30 31 32
175
181
187
176
182
188
177
183
189
178
184
190
179
185
191
180
186
192
Comment
Left/Right
shift
DB1
DB2
L L H
8/32
DB3
DB4
DB5
DB6
OUT
OUT
OUT
OUT
OUT
OUT
187
188
189
190
191
192
181
182
183
184
185
186
175
176
177
178
179
180
13
14
15
16
17
18
07
08
09
10
11
12
01
02
03
04
05
06
Right/Left
shift
STV7622 Circuit description
5.4 2 x 3 x 32-bit data bus, standard transmission (BS1 = H, BS2 = H)
The data bus is in 2 × 3-bit mode (DB1 to DB6 active) for BS1 = H and BS2 = H. Table 5
below describes how data is shifted in the register.
Table 5. 2 x 3 x 32-bit data bus transmission
BS1 BS2 DIR Input
Clock pulse number
Comment
Position 01 02 03
…
30 31 32
H H L
H H H
DB1
DB2
DB3
DB4
DB5
DB6
DB1
DB2
DB3
DB4
DB5
DB6
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
01
02
03
97
98
99
94
95
96
190
191
192
04
05
06
100
101
102
91
92
93
187
188
189
07
08
09
103
104
105
88
89
90
184
185
186
88
89
90
184
185
186
07
08
09
103
104
105
91
92
93
187
188
189
04
05
06
100
101
102
94
95
96
190
191
192
01
02
03
97
98
99
Left/Right shift
Right/Left shift
9/32
Circuit description STV7622
5.5 Differential transmission mode: RSDS (BS1 = L, BS2 = H)
In differential transmission mode, data is transmitted on two wires, one line transmits the
data value, the other the inverted data. The logic level of the data is determined by the
difference between data and inverted data. Two DB inputs are needed for the transmission
of 1 data value. The sampling clocks, CLK1 and CLK2, as well as strobes STB1/ and STB2
are also transmitted differentially. Data is sampled on the rising and falling edges of the
clock.
Table 6. 2 x 3 x 32-bit data bus transmission - differential mode
BS2 B12 DIR Input CLK1 clock pulse number Comment
H L L
H L H
In differential transmission operating mode, the biasing of the data input bus must be
carefully arranged to reduce static power consumption. In stand-by and non-active modes,
DB1, DB3, DB5, CLK1 and /STB1 should be set High to reduce bias current in the
differential input buffers.
For a High level, all differential pairs should be configured with DB1, DB3, DB5, CLK1 and
/STB1 High and with DB2, DB4, DB6, CLK2 and /STB2 Low.
When operating in differential transmission mode, a 100 ohm (1%) resistor termination must
be connected between:
●
●
●
●
●
Position 01↑ 01↓ 02↑
DB1
DB2
DB3
DB4
DB5
DB6
DB1
DB2
DB3
DB4
DB5
DB6
OUT
OUT
DB1 and DB2
DB3 and DB4
DB5 and DB6
CLK1 and CLK2
STB1 and STB2
…
01 04 07 184 187 190
02 05 08 185 188 191
03 06 09 186 189 192
190 187 184 07 04 01
191 188 185 08 05 02
192 189 186 09 06 03
31↓ 32↑ 32↓
Left/Right
shift
Right/Left
shift
with each resistor placed as close as possible to the STV7622 itself.
10/32
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