ST STPMC1 User Manual

Programmable poly-phase energy calculator IC

Features

■ Supports 1-, 2- or 3-phase WYE and Delta

services, from 2 to 4 wires

■ Computes cumulative active and reactive wide-

band and fundamental harmonic energies

■ Computes active and reactive energies, RMS

and momentary voltage and current values for each phase

■ Supports Rogowski coil, current transformer,

Shunt or Hall current sensors

■ Exclusive ripple-free energy calculation

algorithm

■ Programmable pulsed output

■ Stepper motor outputs

■ Neutral current, temperature, and magnetic

field monitoring

■ OTP memory for configuration and calibration

■ SPI interface

■ Supports IEC 62052-11 / 62053-21 / 62053-23

standards

■ Less than 0.1 % error over 1:1000 dynamic

range

Applications

■ Power metering

Description

The STPMC1 device functions as an energy calculator and is an ASSP designed for effective energy measurement in power line systems utilizing Rogowski, current transformer, Shunt or Hall current sensors. Used in combination with one or more STPMSx ICs, it implements all the functions needed in a 1-, 2- or 3-phase energy

Table 1. Device summary

Order code Temperature range Package Packaging

STPMC1

Datasheet − production data

TSSOP20

meter. It can be coupled with a microprocessor for multi-function energy meters, or it can directly drive a stepper motor for a simple active energy meter. The calculator has five input data pins. The first three receive the voltage and current information of the phases. In fact, each data input processes two ΔΣ signals, multiplexed in time and generated by the STPMSx device. The fourth input receives multiplexed ΔΣ signals also, and can be used to sense the neutral current or another signal - temperature, for example. The fifth input data pin accepts non-multiplexed ΔΣ signals and it can be used for sensing the magnetic field information from a Hall sensor. Four internal hard-wired DSP (digital signal processing) units perform all the computations on the ΔΣ streams in real time by means of ΔΣ arithmetic blocks. This allows the achievement of very high computation precision with fast and efficient digital architecture. All the data recorded by the STPMC1 are accessible through an SPI port, which is also used to configure and calibrate the device. The configuration and calibration data can be saved in a 112-bit OTP block, or dynamically set in microprocessor-based meters.

STPMC1BTR - 40 to 85 °C TSSOP20 (tape and reel) 2500 parts per reel

April 2012 Doc ID 15728 Rev 6 1/77

This is information on a product in full production.

www.st.com

Contents STPMC1

Contents

1 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1 Measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.3 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.1 General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9.3 Resetting the STPMC1 (status bit HLT) . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.4 Clock generator (bits MDIV, FR1, HSA) . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.5 Zero crossing detection (signal ZCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.6 Period and line voltage measurement (status bits: LIN, BFR, LOW, BFF) 23

9.7 Single wire operation mode: SWM (status bits: NAH, BFR,

configuration bit FRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.8 Load monitoring (status bit BIL, configuration bit LTCH) . . . . . . . . . . . . . 26

9.9 Error detection (status bits: BCF, PIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.10 Tamper detection module (status bits: BCS, BSF, BIF,

configuration bit ENH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.10.1 Sum of currents is above tamper threshold (status bit BCS) . . . . . . . . . 28

9.10.2 Phase sequence is wrong (status bit BSF) . . . . . . . . . . . . . . . . . . . . . . 31

9.10.3 Phase active powers do not have the same sign (status bit BIF) . . . . . 32

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STPMC1 Contents

9.10.4 EMI is detected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.11 Energy to frequency conversion (configuration bits: APL, KMOT,

LVS, FUND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.12 Using STPMC1 in microcontroller based meter - peripheral

operating mode (configuration bits: APL, KMOT, LVS, FUND) . . . . . . . . . 34

9.13 Driving a stepper motor - standalone operating mode

(configuration bits: APL, LVS, KMOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.14 Negative power accumulation (configuration bit ABS, status bit SIGN) . . 37

9.15 Phase delay calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.16 Calibration (configuration bits: PM, TCS, CIX, CVX, CCA, CCB, CPX) . . 40

9.16.1 Voltage and current channels calibration . . . . . . . . . . . . . . . . . . . . . . . . 40

9.16.2 Phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.16.3 Mutual current compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.17 Data records map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.17.1 Group 0 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.17.2 Group 1 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.17.3 Group 2 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.17.4 Group 3 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.17.5 Group 4 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.17.6 Group 5 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.17.7 Group 6 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.17.8 Parity calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.18 Status bits map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.19 Configuration bits map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.20 Mode signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.21 SPI interface (configuration bit SCLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.21.1 Remote reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.21.2 Reading data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.21.3 Writing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.21.4 Interfacing the standard 3-wire SPI with STPMC1 SPI . . . . . . . . . . . . . 65

9.21.5 Permanent writing of the CFG bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10 Energy calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.1 Active energy calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.2 Reactive energy calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.3 Voltage and current RMS values calculation . . . . . . . . . . . . . . . . . . . . . . 71

Doc ID 15728 Rev 6 3/77

Contents STPMC1

10.4 Energy integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.5 Fundamental power calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4/77 Doc ID 15728 Rev 6

STPMC1 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Programmable pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6. Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 7. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Input channels from the STPMSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Frequency settings through MDIV and FR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11. CLK pin frequency settings through HSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. STPMC1 configuration for STPMS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Good frequency ranges for different clock source values. . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. No-load detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 15. Tamper conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 16. Pin description versus SYS configuration (uX and iX represent the voltage

and the current signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 17. Energy registers LSB value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 18. LED pin configuration for APL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 19. LED pin configuration for APL = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 20. Configuration of MOP and MON driving signals with APL = 1, 2, 3 . . . . . . . . . . . . . . . . . . 36

Table 21. LED pin configuration for APL = 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 22. Accumulation mode for negative power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 23. f Table 24. f Table 25. f

Table 26. Phase compensation for PM = 0, TCS = 0, fline = 50 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 27. Phase compensation for PM = 0, TCS = 1, fline = 50 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 28. Phase compensation for PM = 1, fline = 50 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 29. Mutual current compensation matrix for single-phase systems (SYS > 3) . . . . . . . . . . . . . 45

Table 30. Mutual current compensation matrix for three-phase systems (SYS < 4) . . . . . . . . . . . . . 45

Table 31. 3-phase status bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 32. X-phase status bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 33. Configuration bits map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 34. Mode signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 35. Functional description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

frequency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

phc

frequency values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

phc

frequency settings for PM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

phc

Doc ID 15728 Rev 6 5/77

List of figures STPMC1

List of figures

Figure 1. STPMC1 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Application schematic in standalone operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. Application schematic using an MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Supply current vs. supply voltage, T Figure 6. Digital voltage regulator: line - load regulation. (f

across V

and VSS; 1 µF across VDD and V

Figure 7. Gain response of decimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Connections of oscillator: (a) quartz, (b) external source . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. ZCR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10. LIN and BFR behavior when f

line

Figure 11. Currents of the three phase system in example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 12. Stepper driving signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Phase delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14. Group 0 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 15. Group 1 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 16. Group 2 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 17. Group 3 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 18. Group 4 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 19. Group 5 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 20. Group 6 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 21. Timing for providing remote reset request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 22. Timing for data records reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 23. Data records reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 24. Timing for writing configuration and mode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

> f

MCLK

= 25°C (f

= 4.194 MHz, f

XTAL1

SSA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

= 0; 100 nF

XTAL1

; TA = 25 °C). . . . . . . . . . . . . . . . . . . . . . 17

= 8.192 MHz) . 17

XTAL1

6/77 Doc ID 15728 Rev 6

STPMC1 Functional block diagram

1 Functional block diagram

Figure 1. STPMC1 device block diagram

VDD

VCC

XTAL1

XTAL2

Band Gap

VDD

Linear Vregs

VBG

BIAS

Clock

Generator

POR

CONFIGURATORS

VOTP

112 OTP

STEPPER

DRIVER

MOP

MON

CLK

DAx

DAN

DAH

DAx-C

DAx-V

DAN-C

DAN-V

ENH

xDSP

NDSP

SPI Interface

SCS SYN

SCL

SCS SYN

SCL

Energy to Freq

Converters

SDA

Note: DAx stands for DAR, DAS, DAT, and xDSP stands for RDSP, SDSP, TDSP.

LED

VSSA

VSS

Doc ID 15728 Rev 6 7/77

Pin configuration STPMC1

2 Pin configuration

Figure 2. Pin connections (top view)

MON

MOP

SCS

OTP

DAH

DAR

DAS

STPMC1

LED

SDATD

SCLNLC

XTAL1

XTAL2

SYN

SSA

CLK

DAN

DAT

Table 2. Pin description

Pin n° Symbol Type

(1)

Name and function

1 MON D / P O Programmable output pin, see

2 MOP D / P O Programmable output pin, see

3 SCS D I Digital input pin, see

Ta bl e 5

Ta b l e 5

4VDDA O 1.8 V output of internal low drop regulator which supplies the digital core

A GND Ground level for pad-ring and power supply return

6VCCP I Supply voltage

OTP

P I Supply voltage for OTP cells

8 DAH D I Input for non-multiplexed ΔΣ signals

9 DAR D I Input for multiplexed ΔΣ R-phase signals

10 DAS D I Input for multiplexed ΔΣ S-phase signals

11 DAT D I Input for multiplexed ΔΣ T-phase signals

12 DAN D I Input for multiplexed ΔΣ PTAT and neutral signal

13 CLK D O 2 mA clock output for STPMSx devices

14 V

SSA

15 SYN D I/O Programmable input/output pin, see

A GND Ground level of core

Ta bl e 5

16 XTAL2 A Crystal oscillator pin

17 XTAL1 A Crystal oscillator pin

18 SCLNLC D I/O Programmable input/output pin, see

19 SDATD D I/O Programmable input/output pin, see

20 LED D O Programmable output pin, see

1. A: Analog, D: Digital, P: Power, I: Input, O: Output, GND: Ground

8/77 Doc ID 15728 Rev 6

Ta bl e 5

Ta b l e 5

STPMC1 Maximum ratings

3 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

DC input voltage - 0.3 to 6 V

Current on any pin (sink/source) ± 150 mA

Input voltage at all pins -0.3 to V

+ 0.3 V

Input voltage at OTP pin - 0.3 to 25 V

OTP

ESD Human body model (all pins) ± 3.5 kV

STG

Operating ambient temperature - 40 to 85 °C

Junction temperature - 40 to 150 °C

Storage temperature range - 55 to 150 °C

Note: Absolute maximum ratings are those values beyond which damage to the device may occur.

Functional operation under these condition is not implied.

Table 4. Thermal data

Symbol Parameter Value Unit

thJA

1. This value refers to single-layer PCB, JEDEC standard test board.

Thermal resistance junction-ambient 114.5

(1)

°C/W

Doc ID 15728 Rev 6 9/77

Functions STPMC1

4 Functions

Table 5. Programmable pin functions

Programmable pin Standalone mode (APL = 2 or 3) Peripheral mode (APL = 0 or 1)

MON Output for stepper node (MB) - charge pump Watchdog reset

MOP Output for stepper node (MA) - charge pump

LED 3-phase energy pulsed output Programmable energy pulsed output

SCLNLC No load indicator

SYN-NP Negative power indicator

SCS SPI data transmission enable

ZCR

SPI interfaceSDATD Tamper indicator

signal

10/77 Doc ID 15728 Rev 6

STPMC1 Application

5 Application

Figure 3. Application schematic in standalone operating mode

N R S T

Current

Current Sensor

Sensor

Voltage

Voltage Sensor

Sensor

Current

Current Sensor

Sensor

Voltage

Voltage Sensor

Sensor

Current

Current Sensor

Sensor

Voltage

Voltage Sensor

Sensor

STPMS1

3 V to 5.5 V

VCC

DAR

DAS

DAT

DAN

DAH

CLK XTAL1 XTAL2

Stepper

Stepper Counter

Counter

MOPMONVOTP

STPMC1

VSS

LED

SCS

SYN-NP

SCL-NC

SDA-TD

VDD

VSSA

Pulsed output

Negative power

No load condition

Tamper Detection

Current

Current Sensor

Sensor

Figure 4. Application schematic using an MCU

N R S T

Current

Sensor

Voltage

Sensor

Current

Sensor

Voltage

Sensor

Current

Sensor

Voltage

Sensor

STPMS1

3 V to 5.5 V

Zero

Crossing

DAR

DAS

STPMC1

DAT

DAN

DAH

STPMC1

CLK XTAL1 XTAL 2

MOPMONVOTPVCC

VSS

Watchdog

LED

SCS

SYN-NP

SCL-NC

SDA-TD

VDD

VSSA

Pulsed

Pulsed Output

Output Energy

Energy

To MCU

Current

Sensor

TEMP

Sensor

STPMS1

Doc ID 15728 Rev 6 11/77

Application STPMC1

Table 6. Typical external components

Function Component Value Tolerance Unit

Reads or writes to a calculator device via SPI and performs computation

Measurement reference clock Crystal oscillator

Interface R-phase voltage, current STPMSx --- --- ---

Interface S-phase voltage, current STPMSx --- --- ---

Interface T-phase voltage, current STPMSx --- --- ---

Interface PTAT, neutral current STPMSx --- --- ---

Interface PTAT or hall STPMSx --- --- ---

Low-end user interface Stepper counter

Microprocessor --- --- ---

4.194

8.192

4.915

9.830

± 30 ppm MHz

Note: The components listed above refer to a typical metering application. In any case, STPMC1

operation is not limited to the choice of these external components.

12/77 Doc ID 15728 Rev 6

STPMC1 Electrical characteristics

6 Electrical characteristics

(VCC = 5 V, TA= - 40 to + 85 °C, 100 nF across VCC and VSS; 1 µF across VDD and V

SSA

unless otherwise specified).

Table 7. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Energy measurement accuracy

General Section

ΔI

POR Power on reset on V

OTP

Effective bandwidth Limited by digital filtering

5400Hz

Operating supply voltage 3.17 5.5 V

Supply current. Configuration registers cleared or device locked

=4.194MHz;

XTAL1

=3.2V; CL=100nF; no

loads

567mA

Increase of supply current per configuration bit, during

=4.194MHz; VCC=3.2V 100 µA/bit

XTAL1

programming

=4.194MHz 2.5 V

XTAL1

Digital supply voltage 1.70 1.80 1.90 V

OTP programming voltage 14 20 V

OTP programming current per bit

Single bit programming 5 mA

OTP

LATCH

OTP programming time per bit Single bit programming 500 µs

Current injection latch-up immunity

Digital I/O (DAH, DAR, DAS, DAT, DAN, CLK, SDA, SCS, SYN, LED)

Input high voltage Other pins 0.75V

Input low voltage Other pins 0.25V

Output high voltage IO=-2mA VCC-0.4 V

Output low voltage IO=+2mA 0.4 V

Pull up current 15 µA

Transition time C

LOAD

=50pF, V

=5V 10 ns

Power I/O (MOP, MON)

Output high voltage IO=-16mA 0.9V

Output low voltage IO=+16mA 0.1V

Transition time C

LOAD

=50pF, V

=5V 10 ns

300 mA

Doc ID 15728 Rev 6 13/77

Electrical characteristics STPMC1

Table 7. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Crystal oscillator

XTAL1

MCLK

CLK

Input high voltage 1.2 V

Input low voltage 0.6 V

Input current on XTAL2 V

External resistor 1 4 MΩ

External capacitors 22 pF

Nominal output frequency

Internal clock frequency see

Output CLK pin frequency

SPI interface timing

SCLKr

SCLKw

OFF

SYN

Data read speed TA= 25°C 32 MHz

Data write speed TA= 25°C 100 kHz

Data setup time 20 ns

Data hold time 0 ns

Data driver on time 20 ns

Data driver off time 20 ns

SYN active width 2/f

=5.3V -1 +1 µA

4.000 4.194 4.915

8.000 8.192 9.830

Ta bl e 1 0

HSA

= 0 f

= 1 f

HSA

8.000 8.192 9.830 MHz

XTAL1

MHz

Note: Typical value, not production tested.

14/77 Doc ID 15728 Rev 6

STPMC1 Terminology

7 Terminology

7.1 Measurement error

The error associated with the energy measured by the STPMC1 is defined as:

EnergyTrue)reading(1SPMC

−

EnergyTrue

7.2 Conventions

The lowest analog and digital power supply voltage is called VSS which represents the

system ground (GND). All voltage specifications for digital input/output pins are referred to

GND.

Positive currents flow into a pin. “Sinking current” is the current flowing into the pin, and so it

is positive. “Sourcing current” is the current flowing out of the pin, and so it is negative.

Signal timing specifications treated by a digital control part are relative to XTAL1. This signal

is provided from the crystal oscillator or from an external source as specified in paragraph

9.4

ErrorPercentage

Signal timing specifications of the SPI interface are relative to the SCLNLC. There is no

direct relationship between the clock (SCLNLC) of the SPI interface and the clock of the

DSP block (XTAL1).

A positive logic convention is used in all equations.

Doc ID 15728 Rev 6 15/77

Terminology STPMC1

7.3 Notation

Table 8. Notation

Label Description

uVoltage

i Current

P Active energy full bandwidth

F Active energy fundamental

Q Reactive energy full bandwidth

R Reactive energy fundamental

PIN Pin names are UPPERCASE

CFG

Phase X voltage (X = R, S, T)

Phase X current (X = R, S, T)

Neutral current

Phase X RMS voltage (X = R, S, T)

Phase X RMS current (X = R, S, T)

X energy type per Y phase X = P, F, Q, R Y = R, S, T or Σ for 3-phase

Configuration bit names are UNDERLINED

SIG

Internal signals and status bits are in

ITALICS

16/77 Doc ID 15728 Rev 6

STPMC1 Typical performance characteristics

8 Typical performance characteristics

Figure 5. Supply current vs. supply voltage, TA = 25°C (f

7,5

6,5

(mA)

5,5

4,5

3 3,5 4 4,5 5 5,5 6

(V)

XTAL1

Figure 6. Digital voltage regulator: line - load regulation. (f

1 µF across V

2,5

and V

; TA = 25 °C)

SSA

= 4.194 MHz, f

ICC25°C

ICC-40°C

ICC85°C

= 0; 100 nF across VCC and VSS;

XTAL1

= 8.192 MHz)

XTAL1

1,5

(V)

0,5

0123456

-0,5

(V)

Doc ID 15728 Rev 6 17/77

Typical performance characteristics STPMC1

Figure 7. Gain response of decimator

Flat band (10Hz Flat band (10Hz – 300Hz)

3 dB band (4Hz 3 dB band (4Hz –700Hz)

18/77 Doc ID 15728 Rev 6

STPMC1 Theory of operation

9 Theory of operation

9.1 General operation

The STPMC1 (also called a calculator) is an ASSP designed for effective measurement in

power line systems utilizing the Rogowski coil, current transformer, Shunt or Hall current

sensors. This device, used with the STMicroelectronics STPMSx companion chip (an

analog front-end device), can be implemented as standalone or as a peripheral in a

microprocessor based 1-, 2- or 3-phase energy meter.

The calculator consists of three sections: analog, digital and OTP (see

● The analog section is composed of a band-gap voltage reference and a low-drop

voltage regulator.

● The digital section consists of a system control, clock generator, three PDSP and a

NDSP, a SPI interface.

● The 112-bit OTP block and the 16 system signals, used for testing, configuration and

calibration purposes, are controlled through SPI by means of a dedicated command set.

The calculator has five input data pins, of which four are fed by signals generated by the

STPMSx, see

Ta b le 9

Three of them (DAR/DAS/DAT) are used to receive multiplexed signals of voltage and

current, implementing energy measurement in 1-, 2- and 3-phase (3 and 4 wires) systems.

After being de-multiplexed, each phase input is sent to the correspondent DSP unit that

processes voltage and current information and performs energy calculation, according to

the settings of the configuration bits (see

The DAN input, which also receives a multiplexed signal output from STPMSx device, is

typically used to monitor neutral current for anti tampering functions in 1-, 2- and 3-phase (4

wires) systems. Normally the STPMSx monitors current and voltage but in case of neutral

monitoring the voltage channel can be connected to a different type of sensor, for example a

temperature sensor.

The fifth input data pin (DAH) accepts non-multiplexed ΔΣ signals. It can be used for EMI

sensing through Hall sensors or for temperature sensing.

Table 9. Input channels from the STPMSx

Ta bl e 33

Figure 1

Channel name Property Signal 1 Signal 2

DAR Multiplexed Voltage Current

DAS Multiplexed Voltage Current

DAT Multiplexed Voltage Current

DAN Multiplexed Temperature Current

DAH Not multiplexed EMI or temperature

The companion chip (STPMSx) embeds 2 ΔΣ ADC converters and the necessary logic

capable of providing the multiplexed ΔΣ streams.

See the STPMSx documentation for more details.

Doc ID 15728 Rev 6 19/77

Theory of operation STPMC1

These four multiplexed signals are separated, by a digital de-multiplexer, back into eight ΔΣ

signals, called streams. The signal coming from the voltage channel of the STPMSx is

named with the suffix V, while the stream coming from the current channel is named with the

suffix C. For example, the voltage stream of the S-phase is named DAS-V.

Then, each pair of phase the voltage and current stream coming from DAR, DAS and DAT is

connected to a dual-channel RDSP, SDSP, TDSP unit (i.e. DAR-V and DAR-C are

connected to RDSP).

Each phase voltage input stream is proportional to phase voltage u. Each phase current

input stream is proportional to derivation of phase current di/dt, when it originates from

Rogowski coil, or to phase current i, when it originates from Shunt or CT or Hall sensor. In

this case a derivative is inserted into the voltage channel to get a stream proportional to

du/dt. The sensors differ from each other for sensitivity, phase error and susceptibility to

external EM fields.

Each of these DSP units performs the following:

● checks the integrity of the streams

● calibrates streams

● filters both streams with a dedicated decimation filter

● computes active and reactive energies, momentary and RMS values for voltage and

current, period of power line voltage signal.

In each DSP there are calibrators capable of adjusting the readings ±12.5%.

The power computer does the final calculations of the value and direction of the power and

checks for no-load condition.

Another dual DSP unit, called NDSP, processes the streams coming from DAN and DAH. In

fact, using the ENH

bit (see

Ta bl e 33

), the user can select either the voltage stream of the DAN pin (DAN-V) or the DAH stream as the input of the NDSP unit, while the current stream DAN-C is always processed as neutral current.

In its voltage channel, the NDSP unit uses a 2 s time multiplex to process two streams. During the first half of the interval the voltage input stream is processed (which can be DANV or DAH, according to the ENH

bit), while during the second half a stream constituted by

the sum of all four calibrated currents (i.e. DAR-C + DAS-C + DAT-C + DAN-C).

In its current channel the NDSP unit process the current stream of the neutral conductor as follows:

● checks the integrity of stream

● calibrates the stream

● filters the stream with a dedicated decimation filter

● computes momentary and RMS values of the stream

● if no errors have been detected in the phase timing, computes phase frequency,

integrates the phase powers by means of 3-input integrators of energies and generates all pulse output signals.

When the DAH input stream is selected, it is checked to detect an external magnetic influence (EMI) to the meter.

20/77 Doc ID 15728 Rev 6

STPMC1 Theory of operation

The calculator, thanks to its flexibility, can work in all worldwide distribution network standards. By programming the SYS

OTP bits, it is possible to implement the following systems:

● 3-phase, 4-wire RSTN, 4-system RSTN (tamper);

● 3-phase, 4-wire RSTN, 3-system RST;

● 3-phase, 3-wire RST_, 3-system RST_ (tamper);

● 3-phase, 3-wire RST_, 2-system R_T_ (Aron);

● 2-phase, 3-wire _STN, 2-system _ST_ (America);

● 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:coil);

● 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:shunt);

● 1-phase, 2-wire __TN, 1-system __T_.

The results of all DSP units are available as pulse frequency on pin LED, MOP and MON, which can also drive a stepper counter, and as states on the digital outputs of device or as data bits in data records, which can be read from the device by means of SPI interface from pins SDA, SNC, SCL and SYN. This system bus interface is also used during temporary or permanent programming OTP bits and system signals or to execute a remote reset request.

A logic block common to all DSP units performs other operations like:

● selecting the valid phase period result from which line frequency is computed in NDSP

unit

● checking the equality of phase angles between all three phase voltages

● preparing current values for compensation of external intermediate phase magnetic

influences

● checking the sum of currents

● computing intermediate phase voltages

● combining the 3-phase status bits

● performing a watchdog user function

After the device is fully tested, configured and calibrated, a dedicated bit of the OTP block, called TSTD, can be written permanently in order to prevent the change of any configuration bit.

9.2 Power supply

The supply pins for the analog part are VCC and VSS. The VCC is the power input of the 1.8 V low drop regulator, band-gap reference and bias generators.

From the V used to power the OTP module and digital core. The V for all the internal signals. 100 nF low ESR capacitors should be connected between V and V

to the device.

The STPMC1 contains a power on reset (POR) detection circuit. If the V than 2.5 V then the STPMC1 goes into an inactive state, all the functions are blocked asserting a reset condition. This is useful to ensure correct device operation at power-up and during power-down. The power supply monitor has built-in hysteresis and filtering, which gives a high degree of immunity from false triggering due to noisy supplies. A bandgap voltage reference (VBG) of 1.23 V ±1% is used as a reference voltage level

pin a linear regulator generates the +1.8 V voltage supply level (VDD) which is

, and 1 µF between VDD and V

pin represents the reference point

. All these capacitors must be placed very close

SSA

supply is less

Doc ID 15728 Rev 6 21/77

Theory of operation STPMC1

source for the linear regulator. Also, this module produces several bias currents and voltages for all other analog modules and for the OTP module.

9.3 Resetting the STPMC1 (status bit

HLT

The STPMC1 has no reset pin. The device is automatically reset by the power-on-reset detection circuit (POR) when the V

crosses the 2.5 V value, but it can be reset also

through the SPI interface through a dedicated remote reset request (RRR) command (see paragraph

9.21

for RRR details).

The reset through SPI is used during production testing or in an application with some onboard microprocessors when a malfunction of the device is detected.

Resetting the STPMC1 causes all the functional modules of STPMC1 to be cleared, including the OTP shadow latches (see paragraph

9.19

for an OTP shadow latch memory description). In case of reset through SPI the mode signals (see paragraph description of the mode signals) are not cleared.

In cases of reset caused by the POR circuit all blocks of the digital part, except the SPI interface, are held in a reset state for 125 ms after the reset condition. When the reset is performed through SPI, no delayed turn-on is generated.

During the device reset, the status bit

HLT

is held high, meaning that data read from the

device register are not valid.

9.4 Clock generator (bits MDIV, FR1, HSA)

All the internal timing of the STPMC1 is based on the XTAL1 signal. This signal can be generated in two different ways:

● Quartz: the oscillator works with an external crystal.

● External clock: the clock is provided by an external source connected to XTAL1.

)

9.20

for a

The suggested circuits are depicted in

Figure 8. Connections of oscillator: (a) quartz, (b) external source

22/77 Doc ID 15728 Rev 6

Figure 8

STPMC1 Theory of operation

The clock generator is responsible for two tasks. The first is to retard the turn-on of some functional blocks after POR in order to help a smooth start of external power supply circuitry by keeping off all major loads. For this reason, all blocks of the digital part, except the SPI interface, are held in a reset state for 125 ms after a power on reset (see

Section 9.3

). The second task of the clock generator is to provide all necessary clocks for the digital part. In this task, a MDIV nominal frequency value from XTAL1 (f Four nominal frequencies are possible through proper setting of the MDIV

Ta bl e 10

and FR1 programming bits are used to inform the device about the

XTAL1

and FR1 bits (see

The internal master clock f

Table 10. Frequency settings through MDIV

XTAL1

4.194 MHz 0 0 8.389 MHz

4.915 MHz 0 1 9.830 MHz

8.192 MHz 1 0 8.192 MHz

9.830 MHz 1 1 9.830 MHz

1. 4 MHz and 8 MHz clock are also supported. MDIV and FR1 have to be set as for 4.194 MHz and 8.192

MHz respectively.

Through the HSA bit the frequency of the output pin CLK (f the STPMSx devices, can be derived as reported in

Table 11. CLK pin frequency settings through HSA

HSA (1 bit) f

To properly work with STPMS2, the clock configurations in Moreover, with STPMS2 companion chip the PM

Table 12. STPMC1 configuration for STPMS2

is derived from f

MCLK

MDIV (1 bit) FR1 (1 bit) f

as shown in

XTAL1

and FR1

Ta bl e 11

Ta bl e 10

(1)

), which provides the clock for

CLK

STPMC1

CLK

/ 4

XTAL1

/ 2

XTAL1

Ta bl e 12

must be used.

bit must always be set.

MCLK

MDIV (1 bit) HSA (1 bit) f

00f

10f

01f

9.5 Zero crossing detection (signal

The STPMC1 has a zero crossing detection circuit on the voltage channel that can be used to synchronize some utility equipment to zero crossing or max of line voltage events. This circuit produces the internal signal the line voltages and a rising edge every peak (positive or negative) of one of the line voltages.

ZCR

that has a falling edge every zero crossing of one of

Doc ID 15728 Rev 6 23/77

ZCR

CLK

/ 4

XTAL1

/ 4

XTAL1

/ 2

XTAL1

)

Theory of operation STPMC1

The

ZCR

Figure 9.

signal is a 3-phase voltage zero cross signal. It is the result of a XNOR of the of each phase. The is 300 Hz signal. The

ZCR

of each of the three-phases is a 100 Hz signal, so a 3-phase

ZCR

signal is available on the MOP pin only when the STPMC1 works

as a peripheral with the configuration bit APL

ZCR

signal

=0.

ZCR ZCR

9.6 Period and line voltage measurement (status bits:

LOW, BFF

From voltage channels, a base frequency signal voltage is rising and it is low when the line voltage is falling, so that, the sign of dv/dt. With further elaboration, the

A period meter, which is counting up pulses of f period of voltage channel base frequency and checks if the voltage signal frequency is in the band going from f

This is done, phase by phase, by means of the signal and it is used to reset the period meter.

Table 13. Good frequency ranges for different clock source values

4.194 MHz 8.389 MHz 32.0 Hz 128.0 Hz

4.915 MHz 9.830 MHz 37.5 Hz 150.0 Hz

8.192 MHz 8.192 MHz 31.3 Hz 125.0 Hz

9.830 MHz 9.830 MHz 37.5 Hz 150.0 Hz

XTAL

If the counted number of f

equivalent pulses or if the counting is never stopped (no more base frequency exceeds the lower limit and an error flag the 8-bit status byte of each phase (see

)

MCLK

/(2

LIN

is obtained, which is high when the line

ZCR

signal is also produced.

/8 reference signal, measures the

MCLK

- 23) ≈ f

freq. min. = f

/8 pulses between two trailing edges of

MCLK

/218 to f

MCLK

/216.

MCLK

LIN

, which trailing edge is extracted

/218 freq. max. = f

BFR

Ta bl e 32

LIN

signal represents

LIN

is higher than the

LIN

trailing edge), the

is set. This error flag is part of

LIN, BFR

MCLK

24/77 Doc ID 15728 Rev 6

+ 53 hidden pages