■ Integrated linear voltage regulators for digital
and analog supply
■ Selectable RC or crystal oscillator
■ Supports 50 - 60 Hz - IEC62052-11, IEC62053-
2x specifications
■ Less than 0.1% error in the 1000:1 range
■ Precision voltage reference: 1.23 V with 30
ppm/°C max
Description
The STPM10 is designed for effective
measurement of active, reactive and apparent
energy in a power line system using current
transformer and shunt sensors. The device can
be implemented for peripheral measurement in a
microcontroller-based single-phase or poly-phase
energy meter. The STPM10 consists of two main
sections: analog and digital. The analog part is
composed of preamplifier and first-order sigmadelta A/D converter blocks, a band-gap voltage
reference and low-drop voltage regulator. The
digital part is composed of system control,
oscillator, hard-wired DSP and SPI interface.
There is also an internal volatile memory, which is
Table 1.Device summary
STPM10
with tamper detection
TSSOP20
controlled through the SPI by means of a
dedicated command set. The configured bits are
used for configuration and calibration purposes.
From a pair of sigma-delta output signals
produced by the analog section, the DSP unit
computes the amount of active, reactive and
apparent energy consumed, as well as the RMS
and instantaneous voltage and current values.
The results of the computation are available as
pulse frequencies and states on the digital
outputs of the device, or as data bits in a data
stream, which can be read from the device by
means of the SPI interface. The system bus
interface is also used for temporary programming
of bits of internal volatile memory. The STPM10
generates an output signal with a pulse frequency
proportional to the energy, and this signal is used
in the calibration phase of the energy metering
application.
Order codeTemperature rangePackagePackaging
STPM10BTR- 40 to 85 °CTSSOP20 (tape and reel)2500 parts per reel
A OUT1.8 V output of internal low drop regulator which supplies the digital core
GNDGround
P INSupply voltage
P OUTOutput of internal low drop regulator
A OUT3 V output of internal low drop regulator which supplies the analog part
A INPositive input of primary current channel
A INNegative input of primary current channel
A INPositive input of secondary current channel
A INNegative input of secondary current channel
A INPositive input of voltage channel
A INNegative input of voltage channel
15SYND I/OSPI interface pin
Description
16CLKINA INCrystal oscillator input
17CLKOUTA OUTCrystal oscillator output
18SCLD I/OSPI interface clock pin
19SDAD I/OSPI interface data pin
20LEDD OActive energy pulsed output
1. A: analog, D: digital, P: power
Doc ID 17728 Rev 37/51
Maximum ratingsSTPM10
3 Maximum ratings
Table 3.Absolute maximum ratings
SymbolParameterValueUnit
V
I
V
V
CC
PIN
ID
IA
DC input voltage-0.3 to 6V
Current on any pin (sink/source)± 150mA
Input voltage at digital pins (SCS, ZCR, WDG, SYN, SDA,
SCL, LED)
Input voltage at analog pins (I
IP1
, I
, I
, I
IN1
, VIP, VIN)-0.7 to 0.7V
IP2
IN2
-0.3 to V
+ 0.3V
CC
ESDHuman body model (all pins)± 3.5kV
T
T
OP
T
J
STG
Operating ambient temperature- 40 to 85°C
Junction temperature- 40 to 150°C
Storage temperature range- 55 to 150°C
Note:Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these condition is not implied.
Table 4.Thermal data
SymbolParameterValueUnit
R
thJA
1. This value is based on a single-layer PCB, JEDEC standard test board.
Thermal resistance junction-to-ambient114.5
(1)
°C/W
8/51Doc ID 17728 Rev 3
STPM10Electrical characteristics
4 Electrical characteristics
VCC = 5 V, TA = 25 °C,100 nF to 1 µF between V
and V
Table 5.Electrical characteristics
, 100 nF to 1 µF between VCC and VSS unless otherwise specified.
SS
and VSS, 100 nF to 1 µF between V
DDA
SymbolParameterTest conditionsMin.Typ.Max.Unit
Energy measurement accuracy
f
e
e
e
Effective bandwidthLimited by digital filtering (-3 dB)4800Hz
BW
Accuracy of active powerOver 1 to 1000 of dynamic range0.1%
AW
Accuracy of reactive powerOver 1 to 1000 of dynamic range0.1%
RW
Accuracy of apparent powerOver 1 to 500 of dynamic range0.1%
SW
SNRSignal-to-noise ratioOver the entire bandwidth52db
PSRR
Power supply DC rejection
DC
Voltage signal: 200 mV
Current signal: 10 mV
f
= 4.194 MHz
CLK
rms
rms
/50Hz
/50Hz
0.2%
VCC=3.3V±10%, 5V±10%
PSRR
Power supply AC rejection
AC
Voltage signal: 200 mV
Current signal: 10 mV
f
= 4.194 MHz
CLK
=3.3 V+0.2 V
V
CC
VCC=5.0 V+0.2 V
rms
rms
/50 Hz
rms
/50 Hz
rms
1@100 Hz
1@100 Hz
0.1%
General section
DDD
V
I
Operating supply voltage3.1655.5V
CC
Supply current. Configuration
CC
registers cleared
PORPower on reset on V
V
V
f
CLK
f
LINE
I
LATCH
Analog inputs (I
V
f
ADC
f
SPL
Analog supply voltage2.853.003.15V
DDA
Digital supply Voltage1.7251.801.875V
DDD
Oscillator clock frequency
Nominal line frequency4565Hz
Current injection latch-up
immunity
, I
IP1
IN1
Maximum input signal levels
MAX
A/D converter bandwidth10kHz
A/D sampling frequencyF
4 MHz; V
8 MHz; V
CC
=5 V34mA
CC
=5 V56mA
CC
2.5V
MDIV bit=04.0004.194MHz
MDIV bit=18.0008.192MHz
300mA
, I
, I
, VIP, VIN)
IP2
IN2
Voltage channel-0.3+0.3V
Gain 8X-0.15+0.15V
Current channels:
Gain 32X-0.035+0.035
/4Hz
CLK
Doc ID 17728 Rev 39/51
Electrical characteristicsSTPM10
Table 5.Electrical characteristics (continued)
SymbolParameterTest conditionsMin.Typ.Max.Unit
V
Z
Z
G
I
Amplifier offset±20mV
OFF
VIP, VIN impedance
IP
I
, I
, I
, I
IN
IP1
IN1
Current channels gain error±10%
ERR
Voltage channel leakage
VL
current
IP2
impedance
IN2
Over the total operating voltage
range
Over the total operating voltage
range
Channel disabled (PST=0 to 1
Current channel leakage
I
IL
current
CH2 disabled if CSEL=0; CH1
disabled if CSEL=1) or device off
Input enabled-1010µA
Digital I/O Characteristics (SDA, CLKIN, CLKOUT, SCS, SYN, LED)
SDA, SCS, SYN, LED0.75V
V
Input high voltage
IH
CLKIN1.5
SDA, SCL, SYN, LED0.25V
V
V
V
I
t
Input low voltage
IL
Output high voltageIO=-2 mAVCC-0.4V
OH
Output low voltageIO=+2 mA0.4V
OL
Pull up current15µA
UP
Transition timeC
TR
CLKIN0.8
=50 pF10ns
LOAD
Crystal oscillator (see circuit Figure 19)
100400kΩ
100kΩ
-11µA
-11µA
CC
CC
V
V
I
Input current on CLKIN1µA
I
R
External resistor14MΩ
P
CpExternal capacitors22pF
4.004.194
f
CLK
I
CLKIN
R
t
Nominal output frequency
8.008.192
Settling currentf
Settling resistor12kΩ
SET
Frequency jitter1ns
JIT
= 4 MHz4060µA
CLK
On chip reference voltage
Reference voltage1.23V
V
REF
Reference accuracy±1%
Temperature coefficientAfter calibration3050
T
C
SPI interface timing
F
SCLKr
Data read speedAfter calibration32MHz
10/51Doc ID 17728 Rev 3
MHz
ppm/
°C
STPM10Electrical characteristics
Table 5.Electrical characteristics (continued)
SymbolParameterTest conditionsMin.Typ.Max.Unit
F
SCLKw
t
t
DH
t
ON
t
OFF
t
SYN
Data write speed100kHz
Data setup time20ns
DS
Data hold time0ns
Data driver on time20ns
Data driver off time20ns
SYN active width2/f
CLK
s
Doc ID 17728 Rev 311/51
TerminologySTPM10
5 Terminology
5.1 Measurement error
The error associated with the energy measurement made by the STPM10 is defined as:
Percentage error = [STPM10 (reading) - true energy] / true energy
5.2 ADC offset error
This is the error due to the DC component associated with the analog inputs of the A/D
converters. Due to the internal automatic DC offset cancellation, the STPM10 measurement
is not affected by DC components in the voltage and current channel. The DC offset
cancellation is implemented in the DSP.
5.3 Gain error
The gain error is gain due to the signal channel gain amplifiers. This is the difference
between the measured ADC code and the ideal output code. The difference is expressed as
percentage of the ideal code.
5.4 Power supply DC and AC rejection
This parameter quantifies the STPM10 measurement error as a percentage of the reading
when the power supplies are varied. For the PSRRAC measurement, a reading at two
nominal supply voltages (3.3 and 5 V) is taken. A second reading is obtained with the same
input signal levels when an AC (200 mV
Any error introduced by this AC signal is expressed as a percentage of the reading. For the
PSRRDC measurement, a reading at two nominal supply voltages (3.3 and 5 V) is taken. A
second reading is obtained with the same input signal levels when the supplies are varied ±
10%. Any error introduced is again expressed as a percentage of the reading.
/100 Hz) signal is introduced on the supplies.
RMS
5.5 Conventions
The lowest analog and digital power supply voltage is called VSS, which represents system
ground (GND). All voltage specifications for digital input/output pins are referred to GND.
Positive currents flow into a pin. Sinking current refers to the current flowing into the pin, and
thus it is positive. Sourcing current means that the current is flowing out of the pin, so it is
negative.
Timing specifications of signals treated by the digital control part are relative to CLKOUT.
This signal is provided by the 4.194 MHz nominal-frequency crystal oscillator or from the
internal RC oscillator. An external source of 4.194 MHz or 8.192 MHz can also be used.
Timing specifications of signals from the SPI interface are relative to the SCL, and there is
no direct relationship between the clock (SCL) of the SPI interface and the clock of the DSP
block. A positive logic convention is used in all equations.
12/51Doc ID 17728 Rev 3
STPM10Typical performance characteristics
6 Typical performance characteristics
Figure 3.Supply current vs. supply voltage,
T
= 25 °C (f = 4.194MHz, 8.192MHz)
A
Figure 5.RC oscillator: frequency jitter vs.
temperature
Figure 4.RC oscillator frequency vs. V
R = 12 kΩ, T
= 25 °C
A
CC
,
Figure 6.Analog voltage regulator: line - load
regulation
Figure 7.Digital voltage regulator: line - load
regulation
Doc ID 17728 Rev 313/51
Figure 8.Voltage channel linearity at
different V
voltages
CC
Typical performance characteristicsSTPM10
Figure 9.Power supply AC rejection vs. V
CC
Figure 11. Error over dynamic range gain
dependence
Figure 10. Power supply DC rejection vs. V
CC
Figure 12. Primary current channel linearity at
different V
CC
Figure 13. Gain response of ΔΣ A/D converters
14/51Doc ID 17728 Rev 3
STPM10Theory of operation
7 Theory of operation
7.1 General operation description
The STPM10 is capable of performing measurements of active, reactive and apparent
energy, RMS and instantaneous voltage and current values, and line frequency information.
Most of the functions are fully programmable using internal configuration bits accessible
through the SPI interface. The STPM10 works as a peripheral in microcontroller-based
metering systems. The ZCR and WDG pins are used to provide zero-crossing and watchdog information, and the SPI pins are used to communicate with the microcontroller.
The STPM10 includes volatile internal registers that hold the useful information for the
metering system. Two kinds of active energy are available: wide-band active energy (AW)
which includes all harmonic content (also called type 0) and fundamental active energy
(AF), limited to the 1st harmonic (also called type 1). This latter energy value is obtained by
filtering type 0 active energy. Both the two active energies are stored in up-down counting
accumulator registers with a 20-bit length. Reactive and apparent energies are also
available with a 20-bit accumulation.
The STPM10 also provides the RMS values for voltage and current. Due to the modest
dynamic variation of the voltage, the RMS value is stored with a resolution of 11 bits, while
the RMS current value has a resolution of 16 bits. The instantaneous (momentary) sampled
value of voltage and current are also available with a resolution of 11 and 16 bits,
respectively. The line frequency value is stored with a resolution of 14 bits.
Due to the proprietary energy computation algorithm, the STPM10 calibration is quick and
simple, allowing calibration at only one point over the entire current range.
The configuration and calibration parameters must be downloaded in the internal nonvolatile memory of STPM10 at power-up.
7.2 Analog inputs
Input amplifiers
The STPM10 has one fully differential voltage input channel and two fully differential current
input channels.
The voltage channel consists of a differential amplifier with a gain of 4. The maximum
differential input voltage for the voltage channel is ± 0.3 V.
The two current channels are multiplexed (seeChapter 7.9 for details) to provide a single
input to a preamplifier with a gain of 4. The output of this preamplifier is connected to the
input of a programmable gain amplifier (PGA) with possible gain selections of 2 and 8. The
total gain of the current channels are then 8 and 32. The gain selections are made by writing
to the gain register, and they can be different for the two current channels. If the tamper
function is not used, the secondary current can be disabled.
The maximum differential input voltage is dependent on the selected gain, in accordance
with Ta bl e 6 .
Doc ID 17728 Rev 315/51
Theory of operationSTPM10
Table 6.Gain of voltage and current channels
Voltage channelsCurrent channels
GainMax input voltage (V)GainMax input voltage (V)
4±0.30
8X±0.15
32X±0.035
The gain register is included in the device configuration register with the address name
PST. The table below shows the gain configuration according to the register values:
Table 7.Configuration of current sensors
PrimarySecondary
GainSensorGainSensorPSTTMP
8CTDisabledDisabled00
32ShuntDisabledDisabled10
8
CT
832Shunt11
8CT0 1
Configuration
Bits
Configuration
Bits
Note:If the device is used in configuration PST = 1, TMP = 1 (primary channel with CT, secondary
channel with Shunt), the shunt Ks must always be equal to one fourth of the current
transformer Ks.
Both the voltage and current channels implement an active offset correction architecture
which provides the benefit of avoiding any offset compensation.The analog voltage and
current signals are processed by the Σ Δ analog-to-digital converters, which feed the hardwired DSP. The DSP implements an automatic digital offset cancellation that makes it
possible to avoid any manual offset calibration on the analog inputs.
7.3 ΣΔ A/D converters
Analog-to-digital conversion in the STPM10 is carried out using two first-order Σ Δ
converters. The device performs A/D conversions of analog signals on two independent
channels in parallel. The current channel is multiplexed as a primary or secondary current
channel in order to perform the tamper function, if enabled. The converted Σ Δ signals are
supplied to the internal hard-wired DSP unit, which filters and integrates these signals in
order to boost the resolution and to yield all the necessary signals for the computations.
A Σ Δ modulator converts the input signal into a continuous serial stream of 1’s and 0’s at a
rate determined by the sampling clock. In the STPM10, the sampling clock is equal to
f
/4.
CLK
The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is
subtracted from the input signal. If the loop gain is high enough, the average value of the
DAC output (and therefore the bit stream) can approach that of the input signal level. When
a large number of samples are averaged, a very precise value for the analog signal is
obtained. This averaging is carried out in the DSP section, which implements decimation,
16/51Doc ID 17728 Rev 3
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