ST STMPE812A User Manual
with PWM and dedicated RESET pin
Features
■ Integrated 4-wire resistive touchscreen
controller, pen-down/real-time mode, fullyautonomous
■ 12-bit ADC for high-resolution touchscreen
■ Operating voltage 1.65 - 3.6 V
■ Low power consumption:
– Hibernation mode: 0.5
– Active mode: 100
■ Auto-hibernation and hotkey wake-up features
■ Up to 3 GPIOs with alternate functions
– 1 PWM controller
– 1 general purpose 12-bit ADC input
– Optional interrupt output pin
■ Dedicated reset input pin
■ 400 kHz I
■ 8 kV HBM, 1 kV CDM ESD protection on
2
C interface
X+/X-/Y+/Y-
■ 2 kV HBM, 250 V CDM ESD protection on all
other pins
µA
µA
STMPE812A
Touchscreen controller S-Touch
CSP 12
(2.17 x 1.67 mm)
Description
The STMPE812A is a 4-wire resistive
touchscreen controller with 4-bit port expander
integrated.
The touchscreen controller is designed to be fully
autonomous, requiring only minimal CPU
intervention for sampling, filtering and preprocessing operations.
®
Applications
■ Portable media players
■ Game consoles
■ Mobile and smart phones
Table 1. Device summary
Order code Package Packaging
STMPE812ABJR CSP 12 (2.17 x 1.67 mm) Tape and reel
July 2011 Doc ID 18225 Rev 4 1/53
www.st.com
53
Contents STMPE812A
Contents
1 STMPE812A functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 STMPE812A registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Auto-increment/non auto-increment address . . . . . . . . . . . . . . . . . . . . . . 18
7 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9 ADC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.1 Register map for PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.2 Interrupt of PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11 Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.1 Touchscreen controller detection sequence . . . . . . . . . . . . . . . . . . . . . . . 32
11.2 3 modes of acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.3 Touchscreen controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.4 Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/53 Doc ID 18225 Rev 4
STMPE812A Contents
12 GPIO port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.2 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14 Package mechanical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Doc ID 18225 Rev 4 3/53
STMPE812A functional overview STMPE812A
1 STMPE812A functional overview
The STMPE812A consists of the following blocks:
2
● I
C interface
● GPIO/PWM controller
● Touchscreen controller (TSC)
● Analog-to-digital converted (ADC)
● Driver and switch control unit
Figure 1. STMPE812A block diagram
Tou ch
VDD
GND
Power
Power
Management
Management
Tou ch
Screen
Screen
Drivers and
Drivers and
Switches
Switches
X+
X+
X-
XY+
Y+
Y-
Y-
SDA
SCL
2%3%4.
43#4OU CHSCREENCONTROLLER
!$#!NALOGTO
$IGITAL#ONVERTER
I2C InterfaceI2C Interface
TSC
TSCTSC
ADC
ADCADC
GPIO/PWM
GPIO/PWM
Controller
Controller
POR
PORPOR
Reset
Reset
System
System
M
U
X
'0)/!$#07-
'0)/!$$2
'0)/).4
!-6
4/53 Doc ID 18225 Rev 4
STMPE812A STMPE812A functional overview
1.1 Pin configuration and functions
Figure 2. Pin configuration (top through view)
8
!
6##
!
0
!
Table 2. Pin assignments
9
"
0
"
0
"
8
#
2%3%4.
#
3$!
#
9
$
'.$
$
3#,
$
!-6
Pin Name Current capacity Function
B3 Y+ 50 mA current limit Y+
C3 X- 50 mA current limit X-
D3 Y- 50 mA current limit Y-
Active low RESET (3.6 V tolerant within VCC valid
range). Typical reset filter duration is 788 ns at
CC
.
1.8 V V
C2 RESETN
+8 mA/-12 mA at
3.3 V
Can be > 80 mA
D2 GND
load at touchscreen
Ground
and GPIO drive
2
C clock (fail safe, tolerant to 3.6 V regardless of
D1 SCL -4 mA
I
VCC)
Doc ID 18225 Rev 4 5/53
STMPE812A functional overview STMPE812A
Table 2. Pin assignments (continued)
Pin Name Current capacity Function
2
C data (fail safe, tolerant to 3.6 V regardless of
C1 SDA -4 mA
B1 P2
+8 mA/-12 mA at
3.3 V
I
)
V
CC
GPIO-2/ INT (3.6 V tolerant within V
range)
CC
valid
A1 P1
B2 P0
A2 V
CC
+8 mA/-12 mA at
3.3 V
+8 mA/-12 mA at
3.3 V
Can be > 80 mA
load at touchscreen
and GPIO drive
GPIO-1/ADC/PWM (3.6 V tolerant within V
range except VIN_ADC must be less than VCC)
GPIO-0/ADDR (3.6 V tolerant within V
range)
1.65 - 3.6 V core/IO supply (0.1 µF decoupling
cap)
No low-voltage detection for POR
20 µs POR from power stable
A3 X+ 50 mA current limit X+
Note: All I/O operates on VCC. All I/O tolerant up to 3.6 V, across VCC = 1.65 - 3.6 V
8 kV HBM ESD on all touchscreen pins (+/- 8 kV vs GND)
0.5 µA max input leakage as input, across V
range (GPIO, SCL/SDA)
CC
4 µs hardware filter on the 3 GPIOs as input
CC
CC
valid
valid
6/53 Doc ID 18225 Rev 4
STMPE812A STMPE812A functional overview
1.2 Typical application
Figure 3. Typical application
6
6##
).40
3#,
3$!
2%3%4.
!$$20
34-0%!
'.$
0
WIRE
RESISTIVE
TOUCHSCREEN
#ANBEUSEDAS!$#
07-OR'0)/
!-6
Doc ID 18225 Rev 4 7/53
I2C interface STMPE812A
2 I2C interface
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
address, there is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from
the bus by not responding to the transaction.
Figure 4. I
SDA
SCL
2
C timing diagram
tHD:STAtBUF
tR
SP
tHIGH
tLOW
tHD:STA
tF
tSU:DAT
tHD:DAT
SR
Table 3. I2C timing
Symbol Parameter Min Typ Max Unit
f
SCL
t
LOW
t
HIGH
t
F
t
HD:STA
SCL clock frequency 0 - 400 kHz
Clock low period 1.3 - - µs
Clock high period 600 - - ns
SDA and SCL fall time Note
START condition hold time (after this
period the first clock is generated)
(1)
- 300 ns
600 - - ns
tSU:STOtSU:STA
P
AI00589
t
SU:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
1. Minimum TF is subject to system capacitive load (C
START condition setup time (only relevant
for a repeated start period)
Data setup time 100 - - ns
Data hold time 0 - - µs
STOP condition setup time 600 - - ns
Time the bus must be free before a new
transmission can start
LOAD
8/53 Doc ID 18225 Rev 4
600 - - ns
1.3 - - µs
) condition.
STMPE812A I2C interface
2.1 I2C features
The features that are supported by the I2C interface are listed below:
2
● I
C slave device
● Operates at V
● Compliant to Philips I
● Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
2
● I
C address in 0x41 (0x82/83 including Rd/Wr bit) or 0x40 (0x80/81 including Rd/Wr
bit)
The slave address is selected by the state of P0 pin. The state of the pin is read upon reset
and then the pin can be configured for normal operation. The pin shall have an external pullup or pull-down to set the address.
Table 4. Slave address
(1.65 V - 3.6 V)
CC
ADDR (P0) 7-bit I2C slave address
2
C specification version 2.1
040h
141h
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
2
next I
C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
2.2 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Doc ID 18225 Rev 4 9/53
I2C interface STMPE812A
Table 5. Operating modes
Mode Byte Programming sequence
Read ≥1
Write ≥1
Start, Device address, R/W
Restart, Device address, R/W
= 0, Register address to be read
= 1, Data Read, Stop
If no Stop is issued, the Data Read can be continuously performed. If
the register address falls within the range that allows an address autoincrement, then the register address auto-increments internally after
every byte of data being read. For register address that falls within a
non-incremental address range, the address is kept static throughout
the entire read operations. Refer to the memory map table for the
address ranges that are auto and non-increment.
Start, Device address, R/W
= 0, Register address to be written, Data
Write, Stop
If no Stop is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address autoincrement, then the register address auto-increments internally after
every byte of data being written in. For those register addresses that
fall within a non-incremental address range, the address is kept static
throughout the entire write operation. Refer to the memory map table
for the address ranges that are auto and non-increment.
10/53 Doc ID 18225 Rev 4
STMPE812A I2C interface
Figure 5. Read and write modes (random and sequential)
One byte
Read
More than one byte
More than one byte
Read
One byte
Write
Read
Start
Start
Start
Start
Device
Address
Device
Address
Device
Address
Device
Address
Master
Slave
R/W=0
R/W=0
R/W=0
R/W=0
Ack
Ack
Ack
Ack
Reg
Address
Reg
Address
Reg
Address
Reg
Address
Device
Ack
Address
Device
Ack
Address
Restart
Data
to be
Ack
written
R/W=1
Ack
Ack
R/W=1
Stop
Ack
Data
Read
Data
Read
Stop
No Ack
Ack
Data
Read + 1
Ack
Data
Read + 2
Stop
No Ack
Ack
Data to
Write
Data to
Ack
Write + 1
Ack
Write + 2
Data to
Ack
Stop
AM04175V1
Doc ID 18225 Rev 4 11/53
I2C interface STMPE812A
2.3 Read operation
A write is first performed to load the register address into the Address Counter but without
sending a Stop condition. Then, the bus master sends a reStart condition and repeats the
Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the
content of the addressed byte. If no additional data is to be read, the bus master must not
acknowledge the byte and terminates the transfer with a Stop condition.
If the bus master acknowledges the data byte, then it can continue to perform the data
reading. To terminate the stream of data bytes, the bus master must not acknowledge the
last output byte, and be followed by a Stop condition. If the address of the register written
into the Address Counter falls within the range of addresses that has the auto-increment
function, the data being read is coming from consecutive addresses, which the internal
Address Counter automatically increments after each byte output. After the last memory
address, the Address Counter 'rolls-over' and the device continues to output data from the
memory address of 0x00. Similarly, for the register address that falls within a non-increment
range of addresses, the output data byte comes from the same address (which is the
address referred by the Address Counter).
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an
acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a
low state, then the slave device terminates and switches back to its idle mode, waiting for
the next command.
2.4 Write operations
A write is first performed to load the register address into the Address Counter without
sending a Stop condition. After the bus master receives an acknowledgement from the slave
device, it may start to send a data byte to the register (referred by the Address Counter).
The slave device again acknowledges and the bus master terminates the transfer with a
Stop condition.
If the bus master needs to write more data, it can continue the write operation without
issuing the Stop condition. Whether the Address Counter autoincrements or not after each
data byte write depends on the address of the register written into the Address Counter.
After the bus master writes the last data byte and the slave device acknowledges the receipt
of the last data, the bus master may terminate the write operation by sending a Stop
condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the
next data byte write.
12/53 Doc ID 18225 Rev 4
STMPE812A Power supply
3 Power supply
The STMPE812A GPIO operates from a supply pin VCC. For better resolution and noise
immunity, V
Power up reset
The STMPE812A is equipped with an internal POR circuit that holds the device in reset
state, until the V
above 2.8 V is recommended.
CC
supply input is valid. The internal POR is tied to the VCC supply pin.
CC
Doc ID 18225 Rev 4 13/53
Charge pump STMPE812A
4 Charge pump
The STMPE812A is integrated with an internal charge-pump. The charge pump is required
for any ADC/TSC operations when V
Activating the charge pump when V
device.
is less than 2.5 V.
CC
> 2.5 V may result in permanent damage of the
CC
14/53 Doc ID 18225 Rev 4
STMPE812A Power modes
5 Power modes
The STMPE812A operates in a 2 states: active and hibernate.
Active:
– Whenever PEN-DOWN is detected, the device remains in active mode
– Whenever PWM is active, the device remains in active mode
– Whenever ADC is active, the device remains in ACTIVE MODE
Hibernate:
-PWM/ADC must be “off” (clock disable bit SET)
-Any GPIO input, with interrupt enabled, causes a transition to “active” state, if an input
change is detected.
-Pen down even causes transition to “active” state if the touchscreen controller is enabled.
Table 6. Power mode
Power mode Active Hibernate
Current consumption 280 µA (max)
GPIO hotkey Yes Yes
(1)
1.0 µA (max.)
Touchscreen Yes Yes
2
Interface (I
1. At Vcc=1.8V, TCS running at 100sets of X/Y per second, MAV disabled.
C) Yes Yes
Doc ID 18225 Rev 4 15/53
Power modes STMPE812A
Figure 6. Power modes state diagram
ACTIVE
Soft -Reset, Reset input
I2C activity,
No activity
(about 33 μs)
STMPE812A is in
active mode if PWM
is running
Touch, Hotkey
AUTO -
HIBERNATE
On power up reset, device goes to active state. However, as all the functional blocks are
clocked off by default, no touch/hotkey activity is possible. If there are no I
POR
Reset Input
2
C activities,
AM04141V1
device goes into auto-hibernate mode automatically.
The auto-hibernate feature of STMPE812A is always enabled. Whenever there is a period of
inactivity, the device enters this mode to reduce power consumption. On detection a touch,
correctly addressed I
2
C data, GPIO activity, the device wakes up immediately.
As the device is able to wake up very quickly, there is no loss of touch data.
16/53 Doc ID 18225 Rev 4
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