ST STMPE812A User Manual

STMPE812A

Touchscreen controller S-Touch® with PWM and dedicated RESET pin

Features

■Integrated 4-wire resistive touchscreen controller, pen-down/real-time mode, fullyautonomous

■12-bit ADC for high-resolution touchscreen

■Operating voltage 1.65 - 3.6 V

■Low power consumption:

–Hibernation mode: 0.5 µA

–Active mode: 100 µA

■Auto-hibernation and hotkey wake-up features

■Up to 3 GPIOs with alternate functions

–1 PWM controller

–1 general purpose 12-bit ADC input

–Optional interrupt output pin

■Dedicated reset input pin

■400 kHz I2C interface

■8 kV HBM, 1 kV CDM ESD protection on X+/X-/Y+/Y-

■2 kV HBM, 250 V CDM ESD protection on all other pins

CSP 12 (2.17 x 1.67 mm)

Description

The STMPE812A is a 4-wire resistive touchscreen controller with 4-bit port expander integrated.

The touchscreen controller is designed to be fully autonomous, requiring only minimal CPU intervention for sampling, filtering and preprocessing operations.

Applications

■Portable media players

■Game consoles

■Mobile and smart phones

Table 1.	Device summary
	Order code	Package	Packaging
	STMPE812ABJR	CSP 12 (2.17 x 1.67 mm)	Tape and reel
July 2011		Doc ID 18225 Rev 4	1/53
			www.st.com

Contents	STMPE812A

Contents

1	STMPE812A functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
	1.1	Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	1.2	Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
2	I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.1	I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.2	Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	2.3	Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	2.4	Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
3	Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
4	Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
5	Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
6	STMPE812A registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	6.1	Auto-increment/non auto-increment address . . . . . . . . . . . . . . . . . . . . . .	18
7	System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
8	Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
9	ADC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
10	PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	10.1	Register map for PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	10.2	Interrupt of PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
11	Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
	11.1	Touchscreen controller detection sequence . . . . . . . . . . . . . . . . . . . . . . .	32
	11.2	3 modes of acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	11.3	Touchscreen controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	11.4	Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39

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STMPE812A Contents

12	GPIO port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
13	Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
	13.1	DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
	13.2	AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44

14 Package mechanical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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STMPE812A functional overview	STMPE812A

1 STMPE812A functional overview

The STMPE812A consists of the following blocks:

●I2C interface

●GPIO/PWM controller

●Touchscreen controller (TSC)

●Analog-to-digital converted (ADC)

●Driver and switch control unit

Figure 1. STMPE812A block diagram

	VDD	Power
	GND	Management
	SDA	I2C Interface
	SCL

Touch	X+
Screen	X-
Drivers and	Y+
Switches	Y-
TSC
ADC	'0)/ !$# 07-
	M
	'0)/ !$$2
GPIO/PWM	U
Controller	X
	'0)/ ).4

2%3%4.

Reset

43# 4OUCHSCREEN CONTROLLERC POR System

!$# !NALOGGTO $IGITALI#ONVERTER

!- 6

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STMPE812A	STMPE812A functional overview

1.1Pin configuration and functions

Figure 2. Pin configuration (top through view)

8	9	8	9
!	"	#	$
6##	0	2%3%4.	'.$
!	"	#	$
0	0	3$!	3#,
!	"	#	$

!-6

	Table 2.	Pin assignments
	Pin	Name	Current capacity	Function
	B3	Y+	50 mA current limit	Y+
	C3	X-	50 mA current limit	X-
	D3	Y-	50 mA current limit	Y-
	C2	RESETN	+8 mA/-12 mA at	Active low RESET (3.6 V tolerant within VCC valid
			3.3 V	range). Typical reset filter duration is 788 ns at
				1.8 V VCC.
			Can be > 80 mA
	D2	GND	load at touchscreen	Ground
			and GPIO drive
	D1	SCL	-4 mA	I2C clock (fail safe, tolerant to 3.6 V regardless of
				VCC)

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STMPE812A functional overview				STMPE812A
	Table 2.	Pin assignments (continued)
	Pin	Name	Current capacity	Function
	C1	SDA	-4 mA	I2C data (fail safe, tolerant to 3.6 V regardless of
				VCC)
	B1	P2	+8 mA/-12 mA at	GPIO-2/ INT (3.6 V tolerant within VCC valid
			3.3 V	range)
	A1	P1	+8 mA/-12 mA at	GPIO-1/ADC/PWM (3.6 V tolerant within VCC valid
			3.3 V	range except VIN_ADC must be less than VCC)
	B2	P0	+8 mA/-12 mA at	GPIO-0/ADDR (3.6 V tolerant within VCC valid
			3.3 V	range)
			Can be > 80 mA	1.65 - 3.6 V core/IO supply (0.1 µF decoupling
				cap)
	A2	VCC	load at touchscreen
				No low-voltage detection for POR
			and GPIO drive	20 µs POR from power stable
	A3	X+	50 mA current limit	X+
Note:	All I/O operates on VCC. All I/O tolerant up to 3.6 V, across VCC = 1.65 - 3.6 V
	8 kV HBM ESD on all touchscreen pins (+/- 8 kV vs GND)

0.5 µA max input leakage as input, across VCC range (GPIO, SCL/SDA) 4 µs hardware filter on the 3 GPIOs as input

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STMPE812A	STMPE812A functional overview

1.2Typical application

Figure 3. Typical application

6

6##
).44 0		WIRE
		RESISTIVE
3#,		TOUCHSCREEN
3$! 34-0% !
2%3%4.	0	#ANNBE USEDDAS !$# 07OR '0)/
!$$2 0
'.$

!-6

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I2C interface	STMPE812A

2 I2C interface

For the bus master to communicate to the slave device, the bus master must initiate a Start condition and be followed by the slave device address. Accompanying the slave device address, there is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation.

If a match occurs on the slave device address, the corresponding device gives an acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction.

Figure 4. I2C timing diagram
SDA
tBUF			tHD:STA			tHD:STA
			tR	tF
SCL
				tHIGH	tSU:DAT	tSU:STA	tSU:STO
	P	S		tLOW	tHD:DAT	SR	P
							AI00589
Table 3.	I2C timing

Symbol	Parameter	Min	Typ	Max	Unit
fSCL	SCL clock frequency	0	-	400	kHz
tLOW	Clock low period	1.3	-	-	µs
tHIGH	Clock high period	600	-	-	ns
tF	SDA and SCL fall time	Note(1)	-	300	ns
tHD:STA	START condition hold time (after this	600	-	-	ns
	period the first clock is generated)
tSU:STA	START condition setup time (only relevant	600	-	-	ns
	for a repeated start period)
tSU:DAT	Data setup time	100	-	-	ns
tHD:DAT	Data hold time	0	-	-	µs
tSU:STO	STOP condition setup time	600	-	-	ns
tBUF	Time the bus must be free before a new	1.3	-	-	µs
	transmission can start

1. Minimum TF is subject to system capacitive load (CLOAD) condition.

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STMPE812A	I2C interface

2.1I2C features

The features that are supported by the I2C interface are listed below:

●I2C slave device

●Operates at VCC (1.65 V - 3.6 V)

●Compliant to Philips I2C specification version 2.1

●Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes

●I2C address in 0x41 (0x82/83 including Rd/Wr bit) or 0x40 (0x80/81 including Rd/Wr bit)

The slave address is selected by the state of P0 pin. The state of the pin is read upon reset and then the pin can be configured for normal operation. The pin shall have an external pullup or pull-down to set the address.

Table 4.	Slave address
	ADDR (P0)	7-bit I2C slave address
	0	40h
	1	41h

Start condition

A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and does not respond to any transaction unless one is encountered.

Stop condition

A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A Stop condition terminates communication between the slave device and the bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I2C transaction. A Stop condition at the end of a write command stops the write operation to registers.

Acknowledge bit

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it does not acknowledge the receipt of the data.

2.2Data input

The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA signal must be stable during the rising edge of SCLK and the SDATA signal must change only when SCLK is driven low.

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I2C interface								STMPE812A
	Table 5.	Operating modes
	Mode		Byte	Programming sequence
							= 0, Register address to be read
				Start, Device address, R/W
								= 1, Data Read, Stop
				Restart, Device address, R/W
				If no Stop is issued, the Data Read can be continuously performed. If
	Read		≥1	the register address falls within the range that allows an address auto-
				increment, then the register address auto-increments internally after
				every byte of data being read. For register address that falls within a
				non-incremental address range, the address is kept static throughout
				the entire read operations. Refer to the memory map table for the
				address ranges that are auto and non-increment.
						= 0, Register address to be written, Data
				Start, Device address, R/W
				Write, Stop
				If no Stop is issued, the Data Write can be continuously performed. If
	Write		≥1	the register address falls within the range that allows address auto-
				increment, then the register address auto-increments internally after
				every byte of data being written in. For those register addresses that
				fall within a non-incremental address range, the address is kept static
				throughout the entire write operation. Refer to the memory map table
				for the address ranges that are auto and non-increment.

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STMPE812A	I2C interface

Figure 5. Read and write modes (random and sequential)

One byte

Start

Device

R/W=0

Ack

Reg

Ack

Device

R/W=1

Ack

Data

AckNo

Stop

Read

Address

Address

Address

Read

Read

Start

Address

R/W=0

Ack

Address

Ack

Restart

Address

R/W=1

Ack

Read

Ack

Read + 1

More than one byte

Device

Reg

Device

Data

Data

Write

Start

Address

R/W=0

Ack

Address

Ack

Data

Ack

Stop

One byte

Device

Reg

to be

written

More than one byte

Start

Address

R/W=0

Ack

Address

Ack

Write

Ack

Write + 1

Ack

Write + 2

Ack

Stop

Read

Device

Reg

Data to

Data to

Data to

Master

Slave

Ack

Data

Read + 2

No Ack	Stop

AM04175V1

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I2C interface	STMPE812A

2.3Read operation

A write is first performed to load the register address into the Address Counter but without sending a Stop condition. Then, the bus master sends a reStart condition and repeats the Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the content of the addressed byte. If no additional data is to be read, the bus master must not acknowledge the byte and terminates the transfer with a Stop condition.

If the bus master acknowledges the data byte, then it can continue to perform the data reading. To terminate the stream of data bytes, the bus master must not acknowledge the last output byte, and be followed by a Stop condition. If the address of the register written into the Address Counter falls within the range of addresses that has the auto-increment function, the data being read is coming from consecutive addresses, which the internal Address Counter automatically increments after each byte output. After the last memory address, the Address Counter 'rolls-over' and the device continues to output data from the memory address of 0x00. Similarly, for the register address that falls within a non-increment range of addresses, the output data byte comes from the same address (which is the address referred by the Address Counter).

Acknowledgement in read operation

For the above read command, the slave device waits, after each byte read, for an acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a low state, then the slave device terminates and switches back to its idle mode, waiting for the next command.

2.4Write operations

A write is first performed to load the register address into the Address Counter without sending a Stop condition. After the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (referred by the Address Counter). The slave device again acknowledges and the bus master terminates the transfer with a Stop condition.

If the bus master needs to write more data, it can continue the write operation without issuing the Stop condition. Whether the Address Counter autoincrements or not after each data byte write depends on the address of the register written into the Address Counter. After the bus master writes the last data byte and the slave device acknowledges the receipt of the last data, the bus master may terminate the write operation by sending a Stop condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the next data byte write.

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STMPE812A	Power supply

3 Power supply

The STMPE812A GPIO operates from a supply pin VCC. For better resolution and noise immunity, VCC above 2.8 V is recommended.

Power up reset

The STMPE812A is equipped with an internal POR circuit that holds the device in reset state, until the VCC supply input is valid. The internal POR is tied to the VCC supply pin.

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Charge pump	STMPE812A

4 Charge pump

The STMPE812A is integrated with an internal charge-pump. The charge pump is required for any ADC/TSC operations when VCC is less than 2.5 V.

Activating the charge pump when VCC > 2.5 V may result in permanent damage of the device.

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STMPE812A	Power modes

5 Power modes

The STMPE812A operates in a 2 states: active and hibernate.

Active:

–Whenever PEN-DOWN is detected, the device remains in active mode

–Whenever PWM is active, the device remains in active mode

–Whenever ADC is active, the device remains in ACTIVE MODE

Hibernate:

-PWM/ADC must be “off” (clock disable bit SET)

-Any GPIO input, with interrupt enabled, causes a transition to “active” state, if an input change is detected.

-Pen down even causes transition to “active” state if the touchscreen controller is enabled.

Table 6.	Power mode
	Power mode	Active	Hibernate
Current consumption		280 µA (max)(1)	1.0 µA (max.)
	GPIO hotkey	Yes	Yes
	Touchscreen	Yes	Yes
	Interface (I2C)	Yes	Yes

1. At Vcc=1.8V, TCS running at 100sets of X/Y per second, MAV disabled.

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Power modes	STMPE812A

Figure 6. Power modes state diagram

ACTIVE		POR
	Soft -Reset, Reset input
	I2C activity,
No activity	Touch, Hotkey	Reset Input
(about 33 μs)

AUTO -

HIBERNATE

STMPE812A is in active mode if PWM is running

AM04141V1

On power up reset, device goes to active state. However, as all the functional blocks are clocked off by default, no touch/hotkey activity is possible. If there are no I2C activities, device goes into auto-hibernate mode automatically.

The auto-hibernate feature of STMPE812A is always enabled. Whenever there is a period of inactivity, the device enters this mode to reduce power consumption. On detection a touch, correctly addressed I2C data, GPIO activity, the device wakes up immediately.

As the device is able to wake up very quickly, there is no loss of touch data.

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