ST STMPE610 User Manual
S-Touch®: advanced touchscreen controller
Features
■ 6 GPIOs
■ 1.8 - 3.3 V operating voltage
■ Integrated 4-wire touchscreen controller
■ Interrupt output pin
■ Wakeup feature on each I/O
■ SPI and I
■ Up to 2 devices sharing the same bus in I
mode (1 address line)
■ 6-input 12-bit ADC
■ 128-depth buffer touchscreen controller
■ Touchscreen movement detection algorithm
■ 25 kV air-gap ESD protection (system level)
■ 4 kV HBM ESD protection (device level)
2
C interface
2
C
STMPE610
with 6-bit port expander
QFN16
(3x3mm)
Description
The STMPE610 is a GPIO (general purpose
input/output) port expander able to interface a
main digital ASIC via the two-line bidirectional bus
2
(I
C). A separate GPIO expander is often used in
mobile multimedia platforms to solve the
problems of the limited amount of GPIOs typically
available on the digital engine.
Applications
■ Portable media players
■ Game consoles
■ Mobile and smartphones
■ GPS
Table 1. Device summary
Order code Package Packaging
STMPE610QTR QFN16 Tape and reel
The STMPE610 offers great flexibility, as each I/O
can be configured as input, output or specific
functions. The device has been designed with
very low quiescent current and includes a wakeup
feature for each I/O, to optimize the power
consumption of the device.
A 4-wire touchscreen controller is built into the
STMPE610. The touchscreen controller is
enhanced with a movement tracking algorithm to
avoid excessive data, 128 x 32 bit buffer and a
programmable active window feature.
September 2011 Doc ID 15432 Rev 4 1/56
www.st.com
56
Contents STMPE610
Contents
1 STMPE610 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 I2C and SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 SPI protocol definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 Register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.3 Termination of data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 SPI timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.1 SPI timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 STMPE610 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10 Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.1 Driver and switch control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.2 Touch detect delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/56 Doc ID 15432 Rev 4
STMPE610 Contents
11 Touchscreen controller programming sequence . . . . . . . . . . . . . . . . . 40
12 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.0.1 Power-up reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
14 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
15 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Doc ID 15432 Rev 4 3/56
STMPE610 functional overview STMPE610
1 STMPE610 functional overview
The STMPE610 consists of the following blocks:
2
● I
C and SPI interface
● Analog-to-digital converver (ADC)
● Touchscreen controller (TSC)
● Driver and switch control unit
● GPIO controller
Figure 1. STMPE610 functional block diagram
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INTERFACE
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2#OSCILLATOR
3WITCHES
ANDDRIVERS
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4/56 Doc ID 15432 Rev 4
!-6
STMPE610 Pin configuration and functions
2 Pin configuration and functions
Figure 2. STMPE610 pin configuration (top through view)
12 11 10 9
13
14
STMPE610
15
16
1 2 3 4
Table 2. Pin assignments
Pin Name Function
1 Y- Y-/GPIO-7
2 INT Interrupt output (VCC domain, open drain)
2
3 A0/Data Out I
4SCLKI
5SDATI
6V
7 Data in SPI Data In (V
8NC
CC
C address in Reset, Data out in SPI mode (VCC domain)
2
C/SPI clock (VCC domain)
2
C data/SPI CS (VCC domain)
1.8 −3.3 V supply voltage
domain)
CC
−
8
7
6
5
MODE
9Mode
10 GND Ground
11 IN2 IN2/GPIO-2
12 IN3 IN3/GPIO-3
13 X+ X+/GPIO-4
14 Vio Supply for touchscreen driver and GPIO
15 Y+ Y+/GPIO-5
16 X- X-/GPIO-6
In RESET state, MODE selects the type of serial interface
"0" - I2C
"1" - SPI
Doc ID 15432 Rev 4 5/56
Pin configuration and functions STMPE610
2.1 Pin functions
The STMPE610 is designed to provide maximum features and flexibility in a very small pincount package. Most of the pins are multi-functional. The following table shows how to
select the pin’s function.
Table 3. IN2, IN3 pin configuration
GPIO_AF = 1 GPIO_AF = 0
Pin / control
register
ADC control 1 bit
1 = don’t care
IN2 GPIO-2 ADC External reference +
IN3 GPIO-3 ADC External reference -
Table 4. X, Y pin configuration
GPIO_AF = 1 GPIO_AF = 0
Pin / control
register
TSC control 1 bit
0 = don’t care
X+ GPIO-4 ADC TSC X+
ADC control 1 bit
1 = 0
TSC control 1 bit
0 = 0
ADC control 1 bit
1 = 1
TSC control 1 bit
0 = 1
Y+ GPIO-5 ADC TSC Y+
X- GPIO-6 ADC TSC X-
Y- GPIO-7 ADC TSC Y-
6/56 Doc ID 15432 Rev 4
STMPE610 I2C and SPI interface
3 I2C and SPI interface
3.1 Interface selection
The STMPE610 interfaces with the host CPU via a I2C or SPI interface. The pin IN_1 allows
the selection of interface protocol at reset state.
Figure 3. STMPE610 interface
DIN
SPI I/F
module
DOUT
CLK
CS
SDAT
2
I C I/F
module
Table 5. Interface selection pins
Pin I2C function SPI function Reset state
3 Address 0 Data out CPHA for SPI
4 Clock Clock
5 SDATA CS CPOL_N for SPI
7
9MODEI
SCLK
A0
−
MUX
unit
−
Data in
2
C set to ‘0’ Set to ‘1’ for SPI
−
Doc ID 15432 Rev 4 7/56
I2C interface STMPE610
SC
SC
V
4 I2C interface
The addressing scheme of STMPE610 is designed to allow up to 2 devices to be connected
to the same I
Figure 4. STMPE610 I
LK
Table 6. I
2
C bus.
2
C interface
LK
2
C address
ADDR0 Address
STMPE610
AM00753
00x82
10x88
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
adress, is a read/write bit (R/W
match occurs on the slave device address, the corresponding device gives an acknowledge
on the SDA during the 9
th
). The bit is set to 1 for read and 0 for write operation. If a
bit time. If there is no match, it deselects itself from the bus by not
responding to the transaction.
Figure 5. I
SDA
SCL
2
C timing diagram
tHD:STAtBUF
SP
tHD:STA
tHIGH
tLOW
tF
tSU:DAT
tHD:DAT
SR
tSU:STOtSU:STA
P
AI00589
tR
8/56 Doc ID 15432 Rev 4
STMPE610 I2C interface
Table 7. I2C timing
Symbol Parameter Min Typ Max Unit
f
SCL
t
LOW
t
HIGH
t
F
t
HD:STA
t
SU:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
SCL clock frequency 0
Clock low period 1.3
Clock high period 600
SDA and SCL fall time
START condition hold time (after this
period the first clock is generated)
START condition setup time (only relevant
for a repeated start period)
Data setup time 100
Data hold time 0
STOP condition setup time 600
Time the bus must be free before a new
transmission can start
4.1 I2C features
The features that are supported by the I2C interface are listed below:
2
● I
C slave device
● Operates at 1.8 V
● Compliant to Philips I
● Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
2
C specification version 2.1
−
−−
−−
−−
600
600
−−
−−
−−
−−
−−
1.3
−−
400 kHz
µs
ns
300 ns
ns
ns
ns
µs
ns
µs
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
2
next I
C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
Doc ID 15432 Rev 4 9/56
I2C interface STMPE610
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
4.2 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Table 8. Operating modes
Mode Byte Programming sequence
Read ≥1
Write ≥1
Start, Device address, R/W
Restart, Device address, R/W
If no Stop is issued, the Data Read can be continuously performed. If
the register address falls within the range that allows an address autoincrement, then the register address auto-increments internally after
every byte of data being read.
Start, Device address, R/W
Write, Stop
If no Stop is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address autoincrement, then the register address auto-increments internally after
every byte of data being written in. For those register addresses that
fall within a non-incremental address range, the address will be kept
static throughout the entire write operation. Refer to the memory map
table for the address ranges that are auto and non-increment.
= 0, Register address to be read
= 1, Data Read, Stop
= 0, Register address to be written, Data
10/56 Doc ID 15432 Rev 4
STMPE610 I2C interface
Figure 6. Read and write modes (random and sequential)
One byte
Read
More than one byte
Read
One byte
Write
More than one byte
Read
Start
Start
Start
Start
Device
Address
Device
Address
Device
Address
Device
Address
Master
Slave
4.3 Read operation
R/W=0
R/W=0
R/W=0
R/W=0
Ack
Ack
Ack
Ack
Reg
Address
Reg
Address
Reg
Address
Reg
Address
Ack
Ack
Ack
Ack
Restart
Address
Restart
Data
to be
written
Data to
Write
Device
Address
Device
Ack
Data to
Ack
Write + 1
R/W=1
R/W=1
Stop
Data
Ack
Read
Data
Ack
Read
Ack
Write + 2
Data to
No Ack
Ack
Stop
Data
Read + 1
Ack
Stop
Ack
Data
Read + 2
Stop
No Ack
A write is first performed to load the register address into the Address Counter but without
sending a Stop condition. Then, the bus master sends a reStart condition and repeats the
Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the
content of the addressed byte. If no additional data is to be read, the bus master must not
acknowledge the byte and terminates the transfer with a Stop condition.
If the bus master acknowledges the data byte, then it can continue to perform the data
reading. To terminate the stream of data bytes, the bus master must not acknowledge the
last output byte, and be followed by a Stop condition. If the address of the register written
into the Address Counter falls within the range of addresses that has the auto-increment
function, the data being read will be coming from consecutive addresses, which the internal
Address Counter automatically increments after each byte output. After the last memory
address, the Address Counter 'rolls-over' and the device continues to output data from the
memory address of 0x00. Similarly, for the register address that falls within a non-increment
range of addresses, the output data byte comes from the same address (which is the
address referred by the Address Counter).
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an
acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a
low state, then the slave device terminates and switches back to its idle mode, waiting for
the next command.
Doc ID 15432 Rev 4 11/56
I2C interface STMPE610
4.4 Write operations
A write is first performed to load the register address into the Address Counter without
sending a Stop condition. After the bus master receives an acknowledgement from the slave
device, it may start to send a data byte to the register (referred by the Address Counter).
The slave device again acknowledges and the bus master terminates the transfer with a
Stop condition.
If the bus master needs to write more data, it can continue the write operation without
issuing the Stop condition. Whether the Address Counter autoincrements or not after each
data byte write depends on the address of the register written into the Address Counter.
After the bus master writes the last data byte and the slave device acknowledges the receipt
of the last data, the bus master may terminate the write operation by sending a Stop
condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the
next data byte write.
12/56 Doc ID 15432 Rev 4
STMPE610 SPI interface
5 SPI interface
The SPI interface in STMPE610 uses a 4-wire communication connection (DATA IN, DATA
OUT, CLK, CS). In the diagram, “Data in” is referred to as MOSI (master out slave in) and
“DATA out” is referred to as MISO (master in slave out).
5.1 SPI protocol definition
The SPI (serial peripheral interface) follows a byte sized transfer protocol. All transfers begin
with an assertion of CS_n signal (falling edge). The protocol for reading and writing is
different and the selection between a read and a write cycle is dependent on the first
captured bit on the slave device. A '1' denotes a read operation and a '0' denotes a write
operation. The SPI protocol defined in this section is shown in Figure 3.
The following are the main features supported by this SPI implementation.
● Support of 1 MHz maximum clock frequency.
● Support for autoincrement of address for both read and write.
● Full duplex support for read operation.
● Daisy chain configuration support for write operation.
● Robust implementation that can filter glitches of up to 50 ns on the CS_n and SCL pins.
● Support for all 4 modes of SPI as defined by the CPHA, CPOL bits on SPICON.
5.1.1 Register read
The following steps need to be followed for register read through SPI.
1. Assert CS_n by driving a '0' on this pin.
2. Drive a '1' on the first SCL launch clock on MOSI to select a read operation.
3. The next 7 bits on MOSI denote the 7-bit register address (MSB first).
4. The next address byte can now be transmitted on the MOSI. If the autoincrement bit is
set, the following address transmitted on the MOSI is ignored. Internally, the address is
incremented. If the autoincrement bit is not set, then the following byte denotes the
address of the register to be read next.
5. Read data is transmitted by the slave device on the MISO (MSB first), starting from the
launch clock following the last address bit on the MOSI.
6. Full duplex read operation is achieved by transmitting the next address on MOSI while
the data from the previous address is available on MISO.
7. To end the read operation, a dummy address of all 0's is sent on MOSI.
Doc ID 15432 Rev 4 13/56
SPI interface STMPE610
5.1.2 Register write
The following steps need to be followed for register write through SPI.
1. Assert CS_n by driving a '0' on this pin.
2. Drive a '0' on the first SCL launch clock on MOSI to select a write operation.
3. The next 7 bits on MOSI denote the 7-bit register address (MSB first).
4. The next byte on the MOSI denotes data to be written.
5. The following transmissions on MOSI are considered byte-sized data. The register
address to which the following data is written depends on whether the autoincrement
bit in the SPICON register is set. If this bit has been set previously, the register address
is incremented for data writes.
5.1.3 Termination of data transfer
A transfer can be terminated before the last launch edge by deasserting the CS_n signal. If
the last launch clock is detected, it is assumed that the data transfer is successful.
5.2 SPI timing modes
The SPI timing modes are defined by CPHA and CPOL,CPHA and CPOL are read from the
"SDAT" and "A0" pins during power-up reset. The following four modes are defined
according to this setting.
Table 9. SPI timing modes
CPOL_N (SDAT pin) CPOL CPHA (ADDR pin) Mode
1000
1011
0102
0113
The clocking diagrams of these modes are shown in ON reset. The device always operates
in mode 0. Once the bits are set in the SPICON register, the mode change takes effect on
the next transaction defined by the CS_n pin being deasserted and asserted.
5.2.1 SPI timing definition
Table 10. SPI timing specification
Symbol Description
CS_n falling to
t
CSS
t
CL
first capture
clock
Clock low
period
Timing
Min Typ Max
1
500
−−
−−
Unit
µs
ns
t
CH
14/56 Doc ID 15432 Rev 4
Clock high
period
500
−−
ns
STMPE610 SPI interface
Table 10. SPI timing specification (continued)
Timing
Symbol Description
Launch clock
t
LDI
t
LDO
t
DI
t
CCS
t
CSH
t
CSCL
t
CSZ
to MOSI data
valid
Launch clock
to MISO data
valid
Data on MOSI
valid
Last clock
edge to CS_n
high
CS_n high
period
CS_n high to
first clock edge
CS_n high to
tri-state on
MISO
Min Typ Max
−−
−−
1
1
2
300
1
−−
−−
−−
−−
−−
20 ns
330 µs
Unit
µs
µs
µs
ns
µs
Figure 7. SPI timing specification
Doc ID 15432 Rev 4 15/56
STMPE610 registers STMPE610
6 STMPE610 registers
This section lists and describes the registers of the STMPE610 device, starting with a
register map and then provides detailed descriptions of register types.
Table 11. Register summary map table
Address Register name Bit Type Reset value Function
0x00 CHIP_ID 16 R 0x0811 Device identification
Revision number
0x02 ID_VER 8 R 0x03
0x03 SYS_CTRL1 8 R/W 0x00 Reset control
0x04 SYS_CTRL2 8 R/W 0x0F Clock control
0x08 SPI_CFG 8 R/W 0x01 SPI interface configuration
0x09 INT_CTRL 8 R/W 0x00 Interrupt control register
0x0A INT_EN 8 R/W 0x00 Interrupt enable register
0x0B INT_STA 8 R 0x10 interrupt status register
0x0C GPIO_EN 8 R/W 0x00
0x0D GPIO_INT_STA 8 R 0x00
0x01 for engineering sample
0x03 for final silicon
GPIO interrupt enable
register
GPIO interrupt status
register
0x0E ADC_INT_EN 8 R/W 0x00
0x0F ADC_INT_STA 8 R 0x00 ADC interrupt status register
0x10 GPIO_SET_PIN 8 R/W 0x00 GPIO set pin register
0x11 GPIO_CLR_PIN 8 R/W 0x00 GPIO clear pin register
0x12 GPIO_MP_STA 8 R/W 0x00
0x13 GPIO_DIR 8 R/W 0x00 GPIO direction register
0x14 GPIO_ED 8 R/W 0x00 GPIO edge detect register
0x15 GPIO_RE 8 R/W 0x00 GPIO rising edge register
0x16 GPIO_FE 8 R/W 0x00 GPIO falling edge register
0x17 GPIO_AF 8 R/W 0x00 Alternate function register
0x20 ADC_CTRL1 8 R/W 0x9C ADC control
0x21 ADC_CTRL2 8 R/W 0x01 ADC control
0x22 ADC_CAPT 8 R/W 0xFF
0x30 ADC_DATA_CH0 16 R 0x0000 ADC channel 0
0x32 ADC_DATA_CH1 16 R 0x0000 ADC channel 1
ADC interrupt enable
register
GPIO monitor pin state
register
To initiate ADC data
acquisition
16/56 Doc ID 15432 Rev 4
STMPE610 STMPE610 registers
Table 11. Register summary map table (continued)
Address Register name Bit Type Reset value Function
0x38 ADC_DATA_CH4 16 R 0x0000 ADC channel 4
0x3A ADC_DATA_CH5 16 R 0x0000 ADC channel 5
0x3C ADC_DATA_CH6 16 R 0x0000 ADC channel 6
0x3E ADC_DATA_CH7 16 R 0x0000 ADC channel 7
0x40 TSC_CTRL 8 R/W 0x90
0x41 TSC_CFG 8 R/W 0x00
0x42 WDW_TR_X 16 R/W 0x0FFF Window setup for top right X
0x44 WDW_TR_Y 16 R/W 0x0FFF Window setup for top right Y
0x46 WDW_BL_X 16 R/W 0x0000
0x48 WDW_BL_Y 16 R/W 0x0000
0x4A FIFO_TH 8 R/W 0x00
0x4B FIFO_STA 8 R/W 0x20 Current status of FIFO
0x4C FIFO_SIZE 8 R 0x00 Current filled level of FIFO
0x4D TSC_DATA_X 16 R 0x0000
0x4F TSC_DATA_Y 16 R 0x0000
0x51 TSC_DATA_Z 8 R 0x0000
4-wire touchscreen
controller setup
Touchscreen controller
configuration
Window setup for bottom left
X
Window setup for bottom left
Y
FIFO level to generate
interrupt
Data port for touchscreen
controller data access
Data port for touchscreen
controller data access
Data port for touchscreen
controller data access
0x52 TSC_DATA_XYZ 32 R 0x00000000
0x56
0x57 TSC_DATA 8 R 0x00
0x58 TSC_I_DRIVE 8 R/W 0x00
0x59 TSC_SHIELD 8 R/W 0x00
TSC_FRACT_X
YZ
8 RW 0x00
Doc ID 15432 Rev 4 17/56
Data port for touchscreen
controller data access
Select the range and
accuracy of the pressure
measurement
Data port for touchscreen
controller data access
Touchscreen controller drive
I
Touchscreen controller
shield
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