ST STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB User Manual

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STM32F302xx STM32F303xx

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP48 (7 × 7 mm)

ARM™Cortex-M4 32b MCU+FPU, up to 256KB Flash+48KB SRAM

4 ADCs, 2 DAC ch., 7 comp., 4 PGA, timers, 2.0-3.6 V operation

Datasheet − preliminary data

Features

■ ARM 32-bit Cortex®-M4 CPU (72 MHz max),

single-cycle multiplication and HW division, DSP instruction with FPU (floating-point unit) and MPU (memory protection unit).

■ Operating conditions:

, V

–V

■ Memories

voltage range: 2.0 V to 3.6 V

DDA

– 128 to 256 Kbytes of Flash memory – Up to 40 Kbytes of SRAM on data bus with

HW parity check

– 8 Kbytes of SRAM on instruction bus with HW

parity check (CCM)

■ Clock management

– 4 to 32 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – Internal 8 MHz RC with x 16 PLL option – Internal 40 kHz oscillator

■ Calendar RTC

– Alarm, periodic wakeup from Stop/Standby

■ Reset and supply management

– Power-on/Power down reset (POR/PDR) – Programmable voltage detector (PVD)

■ Low power Sleep, Stop, and Standby modes

■ V

■ Debug mode: serial wire debug (SWD), JTAG

supply for RTC and backup registers

BAT

interfaces, Cortex-M4 ETM

■ DMA

– 12-channel DMA controller – Peripherals supported: timers, ADCs, SPIs,

Cs, USARTs and DACs

■ Up to 4 × ADC 0.20 µS (up to 39 channels) with

selectable resolution of 12/10/8/6 bits, 0 to 3.6 V conversion range, separate analog supply from 2 to 3.6 V

■ Temperature sensor

■ 7 fast rail-to-rail analog comparators

■ Up to 2 x 12-bit DAC channels

■ Up to 4 operational amplifiers that can be used in

PGA mode, all terminal accessible

■ Support for up to 24 capacitive sensing keys

■ Up to 87 fast I/O ports, all mappable on external

interrupt vectors, several 5 V-tolerant

■ Up to 13 timers

– 1 x 32-bit timer and 2 x 16-bit timers with up

to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

– Up to 2 x 16-bit 6-channel advanced-control

timers, with up to 6 PWM channels, deadtime generation and emergency stop

– 1 x 16-bit timer with 2 IC/OCs, 1 OCN/PWM,

deadtime generation and emergency stop

– 2 x 16-bit timers with IC/OC/OCN/PWM,

deadtime generation and emergency stop – 2 x watchdog timers (independent, window) – 1 x SysTick timer: 24-bit downcounter – Up to 2 x 16-bit basic timers to drive the DAC

■ Communication interfaces

– CAN interface (2.0B Active) – USB 2.0 full speed interface – 2 x I2C with 20 mA current sink to support

Fast mode plus – Up to 5 USART/UARTs (ISO 7816 interface,

LIN, IrDA, modem control) – Up to 3 SPIs, 2 with muxed full-duplex I2S to

achieve audio class accuracy via external

PLL

■ CRC calculation unit, 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F302xx

STM32F303xx

STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB, STM32F302VC

STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB, STM32F303VC

June 2012 Doc ID 023353 Rev 1 1/119

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

www.st.com

Contents STM32F302xx/STM32F303xx

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 ARM® Cortex™-M4 core with embedded Flash and SRAM . . . . . . . . . . 13

3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 14

3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.13 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17

3.14 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.15 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.16 Fast ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.16.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.16.2 Internal voltage reference (V

3.16.3 V

3.16.4 OPAMP reference voltage (VOPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 19

battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

BAT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

REFINT

3.17 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.18 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.19 Fast comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.20.1 Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.20.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . 22

3.20.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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STM32F302xx/STM32F303xx Contents

3.20.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.20.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.21 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.21.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.21.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 23

3.21.3 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . 24

3.21.4 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I

3.21.5 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.21.6 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

S) 24

3.22 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.23 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.23.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.23.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 55

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 55

6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Doc ID 023353 Rev 1 3/119

Contents STM32F302xx/STM32F303xx

6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.3.15 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.3.17 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.3.19 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.3.20 Operational amplifer charateristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.3.22 V

6.3.23 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

BAT

7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 115

8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F30x family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 7. Capacitive sensing GPIOs available on STM32F302xx/STM32F303xx

devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8. No. of capacitive sensing channels available on STM32F302xx/STM32F303xx devices . 26

Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 10. STM32F302xx/STM32F303xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 11. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 12. STM32F30x memory map and peripheral register boundary

addresses48

Table 13. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 14. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 15. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 16. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 17. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 18. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 19. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 20. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 21. Typical and maximum current consumption from V

at V

= 3.6 V58

Table 22. Typical and maximum current consumption from the V Table 23. Typical and maximum V Table 24. Typical and maximum V

consumption in Stop and Standby modes . . . . . . . . . . . . . . . 61

consumption in Stop and Standby modes . . . . . . . . . . . . . . 61

DDA

Table 25. Typical and maximum current consumption from V Table 26. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 27. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 64

Table 28. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 29. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 30. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 31. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 32. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 33. LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

LSE

Table 34. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 37. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 38. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 39. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 40. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 41. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 42. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 43. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 44. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

supply

supply . . . . . . . . . . . . . . . . . . 60

DDA

supply. . . . . . . . . . . . . . . . . . . . . . 62

BAT

Doc ID 023353 Rev 1 5/119

List of tables STM32F302xx/STM32F303xx

Table 45. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 46. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 47. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 48. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 49. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 50. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 51. WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 52. I

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 53. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 54. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 55. I

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 56. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 57. Minimum sampling time to be respected for fast and slow channels . . . . . . . . . . . . . . . . . 98

Table 58. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 59. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 60. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 61. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 62. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 63. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

BAT

Table 64. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 65. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 66. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 67. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . 111

Table 68. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 112

Table 69. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 113

Table 70. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 71. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 72. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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STM32F302xx/STM32F303xx List of figures

List of figures

Figure 1. STM32F302xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. STM32F303xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4. STM32F302xx/STM32F303xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 5. STM32F302xx/STM32F303xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 6. STM32F302xx/STM32F303xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 7. STM32F30x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 12. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 13. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 14. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 15. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 16. TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 17. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 84

Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . 84

Figure 20. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 22. I

Figure 23. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 24. SPI timing diagram - slave mode and CPHA = 1 Figure 25. SPI timing diagram - master mode Figure 26. I Figure 27. I

Figure 28. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 30. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 31. USB timings: definition of data signal rise and fall time (to be added) . . . . . . . . . . . . . . . 108

Figure 32. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 111

Figure 33. Recommended footprint

Figure 34. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 112

Figure 35. Recommended footprint Figure 36. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat

Figure 37. Recommended footprint Figure 38. LQFP100 P

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

(1)

S slave timing diagram (Philips protocol)

S master timing diagram (Philips protocol)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Doc ID 023353 Rev 1 7/119

Description STM32F302xx/STM32F303xx

1 Description

The STM32F302xx/STM32F303xx family is based on the high-performance ARM

Cortex™-M4 32-bit RISC core operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The family incorporates high-speed embedded memories (up to 256 Kbytes of Flash memory, up to 48 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.

The devices offer up to four fast 12-bit ADCs (5 Msps), up to seven comparators, up to four operational amplifiers, up to two DAC channels, a low-power RTC, up to five generalpurpose 16-bit timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. They also feature standard and advanced communication interfaces: up to two I

Cs, up to three SPIs (two SPIs are with multiplexed full-duplex I2Ss on STM32F303xx devices), three USARTs, up to two UARTs, CAN and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL.

The STM32F302xx/STM32F303xx family operates in the –40 to +85 °C and –40 to +105 °C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F302xx/STM32F303xx family offers devices in three packages ranging from 48 pins to 100 pins.

The set of included peripherals changes with the device chosen.

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STM32F302xx/STM32F303xx Description

Table 2. STM32F30x family device features and peripheral counts

Peripheral

STM32F

302Cx

STM32F

302Rx

STM32F

302Vx

STM32F

303Cx

STM32F

303Rx

STM32F

303Vx

Flash (Kbytes) 128 256 128 256 128 256 128 256 128 256 128 256

SRAM (Kbytes) on data bus

24 32 24 32 24 32 32 40 32 40 32 40

SRAM (Kbytes) on instruction bus (CCM:

core coupled memory)

Timers

Advanced control

General purpose

1 (16-bit) 2 (16-bit)

5 (16-bit) 1 (32 bit)

Basic 1 (16-bit) 2 (16-bit)

Comm. interfaces

SPI(I2S)

(1)

USART 3

UART 2

33(2)

CAN 1

USB 1

GPIOs 37 52 87 37 52 87

DMA channels 12

12-bit ADCs 2 4

12-bit DAC channels 1 2

Analog comparator 4 7

Operational amplifiers 2 4

CPU frequency 72 MHz

Operating voltage 2.0 to 3.6 V

Operating temperature

Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C

Junction temperature: - 40 to 125 °C

Packages LQFP48 LQFP64 LQFP100 LQFP48 LQFP64 LQFP100

1. In 128K and 256K Flash STM32F303xx devices the SPI interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.

Doc ID 023353 Rev 1 9/119

Device overview STM32F302xx/STM32F303xx

MS18959V5

Touch Sensing

Controller

AHB decoder

TIMER 16

2 Channels,1 Comp Channel, BRK as AF

TIMER 17

TIMER 1 / PWM

SPI1

MOSI, MISO, SCK,NSS as AF

USART1

RX, TX, CTS, RTS, SmartCard as AF

WinWATCHDOG

BusMatrix

MPU/FPU

Cortex M4 CPU

max

: 72 MHz

NVIC

GP DMA1

7 channels

CCM RAM

8KB

Flash

interface

OBL

FLASH 256 KB

64 bits

JTRST

JTDI

JTCK/SWCLK

JTMS/SWDAT

JTDO As AF

Power

Voltage reg.

3.3 V to 1.8V

DD18

Supply

Supervision

POR /PDR

PVD

POR

Reset Int.

DDIO

= 2 to 3.6 V

NRESET V

DDA

SSA

Ind. WDG32K

Standby

interface

PLL

DDIO

DDA

XTAL OSC

4 -32 MHz

Reset &

clock

control

AHBPCLK

APBP1CLK

APBP2CLK

AHB2 APB2

AHB2 APB1

CRC

APB1 F

max

= 36 MHz

APB2 f

max

= 72 MHz

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

OSC_IN OSC_OUT

SPI3

SCL, SDA, SMBAL as AF

USART2

SCL, SDA, SMBAL as AF

USART3

RC LS

TIMER6

TIMER 4

SPI2

12bit DAC1IF

DDA

TIMER2

(32-bit/PWM)

PA[15:0]

PB[15:0]

PC[15:0]

MOSI, MISO, SCK, NSS as AF

4 Channels, ETR as AF

USBDP, USBDM

DAC1_CH1 as AF

HCLK FCLK

USARTCLK

RC HS 8MHz

SRAM

40 KB

ETM

Trace/Trig

SWJTAG

TPIU

Ibus

TRADECLK

TRACED[0-3]

as AF

Dbus

System

GP DMA2

5 channels

12-bit ADC1

12-bit ADC2

Temp. sensor

REF+

REF-

TIMER 15

EXT.IT WKUP

XX AF

1 Channel, 1 Comp Channel, BRK as AF

4 Channels, 4 Comp channels, ETR, BRK as AF

GPIO PORT F

PD[15:0]

PE[15:0]

USB SRAM 512B

PF[7:0]

I2CCLK ADC SAR 1/2/3/4 CLK

DDIO

DDA

@VSW

XTAL 32kHz

OSC32_IN OSC32_OUT

BAT

= 1.65V to 3.6V

RTC

AWU

Backup

Reg

(64Byte)

Backup

interface

ANTI-TAMP

TIMER 3

UART4

UART5

I2C1

I2C2

bx CAN &

512B SRAM

USB 2.0 FS

OpAmp1

OpAmp2

DDA

INxx / OUTxx

INTERFACE

SYSCFG CTL

GP Comparator 6

GP Comparator 4

GP Comparator 2

CAN TX, CAN RX

4 Channels, ETR as AF

RX, TX, CTS, RTS, as AF

RX, TX as AF

DDA

Xx Ins, 4 OUTs as AF

XX Groups of

4 channels as AF

MOSI, MISO, SCK, NSS as AF

GP Comparator 1

2 Device overview

Figure 1. STM32F302xx block diagram

1. AF: alternate function on I/O pins.

10/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Device overview

MS18960V4

Touch Sensing

Controller

AHB decoder

TIMER 16

2 Channels,1 Comp Channel, BRK as AF

TIMER 17

TIMER 1 / PWM

TIMER 8 / PWM

4 Channels, 4 Comp channels, ETR, BRK as AF

SPI1

MOSI, MISO, SCK,NSS as AF

USART1

RX, TX, CTS, RTS, SmartCard as AF

WinWATCHDOG

BusMatrix

MPU/FPU

Cortex M4 CPU

max

: 72 MHz

NVIC

GP DMA1

7 channels

CCM RAM

8KB

Flash

interface

OBL

FLASH 256 KB

64 bits

JTRST

JTDI

JTCK/SWCLK

JTMS/SWDAT

JTDO As AF

Power

Voltage reg.

3.3 V to 1.8V

DD18

Supply

Supervision

POR /PDR

PVD

POR

Reset Int.

DDIO

= 2 to 3.6 V

NRESET V

DDA

SSA

Ind. WDG32K

Standby interface

PLL

DDIO

DDA

XTAL OSC

4 -32 MHz

Reset &

clock

control

AHBPCLK

APBP1CLK

APBP2CLK

AHB2 APB2

AHB2 APB1

CRC

APB1 F

max

= 36 MHz

APB2 f

max

= 72 MHz

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

OSC_IN OSC_OUT

SPI3/I2S

SCL, SDA, SMBAL as AF

USART2

SCL, SDA, SMBAL as AF

USART3

RC LS

TIMER6

TIMER 4

SPI2/I2S

12bit DAC1IF

DDA

TIMER2

(32-bit/PWM)

PA[15:0]

PB[15:0]

PC[15:0]

MOSI/SD, MISO/ext_SD, SCK/CK, NSS/WS, MCLK as AF

4 Channels, ETR as AF

USBDP, USBDM

DAC1_CH1 as AF

HCLK FCLK

USARTCLK

RC HS 8MHz

SRAM 40 KB

ETM

Trace/Trig

SWJTAG

TPIU

Ibus

TRADECLK

TRACED[0-3]

as AF

Dbus

System

GP DMA2

5 channels

12-bit ADC1

12-bit ADC2

Temp. sensor

REF+

REF-

TIMER 15

EXT.IT

WKUP

XX AF

1 Channel, 1 Comp Channel, BRK as AF

4 Channels, 4 Comp channels, ETR, BRK as AF

GPIO PORT F

PD[15:0]

PE[15:0]

TIMER7

USB SRAM 512B

PF[7:0]

12-bit ADC3

12-bit ADC4

I2CCLK ADC SAR 1/2/3/4 CLK

DDIO

DDA

@VSW

XTAL 32kHz

OSC32_IN OSC32_OUT

BAT

= 1.65V to 3.6V

RTC

AWU

Backup

Reg

(64Byte)

Backup

interface

ANTI-TAMP

TIMER 3

UART4

UART5

I2C1

I2C2

bx CAN &

512B SRAM

USB 2.0 FS

DAC1_CH2 as AF

OpAmp1

OpAmp2

OpAmp3

OpAmp4

DDA

INxx / OUTxx

INTERFACE

SYSCFG CTL

GP Comparator 7

GP Comparator...

GP Comparator 1

CAN TX, CAN RX

4 Channels, ETR as AF

MOSI/SD, MISO/ext_SD, SCK/CK, NSS/WS, MCLK as AF

RX, TX, CTS, RTS, as AF

RX, TX as AF

DDA

Xx Ins, 7 OUTs as AF

XX Groups of

4 channels as AF

Figure 2. STM32F303xx block diagram

1. AF: alternate function on I/O pins.

Doc ID 023353 Rev 1 11/119

Device overview STM32F302xx/STM32F303xx

Figure 3. Clock tree

FLITFCLK to Flash programming interface

HSI

to I2Cx (x = 1,2)

I2S_CKIN

SYSCLK

Ext. clock

I2SSRC

SYSCLK

to I2Sx (x = 2,3)

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

MCO

8 MHz

HSI RC

PLLSRC

/2,/3,...

/16

4-32 MHz HSE OSC

LSE OSC

32.768kHz

LSI RC 40kHz

Main clock output

HSI

PLLMUL

PLL

x2,x3,..

x16

/32

LSE

MCO

HSI

PLLCLK

HSE

CSS

RTCCLK

RTCSEL[1:0]

LSI

to IWWDG IWWDGCLK

PLLCLK

HSI LSI

HSE

SYSCLK

AHB

prescaler /1,2,..512

SYSCLK

to RTC

USB

prescaler

/1,1.5

HCLK

APB1

prescaler

/1,2,4,8,16

APB2

prescaler

/1,2,4,8,16

ADC

Prescaler

/1,2,4

Prescaler

/1,2,4,6,8,10,12,16,

32,64,128,256

PCLK1

If (APB1 prescaler =1) x1 else x2

SYSCLK

PCLK2

If (APB2 prescaler =1) x1 else x2

SYSCLK

ADC

PCLK1

HSI

LSE

PCLK2

HSI

LSE

USBCLK to USB interface

to AHB bus, core, memory and DMA

to cortex System timer FHCLK Cortex free running clock

to APB1 peripherals

to TIM 2,3,4,6,7

to USARTx (x = 2..5)

to APB2 peripherals

to TIM 15,16,17

to USART1

TIM1/8

to ADCxy (xy = 12, 34)

MS19989V2

12/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Functional overview

3 Functional overview

3.1 ARM® Cortex™-M4 core with embedded Flash and SRAM

The ARM Cortex-M4 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The ARM Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded ARM core, the STM32F302xx/STM32F303xx family is compatible with all ARM tools and software.

Figure 1 and Figure 2 show the general block diagrams of the

STM32F302xx/STM32F303xx family devices.

3.2 Memory protection unit

The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:

● Outstanding processing performance combined with fast interrupt handling

● Enhanced system debug with extensive breakpoint and trace capabilities

● Efficient processor core, system and memories

● Ultralow power consumption with integrated sleep modes

● Platform security robustness with optional integrated memory protection unit (MPU)

With its embedded ARM core, the STM32F302xx/STM32F303xx devices are compatible with all ARM development tools and software.

Doc ID 023353 Rev 1 13/119

Functional overview STM32F302xx/STM32F303xx

3.3 Nested vectored interrupt controller (NVIC)

The STM32F302xx/STM32F303xx devices embed a nested vectored interrupt controller (NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.4 Embedded Flash memory

All STM32F302xx/STM32F303xx devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).

3.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.6 Embedded SRAM

STM32F302xx/STM32F303xx devices feature up to 48 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from CCM, core coupled memory).

● 8 Kbytes of SRAM mapped on the instruction bus (Core Coupled Memory (CCM)),

used to execute critical routines or to access data (parity check on all of CCM RAM).

● 40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM)

14/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Functional overview

3.7 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed APB domain is 36 MHz.

3.8 Boot modes

At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:

● Boot from user Flash

● Boot from system memory

● Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 or USART2 or USB(DFU).

3.9 Power supply schemes

● V

provided externally through V

● V

SSA

operational amplifiers, reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA

level must be always greater or equal to the V first.

● V

BAT

registers (through power switch) when V

, V

2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is

, V

= 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators

DDA

is 2.4 V when the DACs and operational amplifiers are used). The V

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

3.10 Power supply supervisor

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage V

POR/PDR, without the need for an external reset circuit.

● The POR monitors only the V

that V

● The PDR monitors both the V

should arrive first and be greater than or equal to VDD.

DDA

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V equal to V

pins.

voltage

voltage level and must be provided

is not present.

is below a specified threshold,

DDA

supply voltage. During the startup phase it is required

and V

supply voltages, however the V

DDA

power

DDA

is higher than or

Doc ID 023353 Rev 1 15/119

Functional overview STM32F302xx/STM32F303xx

The device features an embedded programmable voltage detector (PVD) that monitors the V

power supply and compares it to the VPVD threshold. An interrupt can be generated

when V

drops below the V

threshold and/or when V

PVD

is higher than the V

PVD

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR), and power-down.

● The MR mode is used in the nominal regulation mode (Run)

● The LPR mode is used in Stop mode.

● The power-down mode is used in Standby mode: the regulator output is in high

impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

3.12 Low-power modes

The STM32F302xx/STM32F303xx supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USB wakeup on STM32F303xx devices, the RTC alarm, COMPx, I2Cx or U(S)ARTx.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

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STM32F302xx/STM32F303xx Functional overview

3.13 Real-time clock (RTC) and backup registers

The RTC and the 16 backup registers are supplied through a switch that takes power from either the V registers used to store 64 bytes of user application data when V

They are not reset by a system or power reset, or when the device wakes up from Standby mode.

The RTC is an independent BCD timer/counter. It supports the following features:

● Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format.

● Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

● Two programmable alarms with wake up from Stop and Standby mode capability.

● On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synbchronize it with a master clock.

● Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal

inaccuracy.

● Three anti-tamper detection pins with programmable filter. The MCU can be woken up

from Stop and Standby modes on tamper event detection.

● Timestamp feature which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.

● 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY

capability.

supply when present or the V

pin. The backup registers are sixteen 32-bit

BAT

power is not present.

The RTC clock sources can be:

● A 32.768 kHz external crystal

● A resonator or oscillator

● The internal low-power RC oscillator (typical frequency of 40 kHz)

● The high-speed external clock divided by 32.

3.14 DMA (direct memory access)

The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose timers,

DAC and ADC.

3.15 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

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Functional overview STM32F302xx/STM32F303xx

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.16 Fast ADC (analog-to-digital converter)

Up to four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F302xx/STM32F303xx family devices. The ADCs have up to 39 external channels. Some of the external channels are shared between ADC1&2 and between ADC3&4, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADCs have also internal channels: Temperature sensor connected to ADC1 channel 16, V ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to ADC2 channel 17, VOPAMP3 connected to ADC3 channel 17, VOPAMP4 connected to ADC4 channel 17).

Additional logic functions embedded in the ADC interface allow:

● Simultaneous sample and hold

● Interleaved sample and hold

● Single-shunt phase current reading techniques.

connected to ADC1 channel 17, Voltage reference V

BAT/2

connected to the 4

REFINT

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 on all devices and TIM8 on STM32F303xx devices) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

3.16.1 Temperature sensor

The temperature sensor (TS) generates a voltage V temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

that varies linearly with

SENSE

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STM32F302xx/STM32F303xx Functional overview

Table 3. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at

TS_CAL1

TS_CAL2

temperature of 30 °C, V

= 3.3 V

DDA

TS ADC raw data acquired at temperature of 110 °C V

= 3.3 V

DDA

0x1FFF F7B8 - 0x1FFF F7B9

0x1FFF F7C2 - 0x1FFF F7C3

3.16.2 Internal voltage reference (V

The internal voltage reference (V ADC and Comparators. V The precise voltage of V

REFINT

is internally connected to the ADC_IN18 input channel.

REFINT

is individually measured for each part by ST during

REFINT

)

) provides a stable (bandgap) voltage output for the

production test and stored in the system memory area. It is accessible in read-only mode.

Table 4. Temperature sensor calibration values

Calibration value name Description Memory address

Raw data acquired at

3.16.3 V

VREFINT_CAL

battery voltage monitoring

BAT

temperature of 30 °C V

= 3.3 V

DDA

This embedded hardware feature allows the application to measure the V using the internal ADC channel ADC_IN17. As the V and thus outside the ADC input range, the V

BAT

divider by 2. As a consequence, the converted digital value is half the V

3.16.4 OPAMP reference voltage (VOPAMP)

Every OPAMP reference voltage can be measured using a corresponding ADC internal channel: VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to ADC2 channel 17, VOPAMP3 connected to ADC3 channel 17, VOPAMP4 connected to ADC4 channel 17.

0x1FFF F7BA - 0x1FFF F7BB

battery voltage

voltage may be higher than V

BAT

pin is internally connected to a bridge

voltage.

BAT

DDA

3.17 DAC (digital-to-analog converter)

Up to two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

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Functional overview STM32F302xx/STM32F303xx

This digital interface supports the following features:

● Up to two DAC output channels on STM32F303xx devices

● 8-bit or 12-bit monotonic output

● Left or right data alignment in 12-bit mode

● Synchronized update capability on STM32F303xx devices

● Noise-wave generation

● Triangular-wave generation

● Dual DAC channel independent or simultaneous conversions on STM32F303xx

devices

● DMA capability (for each channel on STM32F303xx devices)

● External triggers for conversion

3.18 Operational amplifier

The STM32F302xx/STM32F303xx embeds up to four operational amplifiers with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When an operational amplifier is selected, an external ADC channel is used to enable output measurement.

The operational amplifier features:

● 8MHz GBP

● 0.5 mA output capability

● Rail-to-rail input/output

● In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.

3.19 Fast comparators

The STM32F302xx/STM32F303xx devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity.

The reference voltage can be one of the following:

● External I/O

● DAC output pin

● Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 20: Embedded

internal reference voltage on page 57 for the value and precision of the internal

reference voltage.

All comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator

3.20 Timers and watchdogs

The STM32F302xx/STM32F303xx includes up to two advanced control timers, up to 6 general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.

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STM32F302xx/STM32F303xx Functional overview

Table 5. Timer feature comparison

Timer type Timer

Counter

resolution

TIM1,

TIM8

Advanced

(on

16-bit

STM32F303xx

devices only)

General-

purpose

General-

purpose

General-

purpose

General-

purpose

TIM2 32-bit

TIM3, TIM4 16-bit

TIM15 16-bit Up

TIM16, TIM17 16-bit Up

TIM6,

TIM7

Basic

(on

16-bit Up

STM32F303xx

devices only)

Counter

type

Up, Down,

Up/Down

Up, Down,

Up/Down

Up, Down,

Up/Down

Prescaler

factor

Any integer

between 1

and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

DMA

request

generation

Capture/ compare

Channels

Complementary

Ye s 4 Ye s

Ye s 4 N o

Ye s 2 1

Ye s 1 1

Ye s 0 N o

outputs

3.20.1 Advanced timers (TIM1, TIM8)

The advanced-control timers (TIM1 on all devices and TIM8 on STM32F303xx devices) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for:

● Input capture

● Output compare

● PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

● One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIM timers (described in

Section 3.20.2 using the same architecture, so the advanced-control timers can work

together with the TIM timers via the Timer Link feature for synchronization or event chaining.

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Functional overview STM32F302xx/STM32F303xx

3.20.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)

There are up to six synchronizable general-purpose timers embedded in the STM32F302xx/STM32F303xx (see Tab l e 5 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

● TIM2, 3, and TIM4

These are full-featured general-purpose timers:

– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler

– TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.

These timers all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

● TIM15, 16 and 17

These three timers general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.20.3 Basic timers (TIM6, TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as a generic16-bit time base.

3.20.4 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.20.5 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

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STM32F302xx/STM32F303xx Functional overview

3.20.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

3.21 Communication interfaces

3.21.1 I2C bus

Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.

Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.

Table 6. Comparison of I2C analog and digital filters

Analog filter Digital filter

Pulse width of suppressed spikes

Benefits Available in Stop mode

Drawbacks

≥ 50 ns

Variations depending on temperature, voltage, process

Programmable length from 1 to 15 I2C peripheral clocks

1. Extra filtering capability vs. standard requirements.

2. Stable length

Disabled when Wakeup from Stop mode is enabled

In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller.

3.21.2 Universal synchronous/asynchronous receiver transmitter (USART)

The STM32F302xx/STM32F303xx devices have three embedded universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).

The USART interfaces are able to communicate at speeds of up to 9Mbits/s.

They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller.

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Functional overview STM32F302xx/STM32F303xx

3.21.3 Universal asynchronous receiver transmitter (UART)

The STM32F302xx/STM32F303xx devices have 2 embedded universal asynchronous receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC, multiprocessor communication mode and single-wire half-duplex communication mode. The UART interfaces can be served by the DMA controller.

3.21.4 Serial peripheral interface (SPI)/Inter-integrated sound interfaces

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio standards can operate as master or slave at simplex and full duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 96 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency.

3.21.5 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.

3.21.6 Universal serial bus (USB)

The STM32F302xx/STM32F303xx medium and high density devices embed an USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a fullspeed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

3.22 Touch sensing controller (TSC)

The device has an embedded independent hardware controller (TSC) for controlling touch sensing acquisitions on the I/Os.

Up to 18 touch sensing electrodes can be controlled by the TSC. The touch sensing I/Os are organized in 8 acquisition groups, with up to 4 I/Os in each group.

The STM32F302xx/STM32F303xx devices provide a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect the presence of a finger near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this

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STM32F302xx/STM32F303xx Functional overview

acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. The STM32F302xx/STM32F303xx devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

Table 7. Capacitive sensing GPIOs available on STM32F302xx/STM32F303xx

devices

Pin name

PA0 G1_IO1 PB3 G5_IO1

PA1 G1_IO2 PB4 G5_IO2

PA2 G1_IO3 PB6 G5_IO3

PA3 G1_IO4 PB7 G5_IO4

PA4 G2_IO1 PB11 G6_IO1

PA5 G2_IO2 PB12 G6_IO2

PA6 G2_IO3 PB13 G6_IO3

PA7 G2_IO4 PB14 G6_IO4

PC5 G3_IO1 PE2 G7_IO1

PB0 G3_IO2 PE3 G7_IO2

PB1 G3_IO3 PE4 G7_IO3

PB2 G3_IO4 PE5 G7_IO4

PA9 G4_IO1 PD12 G8_IO1

PA10 G4_IO2 PD13 G8_IO2

PA13 G4_IO3 PD14 G8_IO3

PA14 G4_IO4 PD15 G8_IO4

Capacitive sensing

group name

Pin name

Capacitive sensing

group name

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Functional overview STM32F302xx/STM32F303xx

Table 8. No. of capacitive sensing channels available on

STM32F302xx/STM32F303xx devices

Number of capacitive sensing channels

Analog I/O group

STM32F30xVx STM32F30xRx STM32F30xCx

G1 3 3 3

G2 3 3 3

G3 3 3 2

G4 3 3 3

G5 3 3 3

G6 3 3 3

G7 3 0 0

G8 3 0 0

Number of capacitive

sensing channels

24 18 17

3.23 Development support

3.23.1 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.23.2 Embedded trace macrocell™

The ARM embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F302xx/STM32F303xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using a highspeed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

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STM32F302xx/STM32F303xx Pinouts and pin description

MS19819V2

VDD_1

VSS_1

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

48 47 46 45 44 43 42 41 40 39 38 37

VBAT

136

VDD_3

PC13

235

VSS_3

PC14 / OSC32_IN

334

PA13

PC15 OSC32_OUT

433

PA12

PF0 OSC_IN

532

PA11

PF1 OSC_OUT

48-pins

PA10

NRST

730

PA9

VSSA

829

PA8

VDDA

928

PB15

10 27

PB14

PA1

11 26

PB13

PA2

12 25

PB12

13 14 15 16 17 18 19 20 21 22 23 24

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

VSS_2

VDD_2

4 Pinouts and pin description

Figure 4. STM32F302xx/STM32F303xx LQFP48 pinout

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Pinouts and pin description STM32F302xx/STM32F303xx

ai18484V2

VDD_1

VSS_1

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA15

PA14

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VBAT

148

VDD_3

PC13

247

VSS_3

PC14 / OSC32_IN

346

PA13

PC15 / OSC32_OUT

445

PA12

PF0 / OSC_IN

544

PA11

PF1 / OSC_OUT

643

PA10

NRST

742

PA9

PC0

64-pins

PA8

PC1

940

PC9

PC2

10 39

PC8

PC3

11 38

PC7

VSSA

12 37

PC6

VDDA

13 36

PB15

PA0

14 35

PB14

PA1

15 34

PB13

PA2

16 33

PB12

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PA3

PF4

VDD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS_2

VDD_2

MS30357V1

VDD_1

VSS_1

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA15

PA14

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VBAT

148

VDD_3

PC13

247

VSS_3

PC14 / OSC32_IN

346

PA13

PC15 / OSC32_OUT

445

PA12

PF0 / OSC_IN

544

PA11

PF1 / OSC_OUT

643

PA10

NRST

742

PA9

PC0

64-pins

PA8

PC1

940

PC9

PC2

10 39

PC8

PC3

11 38

PC7

VSSA

12 37

PC6

VDDA

13 36

PB15

PA0

14 35

PB14

PA1

15 34

PB13

PA2

16 33

PB12

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PA3

PF4

VDD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

NPOR

PB10

PB11

VSS_2

VDD_2

Figure 5. STM32F302xx/STM32F303xx LQFP64 pinout

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STM32F302xx/STM32F303xx Pinouts and pin description

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Figure 6. STM32F302xx/STM32F303xx LQFP100 pinout

Doc ID 023353 Rev 1 29/119

Pinouts and pin description STM32F302xx/STM32F303xx

Table 9. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name

Pin type

I/O structure

functions

Notes

Alternate functions

Additional

functions

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

FTf 5 V tolerant I/O, FM+ capable

TTa 3.3 V tolerant I/O directly connected to ADC

TC Standard 3.3V I/O

B Dedicated BOOT0 pin

RST Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

30/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Pinouts and pin description

Table 10. STM32F302xx/STM32F303xx pin definitions

Pin number

Pin name

LQF

P100

LQF

P64

LQF

P48

(function

after reset)

Pin type

1 PE2 I/O FT

2 PE3 I/O FT

3 PE4 I/O FT

4 PE5 I/O FT

PE6_

TAMPER3_

I/O FT TRACED3 WKUP3

WKUP3

611 V

722

BAT

PC13_

TAMPER1_

S Backup power supply

I/O TC TIM1_CH1N

PC14 -

833

OSC32_IN

I/O TC OSC32_IN

(PC14)

I/O structure

Notes

(1)

Pin functions

Alternate functions Additional functions

TRACECK, TIM3_CH1,

TSC_G7_IO1

TRACED0, TIM3_CH2,

TSC_G7_IO2

TRACED1,

TIM3_CH3,TSC_G7_IO3

TRACED2,

TIM3_CH4,TSC_G7_IO4

WKUP2,

RTC_TAMPER1,

RTC_TS, RTC_OUT

PC15-

944

OSC32_OUT

I/O TC OSC32_OUT

(PC15)

10 PF9 I/O FT TIM15_CH1, SPI2_SCK

11 PF10 I/O FT TIM15_CH2, SPI2_SCK

12 5 5

PF0-OSC_IN

(PF0)

I/O FTf TIM1_CH3N, I2C2_SDA OSC_IN

PF1-

13 6 6

OSC_OUT

I/O FTf I2C2_SCL OSC_OUT

(PF1)

14 7 7 NRST I/O RST Device reset input / internal reset output (active low)

15 8 PC0 I/O TTa

16 9 PC1 I/O TTa

17 10 PC2 I/O TTa COMP7_OUT

(2)

ADC12_IN6,

COMP7_INM

ADC12_IN7,

COMP7_INP

ADC12_IN8

(2)

18 11 PC3 I/O TTa TIM1_BKIN2 ADC12_IN9

19 PF2 I/O TTa ADC12_IN10

20 12 8 V

SSA

21 V

, V

REF+

REF-

Doc ID 023353 Rev 1 31/119

Pinouts and pin description STM32F302xx/STM32F303xx

Table 10. STM32F302xx/STM32F303xx pin definitions (continued)

Pin number

Pin name

LQF

P100

P64

P48

22 V

13 9

(function

after reset)

DDA

REF+

Pin type

23 14 10 PA0 I/O TTa

24 15 11 PA1 I/O TTa

25 16 12 PA2 I/O TTa

26 17 13 PA3 I/O TTa

I/O structure

Notes

Pin functions

Alternate functions Additional functions

USART2_CTS,

TIM2_CH1_ETR,

TIM8_BKIN

TIM8_ETR

(2)

TSC_G1_IO1,

ADC1_IN1,

COMP1_INM,

RTC_ TAMP2,WKUP1,

COMP7_INP

COMP1_OUT

USART2_RTS,

TIM2_CH2,

TSC_G1_IO2,

TIM15_CH1N

(2)

USART2_TX,

TIM2_CH3, TIM15_CH1,

TSC_G1_IO3, COMP2_OUT

ADC1_IN2,

COMP1_INP,

OPAMP1_VINP,

OPAMP3_VINP

ADC1_IN3,

COMP2_INM,

AOP1_OUT

ADC1_IN4,

USART2_RX,

TIM2_CH4, TIM15_CH2,

TSC_G1_IO4,

OPAMP1_VINP,

COMP2_INP,

OPAMP1_VINM

(2)

27 18 PF4 I/O TTa COMP1_OUT ADC1_IN5

28 19 V

DD_4

29 20 14 PA4 I/O TTa

SPI1_NSS,SPI3_NSS,

I2S3_WS

USART2_CK,

TSC_G2_IO1,

(2)

ADC2_IN1,

DAC1_OUT1

TIM3_CH2

30 21 15 PA5 I/O TTa

31 22 16 PA6 I/O TTa

SPI1_SCK,

TIM2_CH1_ETR,

TSC_G2_IO2

SPI1_MISO, TIM3_CH1,

TIM8_BKIN

(2)

TIM1_BKIN, TIM16_CH1,

COMP1_OUT,

ADC2_IN2, DAC1_OUT2 OPAMP2_VINM

ADC2_IN3,

AOP2_OUT

TSC_G2_IO3

SPI1_MOSI,TIM3_CH2,

32 23 17 PA7 I/O TTa

TIM17_CH1,

TIM1_CH1N,

TSC_G2,_IO4,

COMP2_OUT,

ADC2_IN4,COMP2_INP

OPAMP2_VINP,

OPAMP1_VINP

TIM18_CH1

33 24 PC4 I/O TTa USART1_TX ADC2_IN5

(2)

32/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Pinouts and pin description

Table 10. STM32F302xx/STM32F303xx pin definitions (continued)

Pin number

Pin functions

Pin name

LQF

P100

LQF

P64

LQF

P48

(function

after reset)

Pin type

Notes

Alternate functions Additional functions

I/O structure

ADC2_IN11,

OPAMP2_VINM,

OPAMP1_VINM

ADC3_IN12

COMP4_INP,

OPAMP3_VINP

OPAMP2_VINP

34 25 PC5 I/O TTa

35 26 18 PB0 I/O TTa

USART1_RX, TSC_G3_IO1

TIM3_CH3, TIM1_CH2N,

TIM8_CH2N

(2)

TSC_G3_IO2

TIM3_CH4,

36 27 19 PB1 I/O TTa

TIM1_CH3N,

TIM8_CH3N

COMP4_OUT,

(2)

ADC3_IN1

AOP3_OUT

TSC_G3_IO3

ADC2_IN12,

37 28 20 PB2 I/O TTa TSC_G3_IO4

COMP4_INM,OPAMP3_

VINM

38 PE7 I/O TTa TIM1_ETR

39 PE8 I/O TTa TIM1_CH1N

ADC3_IN13

COMP4_INP

COMP4_INM, ADC34_IN6

40 PE9 I/O TTa TIM1_CH1 ADC3_IN2

41 PE10 I/O TTa TIM1_CH2N ADC3_IN14

42 PE11 I/O TTa TIM1_CH2 ADC3_IN15

43 PE12 I/O TTa TIM1_CH3N ADC3_IN16

44 PE13 I/O TTa TIM1_CH3 ADC3_IN3

45 PE14 I/O TTa TIM1_CH4_BKIN2 ADC4_IN1

46 PE15 I/O TTa USART3_RX,TIM1_BKIN ADC4_IN2

COMP5_INM OPAMP4_VINM OPAMP3_VINM

COMP6_INP,

OPAMP4_VINP

ADC4_IN3

COMP3_INM,

AOP4_OUT,

47 29 21 PB10 I/O TTa

48 30 22 PB11 I/O TTa

49 31 23 V

50 32 24 V

S Digital ground

S Digital power supply

51 33 25 PB12 I/O TTa

USART3_TX, TIM2_CH3,

SYNC

USART3_RX,

TIM2_CH4, TSC_G6_IO1

SPI2_NSS,I2S2_WS

(2)

I2C2_SMBAL,

USART3_CK,

TIM1_BKIN,

TSC_G6_IO2

(2)

Doc ID 023353 Rev 1 33/119

Pinouts and pin description STM32F302xx/STM32F303xx

Table 10. STM32F302xx/STM32F303xx pin definitions (continued)

Pin number

Pin functions

Pin name

LQF

P100

LQF

P64

LQF

P48

(function

after reset)

Pin type

Notes

Alternate functions Additional functions

I/O structure

(2)

52 34 26 PB13 I/O TTa

53 35 27 PB14 I/O TTa

SPI2_SCK, I2S2_CK

USART3_CTS,

TIM1_CH1N,

TSC_G6_IO3

SPI2_MISO,

I2S2ext_SD

(2)

USART3_RTS,

TIM1_CH2N,

TIM15_CH1,

ADC3_IN5

COMP5_INP

OPAMP4_VINP

OPAMP3_VINP

COMP3_INP

ADC4_IN4

OPAMP2_VINP

TSC_G6_IO4

SPI2_MOSI,

(2)

54 36 28 PB15 I/O TTa

I2S2_SD

, TIM1_CH3N,

TIM15_CH1N,

TIM15_CH2

55 PD8 I/O TTa USART3_TX

ADC4_IN5

RTC_REFIN,

COMP6_INM

ADC4_IN12

OPAMP4_VINM

56 PD9 I/O TTa USART3_RX ADC4_IN13

57 PD10 I/O TTa USART3_CK

ADC34_IN7

COMP6_INM

ADC34_IN8

58 PD11 I/O TTa USART3_CTS

COMP6_INP,

OPAMP4_VINP

59 PD12 I/O TTa

60 PD13 I/O TTa

USART3_RTS

TIM4_CH1,

TSC_G8_IO1

TIM4_CH2,

TSC_G8_IO2

ADC34_IN9 COMP5_INP

ADC34_IN10

COMP5_INM

(2)

61 PD14 I/O TTa

62 PD15 I/O TTa

63 37 PC6 I/O FT

SPI2_NSS,TIM4_CH4,

TM8_CH1,TIM3_CH1,

64 38 PC7 I/O FT

65 39 PC8 I/O FT

34/119 Doc ID 023353 Rev 1

TIM4_CH3,

TSC_G8_IO3

TSC_G8_IO4

I2S2_MCK

(2)

COMP6_OUT

I2S3_MCK TIM8_CH2

(2)

TIM3_CH2,

COMP5_OUT

TIM8_CH3

(2)

TIM3_CH3,

COMP3_OUT

(2)

COMP3_INP,

ADC34_IN11

(2)

OPAMP2_VINP

COMP3_INM

, ,

STM32F302xx/STM32F303xx Pinouts and pin description

Table 10. STM32F302xx/STM32F303xx pin definitions (continued)

Pin number

Pin name

LQF

P100

LQF

P64

LQF

P48

(function

after reset)

Pin type

66 40 PC9 I/O FT

67 41 29 PA8 I/O FT

68 42 30 PA9 I/O FTf

69 43 31 PA10 I/O FTf

70 44 32 PA11 I/O FT

71 45 33 PA12 I/O FT

72 46 34 PA13 I/O FT

73 PF6 I/O FTf

74 47 35 V

75 48 36 V

I/O structure

Notes

Pin functions

Alternate functions Additional functions

(2)

TIM8_CH4_BKIN2

TIM3_CH4,

I2S_CKIN

I2C2_SMBAL,

I2S2_MCK USART1_CK,

TIM1_CH1, TIM4_ETR,

MCO

(2)

I2S3_MCK

, COMP3_OUT

I2C2_SCL,

(2)

USART1_TX,

TIM1_CH2, TIM2_CH3,

TIM15_BKIN,

TSC_G4_IO1,

COMP5_OUT

(2)

I2C2_SDA,

USART1_RX,

TIM1_CH3, TIM2_CH4,

TIM8_BKIN

(2)

TIM17_BKIN, TSC_G4_IO2, COMP6_OUT

USART1_CTS,

USBDM,

CAN_RX,

TIM1_CH1N,

TIM1_CH4_BKIN2,

TIM4_CH1,

COMP1_OUT

USART1_RTS,USBDP,

CAN_TX,

TIM1_CH2N,

TIM1_ETR,TIM4_CH2,

TIM16_CH1,

COMP2_OUT

USART3_CTS,

TIM4_CH3, TIM16_CH1N, TSC_G4_IO3,

IR_OUT, JTMS-SWDIO

I2C2_SCL,

USART3_RTS,

TIM4_CH4

Doc ID 023353 Rev 1 35/119

Pinouts and pin description STM32F302xx/STM32F303xx

Table 10. STM32F302xx/STM32F303xx pin definitions (continued)

Pin number

Pin name

LQF

P100

LQF

P64

LQF

P48

(function

after reset)

Pin type

76 49 37 PA14 I/O FTf

77 50 38 PA15 I/O FT

78 51 PC10 I/O FT

79 52 PC11 I/O FT

80 53 PC12 I/O FT

I/O structure

Notes

Pin functions

Alternate functions Additional functions

I2C1_SDA,

USART2_TX,

TIM8_CH2, TIM1_BKIN,

TSC_G4_IO4, JTCK-SWCLK

I2C1_SCL, SPI3_NSS,

SPI1_NSS, I2S3_WS,

USART2_RX,

TIM1_BKIN,

TIM2_CH1_ETR,

TIM8_CH1

SPI3_SCK, I2S3_CK,

USART3_TX,

UART4_TX,

TIM8_CH1N

SPI3_MISO,

I2S3ext_SD

(2)

USART3_RX,

UART4_RX,

TIM8_CH2N

SPI3_MOSI, I2S3_SD

(2)

USART3_CK,

UART5_TX,

TIM8_CH3N

(2)

81 PD0 I/O FT CAN_RX

82 PD1 I/O FT

83 54 PD2 I/O FT

84 PD3 I/O FT

85 PD4 I/O FT

CAN_TX,

TIM8_CH4_BKIN2

UART5_RX,TIM3_ETR,

TIM8_BKIN

USART2_CTS,

TIM2_CH1_ETR

USART2_RTS,

TIM2_CH2

86 PD5 I/O FT USART2_TX

87 PD6 I/O FT

88 PD7 I/O FT

USART2_RX,

TIM2_CH4

USART2_CK,

TIM2_CH3

36/119 Doc ID 023353 Rev 1

(2)

STM32F302xx/STM32F303xx Pinouts and pin description

Table 10. STM32F302xx/STM32F303xx pin definitions (continued)

Pin number

Pin name

LQF

P100

LQF

P64

LQF

P48

(function

after reset)

Pin type

89 55 39 PB3 I/O FT

90 56 40 PB4 I/O FT

91 57 41 PB5 I/O FT

92 58 42 PB6 I/O FTf

I/O structure

Notes

Pin functions

Alternate functions Additional functions

SPI3_SCK,SPI1_SCK,

I2S3_CK

(2)

USART2_TX,

TIM2_CH2, TIM3_ETR,

TIM4_ETR,

(2)

TIM8_CH1N

, G5_IO1,

JTDO

SPI3_MISO, SPI1_MISO,

I2S3ext_SD

(2)

USART2_RX,

TIM3_CH1,

TIM16_CH1,

TIM17_BKIN,

TIM8_CH2N

(2)

TSC_G5_IO2, NJTRST

SPI3_MOSI,

SPI1_MOSI, I2S3_SD,

I2C1_SMBAL,

USART2_CK,

TIM16_BKIN, TIM3_CH2,

TIM8_CH3N

(2)

TIM17_CH1

I2C1_SCL,

USART1_TX,

TIM16_CH1N,

TIM4_CH1,

TIM8_CH1

TIM8_ETR_BKIN2

(2)

TSC_G5_IO3

93 59 43 PB7 I/O FTf

94 60 44 BOOT0 I B

95 61 45 PB8 I/O FTf

Doc ID 023353 Rev 1 37/119

I2C1_SDA,

USART1_RX,TIM3_CH4,

TIM4_CH2, TIM17_CH1N,

TIM8_BKIN,

TSC_G5_IO4

I2C1_SCL, CAN_RX,

TIM16_CH1, TIM4_CH3,

TIM8_CH2

(2)

TIM1_BKIN, SYNC,

COMP1_OUT

Pinouts and pin description STM32F302xx/STM32F303xx

Table 10. STM32F302xx/STM32F303xx pin definitions (continued)

Pin number

Pin name

LQF

P100

LQF

P64

LQF

P48

(function

after reset)

Pin type

96 62 46 PB9 I/O FTf

97 PE0 I/O FT

98 PE1 I/O FT

99 63 47 V

100 64 48 V

1. Function availability depends on the chosen device.

2. On STM32F303xx devices only.

I/O structure

Notes

Pin functions

Alternate functions Additional functions

I2C1_SDA,CAN_TX,

TIM17_CH1,TIM4_CH4,

TIM8_CH3

(2)

IR_OUT,

COMP2_OUT

USART1_TX,

TIM4_ETR,TIM16_CH1

USART1_RX,

TIM17_CH1

38/119 Doc ID 023353 Rev 1

Table 11. Alternate functions

Port

n°

Name

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

STM32F302xx/STM32F303xx Pinouts and pin description

Doc ID 023353 Rev 1 39/119

TIM2_

7PA0

5PA1

6PA2

5PA3

6PA4

4PA5

8PA6

8PA7

8PA8 MCO

9 PA9 G4_IO1

CH1_E TR

TIM2_ CH2

TIM2_ CH3

TIM2_ CH4

TIM2_ CH1_E TR

TIM16_ CH1

TIM17_ CH1

TIM3_ CH2

TIM3_ CH1

TIM3_ CH2

G1_IO1

G1_IO2

G1_IO3

G1_IO4

G2_IO1

G2_IO2

G2_IO3

G2_IO4

SPI1_N SS

SPI1_S CK

TIM8_B KIN

TIM8_C H1N

I2C2_S MBAL

I2C2_SCLI2S3_MCKTIM1_

SPI1_M ISO

SPI1_M OSI

I2S2_MCKTIM1_

SPI3_ NSS/I2 S3_WS

TIM1_ BKIN

TIM1_ CH1N

CH1

CH2

USART 2_CTS

USART 2_RTS

USART 2_TX

USART 2_RX

USART 2_CK

USART 1_CK

USART 1_TX

COM P1_ OUT

COM P2_ OUT

COM P1_ OUT

COM P2_ OUT

COM P3_ OUT

COM P5_ OUT

TIM8_B KIN

TIM15_ CH1N

TIM15_ CH1

TIM15_ CH2

TIM15_B KIN

TM8_ ETR

TIM4_ ETR

TIM2_ CH3

EVENT OUT

40/119 Doc ID 023353 Rev 1

Table 11. Alternate functions (continued)

Port

n°

Name

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts and pin description STM32F302xx/STM32F303xx

9PA10

9PA11

9PA12

7PA13

7PA14

9PA15JTDI

5 PB0

6 PB1

JTMSSWDAT

JTCKSWCLK

TIM17_ BKIN

TIM16_ CH1

TIM16_ CH1N

TIM2_ CH1_E TR

TIM8_ CH1

TIM3_ CH3

TIM3_ CH4

G4_IO2

G4_IO3 IR-Out

G4_IO4

G3_IO2

G3_IO3

I2C2_S DA

I2C1_SDATIM8_CH2TIM1_

I2C1_SCLSPI1_N

TIM8_C H2N

TIM8_C H3N

TIM1_ CH3

TIM1_ CH1N

TIM1_ CH2N

BKIN

SPI3_ NSS/ I2S3_ WS

TIM1_ CH2N

TIM1_ CH3N

USART 1_RX

USART 1_CTS

USART 1_RTS

USART 3_CTS

USART 2_TX

USART 2_RX

COM P6_ OUT

COM P1_ OUT

COM P2_ OUT

COM P4_ OUT

CAN_RX

CAN_TX

TIM1_B KIN

TIM2_ CH4

TIM4_ CH1

TIM4_ CH2

TIM4_ CH3

TIM8_ BKIN

TIM1_ CH4

TIM1_ ETR

TIM1_ BKIN2

USBDM

USBDP

EVENT OUT

2 PB2 G3_IO4

10 PB3

JTDO/T RACES WO

TIM2_ CH2

TIM4_ ETR

G5_IO1

TIM8_C H1N

SPI1_S CK

SPI3_S CK /I2S3_ CK

USART 2_TX

TIM3_ ETR

EVENT OUT

Table 11. Alternate functions (continued)

Port

n°

Name

10 PB4 NJTRST

9 PB5

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

TIM16_ CH1

TIM16_ BKIN

TIM3_ CH1

TIM3_ CH2

G5_IO2

TIM8_ CH3N

TIM8_C H2N

I2C1_S MBAL

SPI1_M ISO

SPI1_M OSI

SPI3_ MISO/ I2S3ext _SD

SPI3_ MOSI/ I2S3_S D

USART 2_RX

USART 2_CK

TIM17 _BKIN

TIM17 _CH1

STM32F302xx/STM32F303xx Pinouts and pin description

EVENT OUT

Doc ID 023353 Rev 1 41/119

9 PB6

8 PB7

10 PB8

9 PB9

4 PB10

4 PB11

6 PB12 G6_IO2

5 PB13 G6_IO3

TIM16_ CH1N

TIM17_ CH1N

TIM16_ CH1

TIM17_ CH1

TIM2_ CH3

TIM2_ CH4

TIM4_ CH1

TIM4_ CH2

TIM4_ CH3

TIM4_ CH4

G5_IO3

G5_IO4

SYNCH

G6_IO1

I2C1_SCLTIM8_CH1TIM8_

ETR

I2C1_SDATIM8_B

KIN

I2C1_S CL

I2C1_S DA

I2C2_S MBAL

SPI2_N SS/I2S2 _WS

SPI2_S CK/I2S2 _CK

IROUT

TIM1_ BKIN

TIM1_ CH1N

USART 1_TX

USART 1_RX

USART 3_TX

USART 3_RX

USART 3_CK

USART 3_CTS

COM P1_ OUT

COM P2_ OUT

CAN_RX

CAN_TX

TIM8_ BKIN2

TIM3_ CH4

TIM8_ CH2

TIM8_ CH3

TIM1_ BKIN

EVENT OUT

42/119 Doc ID 023353 Rev 1

Table 11. Alternate functions (continued)

Port

n°

Name

6 PB14

5 PB15

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

TIM15_ CH1

TIM15_ CH2

TIM15_ CH1N

G6_IO4

TIM1_C H3N

SPI2_M ISO/ I2S2ext _SD

SPI2_M OSI/I2S 2_DOU T

TIM1_ CH2N

USART 3_RTS

Pinouts and pin description STM32F302xx/STM32F303xx

EVENT OUT

1PC0

1PC1

2PC2

2PC3

2PC4

3PC5

5PC6

5PC7

4PC8

5PC9

EVENT OUT

TIM3_ CH1

TIM3_ CH2

TIM3_ CH3

TIM3_ CH4

COMP 7_OUT

G3_IO1

TIM8_C H1

TIM8_C H2

TIM8_C H3

TIM8_C H4

CKIN

TIM1_ BKIN2

I2S2_ MCK

I2S3_ MCK

TIM8_ BKIN2

USART 1_TX

USART 1_RX

COMP 6_OUT

COMP 5_OUT

COMP 3_OUT

Table 11. Alternate functions (continued)

Port

n°

Name

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

STM32F302xx/STM32F303xx Pinouts and pin description

Doc ID 023353 Rev 1 43/119

5PC10

5PC11

5PC12

PC13

PC14

PC15

2PD0

4PD1

4PD2

3PD3

3PD4

2PD5

EVENT OUT

TIM3_ ETR

TIM2_ CH1_E TR

TIM2_ CH2

TIM8_C H1N

TIM8_C H2N

TIM8_C H3N

TIM1_C H1N

TIM8_C H4

TIM8_B KIN

UART4 _TX

UART4 _RX

UART5 _TX

UART5 __RX

SPI3_S CK/I2S 3_CK

SPI3_ MISO/I 2S3ext _SD

SPI3_ MOSI/ I2S3_S D

TIM8_ BKIN2

USART 3_TX

USART 3_RX

USART 3_CK

CAN_R X

CAN_T X

USART 2_CTS

USART 2_RTS

USART 2_TX

44/119 Doc ID 023353 Rev 1

Table 11. Alternate functions (continued)

Port

n°

Name

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts and pin description STM32F302xx/STM32F303xx

3PD6

3PD7

2PD8

2PD9

2PD10

2PD11

4PD12

3PD13

3PD14

4PD15

4 PE0

EVENT OUT

TIM2_ CH4

TIM2_ CH3

TIM4_ CH1

TIM4_ CH2

TIM4_ CH3

TIM4_ CH4

TIM4_ ETR

G8_IO1

G8_IO2

G8_IO3

G8_IO4

TIM16_ CH1

USART 2_RX

USART 2_CK

USART 3_TX

USART 3_RX

USART 3_CK

USART 3_CTS

USART 3_RTS

SPI2_ NSS

USART 1_TX

3 PE1

4 PE2

EVENT OUT

TRACECKEVENT

OUT

TIM3_ CH1

G7_IO1

TIM17_ CH1

USART 1_RX

Table 11. Alternate functions (continued)

Port

n°

Name

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

STM32F302xx/STM32F303xx Pinouts and pin description

Doc ID 023353 Rev 1 45/119

4 PE3

4 PE4

4 PE5

2 PE6

2 PE7

2 PE8

2 PE9

2 PE10

2 PE11

2 PE12

2 PE13

TRACED0EVENT

OUT

TRACED1EVENT

OUT

TRACED2EVENT

OUT

TRACED3EVENT

OUT

EVENT OUT

TIM3_ CH2

TIM3_ CH3

TIM3_ CH4

TIM1_ ETR

TIM1_ CH1N

TIM1_ CH1

TIM1_ CH2N

TIM1_ CH2

TIM1_ CH3N

TIM1_ CH3

G7_IO2

G7_IO3

G7_IO4

3 PE14

3 PE15

EVENT OUT

TIM1_ CH4

TIM1_ BKIN

TIM1_ BKIN2

USART 3_RX

46/119 Doc ID 023353 Rev 1

Table 11. Alternate functions (continued)

Port

n°

Name

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts and pin description STM32F302xx/STM32F303xx

2PF0

1PF1

1PF2

2PF4

4PF6

3PF9

3PF10

EVENT OUT

COMP 1_OUT

TIM4_ CH4

TIM15_ CH1

TIM15_ CH2

I2C2_S DA

I2C2_S CL

TIM1_ CH3N

USART 3_RTS

SPI2_S CK

STM32F302xx/STM32F303xx Memory mapping

0xFFFF FFFF

0xE000 0000

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x4000 0000

0x2000 0000

0x0000 0000

Cortex-M4

Internal

Peripherals

SRAM

CODE

Option bytes

System memory

CCM RAM

Flash memory

Flash, system memory

or SRAM, depending

on BOOT configuration

AHB2

AHB1

APB2

APB1

0x5000 0000

0x4800 1800

0x4800 0000

0x4002 43FF

0x4002 0000

0x4001 6C00

0x4001 0000

0x4000 A000

0x4000 0000

0x1FFF FFFF

0x1FFF F800

0x1FFF D800

0x1000 2000

0x0804 0000

0x0800 0000

0x0004 0000

0x0000 0000

0x1000 0000

Reserved

MS30355V1

AHB3

0x5000 07FF

Reserved

5 Memory mapping

Figure 7. STM32F30x memory map

Doc ID 023353 Rev 1 47/119

Memory mapping STM32F302xx/STM32F303xx

Table 12. STM32F30x memory map and peripheral register boundary

addresses

Bus Boundary address

0x5000 0400 - 0x5000 07FF 1 K ADC3 - ADC4

AHB3

0x5000 0000 - 0x5000 03FF 1 K ADC1 - ADC2

0x4800 1800 - 0x4FFF FFFF ~132 M Reserved

0x4800 1400 - 0x4800 17FF 1 K GPIOF

0x4800 1000 - 0x4800 13FF 1 K GPIOE

0x4800 0C00 - 0x4800 0FFF 1 K GPIOD

AHB2

0x4800 0800 - 0x4800 0BFF 1 K GPIOC

0x4800 0400 - 0x4800 07FF 1 K GPIOB

0x4800 0000 - 0x4800 03FF 1 K GPIOA

0x4002 4400 - 0x47FF FFFF ~128 M Reserved

0x4002 4000 - 0x4002 43FF 1 K TSC

0x4002 3400 - 0x4002 3FFF 3 K Reserved

0x4002 3000 - 0x4002 33FF 1 K CRC

0x4002 2400 - 0x4002 2FFF 3 K Reserved

0x4002 2000 - 0x4002 23FF 1 K Flash interface

AHB1

0x4002 1400 - 0x4002 1FFF 3 K Reserved

0x4002 1000 - 0x4002 13FF 1 K RCC

0x4002 0800 - 0x4002 0FFF 2 K Reserved

Size

(bytes)

Peripheral

0x4002 0400 - 0x4002 07FF 1 K DMA2

0x4002 0000 - 0x4002 03FF 1 K DMA1

0x4001 8000 - 0x4001 FFFF 32 K Reserved

0x4001 4C00 - 0x4001 7FFF 13 K Reserved

0x4001 4800 - 0x4001 4BFF 1 K TIM17

0x4001 4400 - 0x4001 47FF 1 K TIM16

0x4001 4000 - 0x4001 43FF 1 K TIM15

0x4001 3C00 - 0x4001 3FFF 1 K Reserved

APB2

48/119 Doc ID 023353 Rev 1

0x4001 3800 - 0x4001 3BFF 1 K USART1

0x4001 3400 - 0x4001 37FF 1 K TIM8

0x4001 3000 - 0x4001 33FF 1 K SPI1

0x4001 2C00 - 0x4001 2FFF 1 K TIM1

0x4001 0800 - 0x4001 2BFF 9 K Reserved

0x4001 0400 - 0x4001 07FF 1 K EXTI

0x4001 0000 - 0x4001 03FF 1 K SYSCFG + COMP + OPAMP

STM32F302xx/STM32F303xx Memory mapping

Table 12. STM32F30x memory map and peripheral register boundary

addresses (continued)

Bus Boundary address

0x4000 8000 - 0x4000 FFFF 32 K Reserved

0x4000 7800 - 0x4000 7FFF 2 K Reserved

0x4000 7400 - 0x4000 77FF 1 K DAC (dual)

0x4000 7000 - 0x4000 73FF 1 K PWR

0x4000 6C00 - 0x4000 6FFF 1 K Reserved

0x4000 6800 - 0x4000 6BFF 1 K Reserved

0x4000 6400 - 0x4000 67FF 1 K bxCAN

0x4000 6000 - 0x4000 63FF 1 K USB SRAM 512 bytes

0x4000 5C00 - 0x4000 5FFF 1 K USB device FS

0x4000 5800 - 0x4000 5BFF 1 K I2C2

0x4000 5400 - 0x4000 57FF 1 K I2C1

0x4000 5000 - 0x4000 53FF 1 K UART5

0x4000 4C00 - 0x4000 4FFF 1 K UART4

0x4000 4800 - 0x4000 4BFF 1 K USART3

0x4000 4400 - 0x4000 47FF 1 K USART2

APB1

0x4000 4000 - 0x4000 43FF 1 K I2S3ext

0x4000 3C00 - 0x4000 3FFF 1 K SPI3/I2S3

Size

(bytes)

Peripheral

0x4000 3800 - 0x4000 3BFF 1 K SPI2/I2S2

0x4000 3400 - 0x4000 37FF 1 K I2S2ext

0x4000 3000 - 0x4000 33FF 1 K IWDG

0x4000 2C00 - 0x4000 2FFF 1 K WWDG

0x4000 2800 - 0x4000 2BFF 1 K RTC

0x4000 1800 - 0x4000 27FF 4 K Reserved

0x4000 1400 - 0x4000 17FF 1 K TIM7

0x4000 1000 - 0x4000 13FF 1 K TIM6

0x4000 0C00 - 0x4000 0FFF 1 K Reserved

0x4000 0800 - 0x4000 0BFF 1 K TIM4

0x4000 0400 - 0x4000 07FF 1 K TIM3

0x4000 0000 - 0x4000 03FF 1 K TIM2

Doc ID 023353 Rev 1 49/119

Electrical characteristics STM32F302xx/STM32F303xx

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6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

6.1.2 Typical values

= 25 °C and TA = TAmax (given by

Unless otherwise specified, typical data are based on TA = 25 °C, V are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Figure 8. Pin loading conditions Figure 9. Pin input voltage

(mean±2Σ).

= V

= 3.3 V. They

DDA

50/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

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6.1.6 Power supply scheme

Figure 10. Power supply scheme

6.1.7 Current consumption measurement

Figure 11. Current consumption measurement scheme

Doc ID 023353 Rev 1 51/119

Electrical characteristics STM32F302xx/STM32F303xx

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics,

Table 14: Current characteristics, and Table 15: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 13. Voltage characteristics

Symbol Ratings Min Max Unit

(1)(2)

VDD–V

DD–VDDA

External main supply voltage (including V VDD)

Allowed voltage difference for VDD > V

Input voltage on FT and FTf pins V

(3)

Input voltage on TTa pins V

Input voltage on any other pin V

|ΔV

| Variations between different V

DDx

− VSS| Variations between all the different ground pins 50

SSX

ESD(HBM)

1. All main power (VDD, V permitted range.

2. The following relationship must be respected between V V

in the power up sequence. V

maximum must always be respected. Refer to Table 14: Current characteristics for the maximum allowed injected

3. V

current values.

Electrostatic discharge voltage (human body model)

) and ground (VSS, V

DDA

can be greater than or equal to VDD.

DDA

power pins 50

) pins must always be connected to the external power supply, in the

SSA

and VDD: V

DDA

and

DDA

0.4

DDA

-0.3 4.0

− 0.3 V

− 0.3 4.0

see Section 6.3.11: Electrical

sensitivity characteristics

must power on before or at the same time as

DDA

+ 4.0

+ 0.3

52/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 14. Current characteristics

(1)

Symbol Ratings Max. Unit

VDD

VSS

Total current into V

Total current out of V

power lines (source)

ground lines (sink)

(2)

TBD

Output current sunk by any I/O and control pin 25

INJ(PIN)

ΣI

INJ(PIN)

(3)

1. TBD stands for “to be defined”.

2. All main power (V permitted range.

3. A positive injection is induced by V exceeded. Refer also to Table 13: Voltage characteristics for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. See note 2 below Table 58 on page 99.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. When several inputs are submitted to a current injection, the maximum ΣI negative injected currents (instantaneous values).

Output current source by any I/Os and control pin − 25

Injected current on FT, FTf, and TTa pins -5/+NA

Injected current on any other pin ± 5

Total injected current (sum of all I/O and control pins)

, V

Table 15. Thermal characteristics

) and ground (VSS, V

DDA

IN>VDD

while a negative injection is induced by VIN<VSS. I

) pins must always be connected to the external power supply, in the

SSA

(5)

is the absolute sum of the positive and

INJ(PIN)

(4)

± 25

must never be

Symbol Ratings Value Unit

STG

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

Doc ID 023353 Rev 1 53/119

Electrical characteristics STM32F302xx/STM32F303xx

6.3 Operating conditions

6.3.1 General operating conditions

Table 16. General operating conditions

(1)

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK1

PCLK2

DDA

BAT

Internal AHB clock frequency 0 72

Internal APB1 clock frequency 0 36

Internal APB2 clock frequency 0 72

Standard operating voltage 2 3.6 V

Analog operating voltage (OPAMP and DAC not used)

Analog operating voltage (OPAMP and DAC used)

Must have a potential equal to or higher than V

23.6

2.4 3.6

Backup operating voltage 1.65 3.6 V

Power dissipation at T 85 °C for suffix 6 or TA =

105 °C for suffix 7

Ambient temperature for 6 suffix version

(2)

LQFP100 TBD

LQFP48 TBD

Maximum power dissipation –40 85

Low power dissipation

(3)

–40 105

Ambient temperature for 7 suffix version

Maximum power dissipation –40 105

Low power dissipation

(3)

–40 125

6 suffix version –40 105

J Junction temperature range

7 suffix version –40 125

1. TBD stands for “to be defined”.

2. If TA is lower, higher PD values are allowed as long as TJ does not exceed T

characteristics).

3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed T

Table 15: Thermal characteristics).

(see Table 15: Thermal

Jmax

MHzf

mWLQFP64 TBD

°C

(see

54/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

6.3.2 Operating conditions at power-up / power-down

The parameters given in Tab l e 17 are derived from tests performed under the ambient temperature condition summarized in Ta bl e 1 6.

Table 17. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

(1)

VDD

VDDA

1. TBD stands for “to be defined”.

fall time rate 20

rise time rate 0

DDA

fall time rate 20

DDA

6.3.3 Embedded reset and power control block characteristics

The parameters given in Tab l e 18 are derived from tests performed under ambient

VDD rise time rate 0

temperature and V

Table 18. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

Power on/power down

POR/PDR

PDRhyst

RSTTEMPO

1. The PDR detector monitors VDD and also V monitors only VDD.

2. The product behavior is guaranteed by design down to the minimum V

3. Guaranteed by design, not tested in production

(1)

reset threshold

(1)

PDR hysteresis 40 mV

(3)

Reset temporization 1.5 2.5 4.5 ms

supply voltage conditions summarized in Tab l e 16 .

Falling edge

Rising edge 1.84 1.92 2.0 V

(if kept enabled in the option bytes). The POR detector

DDA

POR/PDR

(2)

1.8

value.

µs/V

1.88 1.96 V

Table 19. Programmable voltage detector characteristics

Symbol Parameter Conditions Min

Rising edge 2.1 2.18 2.26 V

PVD0

PVD threshold 0

Falling edge 2 2.08 2.16 V

Rising edge 2.19 2.28 2.37 V

PVD1

PVD threshold 1

Falling edge 2.09 2.18 2.27 V

Rising edge 2.28 2.38 2.48 V

PVD2

PVD threshold 2

Falling edge 2.18 2.28 2.38 V

Rising edge 2.38 2.48 2.58 V

PVD3

PVD threshold 3

Falling edge 2.28 2.38 2.48 V

Rising edge 2.47 2.58 2.69 V

PVD4

PVD threshold 4

Falling edge 2.37 2.48 2.59 V

Doc ID 023353 Rev 1 55/119

(1)

Typ Ma x

(1)

Unit

Electrical characteristics STM32F302xx/STM32F303xx

Table 19. Programmable voltage detector characteristics (continued)

Symbol Parameter Conditions Min

(1)

Typ Ma x

(1)

Unit

PVD5

PVD threshold 5

Falling edge 2.47 2.58 2.69 V

Rising edge 2.66 2.78 2.9 V

Rising edge 2.57 2.68 2.79 V

PVD6

PVD threshold 6

Falling edge 2.56 2.68 2.8 V

Rising edge 2.76 2.88 3 V

PVD7

PVDhyst

IDD(PVD)

1. Data based on characterization results only, not tested in production.

2. Guaranteed by design, not tested in production.

PVD threshold 7

Falling edge 2.66 2.78 2.9 V

(2)

PVD hysteresis 100 mV

PVD current consumption

0.15 0.26 µA

56/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

6.3.4 Embedded reference voltage

The parameters given in Tab l e 20 are derived from tests performed under ambient temperature and V

Table 20. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

supply voltage conditions summarized in Tab l e 16 .

REFINT

Internal reference voltage

ADC sampling time when

S_vrefint

reading the internal reference voltage

Internal reference voltage

RERINT

spread over the temperature range

Coeff

1. Data based on characterization results, not tested in production.

2. Guaranteed by design, not tested in production

Temperature coefficient

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 11: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark x.x code.

–40 °C < T

< +105 °C 1.16 1.2 1.25 V

< +85 °C 1.16 1.2 1.24

VDD = 3 V ±10 mV

(1)

2.2 - - µs

(2)

ppm/°C

100

Typical and maximum current consumption

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except when explicitly mentioned

● The Flash memory access time is adjusted to the f

to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)

● Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

PCLK2

= f

HCLK

The parameters given in Tab l e 21 to Tab l e 25 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Tab le 1 6.

Doc ID 023353 Rev 1 57/119

or VSS (no load)

frequency (0 wait state from 0

HCLK

and f

PCLK1

= f

HCLK/2

Electrical characteristics STM32F302xx/STM32F303xx

Table 21. Typical and maximum current consumption from VDD supply

at V

DD=

3.6 V

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions f

HCLK

Max @ T

Typ

(1)

Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

72 MHz

64 MHz

External clock (HSE bypass)

Supply current in

48 MHz

32 MHz

24 MHz

8 MHz

Run mode, executing from Flash

1 MHz

64 MHz

48 MHz Internal clock (HSI)

32 MHz

24 MHz

8 MHz

72 MHz

64 MHz

Max @ T

(1)

Unit

Supply current in Run mode, executing from RAM

External clock (HSE bypass)

Internal clock (HSI)

48 MHz

32 MHz

24 MHz

8 MHz

1 MHz

64 MHz

48 MHz

32 MHz

24 MHz

8 MHz

58/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 21. Typical and maximum current consumption from VDD supply

at V

3.6 V (continued)

DD=

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions f

HCLK

Max @ T

Typ

(1)

Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

8 MHz

1 MHz

64 MHz

Supply current in Sleep mode, executing from Flash or RAM

External clock (HSE bypass)

48 MHz Internal clock (HSI)

32 MHz

24 MHz

8 MHz

1. Data based on characterization results, not tested in production unless otherwise specified.

Max @ T

(1)

Unit

Doc ID 023353 Rev 1 59/119

Electrical characteristics STM32F302xx/STM32F303xx

Table 22. Typical and maximum current consumption from the V

Symbol Parameter Conditions f

HSE

bypass,

PLL on

Supply

current in

Run mode,

code

HSE

bypass,

PLL off

executing

from Flash

or RAM

HSI clock,

PLL on

HSI clock,

PLL off

DDA

HSE

bypass,

PLL on

Supply

current in

Sleep

mode,

HSE

bypass,

PLL off

code

executing

from Flash

or RAM

HSI clock,

PLL on

HCLK

Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

8 MHz

1 MHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

8 MHz

72 MHz

64 MHz

48 MHz

32 MHz

24 MHz

8 MHz

1 MHz

72 MHz

64 MHz

48 MHz

32 MHz

2.4 V V

DDA=

Max @ T

(1)

DDA

Typ

supply

DDA=

3.6 V

Max @ T

(1)

Unit

µA

24 MHz

HSI clock,

PLL off

1. Data based on characterization results, not tested in production.

8 MHz

60/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 23. Typical and maximum VDD consumption in Stop and Standby modes

Symbol Parameter Conditions

Typ @VDD (VDD=V

2.0V 2.4V 2.7V 3.0 V 3.3V 3.6 V

)Max

DDA

25 °C

Regulator in run mode,

Supply

all oscillators OFF

current in

Regulator in low-power mode, all oscillators OFF

LSI ON and IWDG ON

Stop mode

Supply current in Standby

LSI OFF and IWDG OFF

mode

Table 24. Typical and maximum V

Symbol Parameter Conditions

consumption in Stop and Standby modes

DDA

= V

Typ @V

)Max

DDA

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

Regulator in run mode,

Supply current in Stop mode

all oscillators OFF

Regulator in low-power mode, all oscillators OFF

DDA

Supply current in Standby mode

Supply current in Stop mode

LSI ON and IWDG ON

monitoring ON

DDA

LSI OFF and IWDG

OFF

Regulator in run mode, all oscillators OFF

Regulator in low-power mode, all oscillators OFF

Supply current in Standby mode

1. Data based on characterization results, not tested in production.

LSI ON and IWDG ON

monitoring OFF

DDA

LSI OFF and IWDG

OFF

TA =

85 °C

TA =

85 °C

(1)

TA =

105 °C

TA =

105 °C

Unit

µA

Unit

µA

Doc ID 023353 Rev 1 61/119

Electrical characteristics STM32F302xx/STM32F303xx

Table 25. Typical and maximum current consumption from V

Typ @V

BAT

Symbol Parameter Conditions

= 1.8 V

= 2.4 V

= 1.65 V

= 2.7 V

LSE & RTC ON; "Xtal mode" lower driving capability; LSEDRV[1:0] = '00'

LSE & RTC ON; "Xtal mode" higher driving

DD_VBAT

Backup domain supply current

capability; LSEDRV[1:0] = '11'

1. Data based on characterization results, not tested in production.

Typical current consumption

The MCU is placed under the following conditions:

● V

● All I/O pins are in analog input configuration

● The Flash access time is adjusted to f

● Prefetech is ON when the peripherals are enabled, otherwise it is OFF

● When the peripherals are enabled, f

●

● AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and

= V

DDA

= 3.3 V

frequency (0 wait states from 0 to 24 MHz,

HCLK

1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz)

= f

APB1

AHB/2

PLL is used for frequencies greater than 8 MHz

500 kHz respectively

BAT

, f

= 3.3 V

APB2

supply

= 3.6 V

= f

AHB

TA =

25 °C

Max

TA =

85 °C

(1)

TA =

105 °C

Unit

µA

A development tool is connected to the board and the parasitic pull-up current is around 30 µA.

62/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 26. Typical current consumption in Run mode, code with data processing

running from Flash

Typ

Symbol Parameter Conditions f

Supply current in

Run mode from

supply

Running from HSE crystal clock 8 MHz,

500 kHz

code executing from Flash

Supply current in

DDA

Run mode from V

supply

DDA

500 kHz

HCLK

72 MHz

64 MHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

72 MHz

64 MHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

Peripherals

enabled

Peripherals

disabled

Unit

µA

Doc ID 023353 Rev 1 63/119

Electrical characteristics STM32F302xx/STM32F303xx

Table 27. Typical current consumption in Sleep mode, code running from Flash or RAM

Typ

Symbol Parameter Conditions f

Supply current in

Sleep mode from VDD supply

Running from HSE crystal clock 8 MHz,

500 kHz

125 kHz

code executing from Flash or RAM

Supply current in

DDA

Run mode from V

supply

DDA

500 kHz

125 kHz

HCLK

72 MHz

64 MHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

72 MHz

64 MHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

Peripherals

enabled

Peripherals

disabled

Unit

µA

64/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

DDfSW

C××=

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 45: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 29: Peripheral current consumption), the I/Os used by an application also contribute to

the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

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Electrical characteristics STM32F302xx/STM32F303xx

Table 28. Switching output I/O current consumption

Symbol Parameter Conditions

(1)

= 3.3 V

C =C

INT

= 3.3 V

= 0 pF

ext

C = C

INT

+ C

EXT

+ C

I/O toggling

frequency (fSW)

Typ U nit

I/O current

consumption

C = C

ext

INT

= 10 pF

+ C

EXT +CS

VDD = 3.3 V

= 22 pF

ext

INT

+ C

EXT +CS

C = C

VDD = 3.3 V

= 33 pF

ext

C = C

INT

C = C

+ C

EXT

int

+ C

VDD = 3.3 V C

= 47 pF

ext

C = C

INT

C = C

+ C

EXT

int

+ C

66/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 28. Switching output I/O current consumption (continued)

= 2.4 V

C = C

ext

INT

C = C

= 47 pF

+ C

EXT

int

+ C

1. CS = 7 pF (estimated value).

I/O current consumption

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Ta bl e 2 9. The MCU is placed under the following conditions:

● all I/O pins are in input mode with a static value at V

● all peripherals are disabled unless otherwise mentioned

● the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

● ambient operating temperature and V

supply voltage conditions summarized in

Ta bl e 1 3

or VSS (no load)

Doc ID 023353 Rev 1 67/119

Electrical characteristics STM32F302xx/STM32F303xx

Table 29. Peripheral current consumption

Typical consumption at 25 °C

Peripheral

ADC1

ADC2

ADC3

ADC4

COMP1

COMP2

COMP3

COMP4

COMP5

COMP6

COMP7

DAC CH1

DAC CH2

OPAMP1

OPAMP2

OPAMP3

OPAMP4

DMA

GPIOA

GPIOB

GPIOC

GPIOD

GPIOF

GPIOE

I2C1

I2C2

I2S2

I2S3

IWDG

SPI1

SPI2

SPI3

TIM1

TIM2

(2)

(3)

(4)

(5)

(1)

Unit

DDA

68/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 29. Peripheral current consumption

Typical consumption at 25 °C

Peripheral

TIM3

TIM4

TIM6

TIM7

TIM8

TIM15

TIM16

TIM17

TSC

USART1

USART2

USART3

USART4

USART5

WWDG

CAN

USB

(1)

(continued)

DDA

Unit

1. f

2. COMP IDDA is specified as IDD(COMP)

3. DAC channel 1 enabled

4. DAC channel 2 enabled

5. OPAMP IDDA is specified as IDD(OPAMP)

= 72 MHz, f

HCLK

APB1

= f

HCLK/2

, f

APB2

= f

, default prescaler value for each peripheral.

HCLK

Doc ID 023353 Rev 1 69/119

Electrical characteristics STM32F302xx/STM32F303xx

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6.3.6 External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Tab l e 30 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Ta bl e 1 6.

Table 30. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

HSE_ext

HSEH

HSEL

w(HSEH)

w(HSEL)

r(HSE)

f(HSE)

1. Guaranteed by design, not tested in production.

User external clock source frequency

(1)

OSC_IN input pin high level voltage 0.7V

OSC_IN input pin low level voltage V

(1)

OSC_IN high or low time

OSC_IN rise or fall time

1832MHz

Figure 12. High-speed external clock source AC timing diagram

0.3V

70/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

-36

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Low-speed external user clock generated from an external source

The characteristics given in Tab l e 31 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Ta bl e 1 6.

Table 31. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

LSE_ext

LSEH

LSEL

w(LSEH)

w(LSEL)

r(LSE)

f(LSE)

1. Guaranteed by design, not tested in production.

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

(1)

0.7V

450

Figure 13. Low-speed external clock source AC timing diagram

32.768 1000 kHz

0.3V

Doc ID 023353 Rev 1 71/119

Electrical characteristics STM32F302xx/STM32F303xx

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Ta bl e 3 2. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 32. HSE oscillator characteristics

Symbol Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit

OSC_IN

SU(HSE)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design, not tested in production.

3. This consumption level occurs during the first 2/3 of the t

4. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Oscillator frequency 4 8 32 MHz

Feedback resistor 200 kΩ

During startup

=3.3 V, Rm= 30Ω,

CL=10 pF@8 MHz

=3.3 V, Rm= 45Ω,

CL=10 pF@8 MHz

HSE current consumption

=3.3 V, Rm= 30Ω,

CL=10 pF@32 MHz

=3.3 V, Rm= 30Ω,

CL=10 pF@32 MHz

=3.3 V, Rm= 30Ω,

CL=10 pF@32 MHz

Oscillator transconductance Startup 10 mA/V

(4)

Startup time VDD is stabilized 2 ms

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

(3)

0.4

0.5

0.8

1.5

startup time

8.5

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 14). C

and C

are usually the

same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing C

and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

72/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

-36

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GAIN



Figure 14. Typical application with an 8 MHz crystal

1. R

value depends on the crystal characteristics.

EXT

Doc ID 023353 Rev 1 73/119

Electrical characteristics STM32F302xx/STM32F303xx

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Ta bl e 3 3. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 33. LSE oscillator characteristics (f

Symbol Parameter Conditions

= 32.768 kHz)

LSE

(1)

Min

(2)

Typ Max

(2)

Unit

LSEDRV[1:0]=00

lower driving capability

LSEDRV[1:0]=01

medium low driving capability

LSE current consumption

LSEDRV[1:0]=10

medium high driving capability

LSEDRV[1:0]=11

higher driving capability

LSEDRV[1:0]=00

lower driving capability

LSEDRV[1:0]=01

Oscillator transconductance

medium low driving capability

LSEDRV[1:0]=10

medium high driving capability

LSEDRV[1:0]=11

higher driving capability

(3)

SU(LSE)

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

2. Guaranteed by design, not tested in production.

3. t

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Startup time VDD is stabilized 2 s

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

0.5 0.9

1.3

1.6

µA/V

µA

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

74/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

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Figure 15. Typical application with a 32.768 kHz crystal

6.3.7 Internal clock source characteristics

The parameters given in Tab l e 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Tab le 1 6.

High-speed internal (HSI) RC oscillator

Table 34. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

HSI

Frequency 8 MHz

TRIM HSI user trimming step 1

DuCy

(HSI)

ACC

HSI

su(HSI)

DD(HSI)

1. V

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

= 3.3 V, TA = –40 to 105 °C unless otherwise specified.

DDA

Duty cycle 45

= –40 to 105 °C –2

Accuracy of the HSI oscillator (factory calibrated)

= –10 to 85 °C –1.5

= 0 to 70 °C –1.3

= 25 °C –1.1 1.8 %

HSI oscillator startup time

HSI oscillator power consumption

(2)

(3)

(2)

2.5

2.2

80 100

(2)

(3)

(2)

(3)

(2)

µs

µA

Doc ID 023353 Rev 1 75/119

Electrical characteristics STM32F302xx/STM32F303xx

Low-speed internal (LSI) RC oscillator

Table 35. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

(1)

LSI

su(LSI)

DD(LSI)

DDA

2. Guaranteed by design, not tested in production.

Frequency 30 40 50 kHz

(2)

LSI oscillator startup time 85 µs

(2)

LSI oscillator power consumption 0.75 1.2 µA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

Wakeup time from low-power mode

The wakeup times given in Ta bl e 3 6 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

● Stop or Standby mode: the clock source is the RC oscillator

● Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V voltage conditions summarized in Tab le 1 6 .

Table 36. Low-power mode wakeup timings

Symbol Parameter Conditions

Regulator in run

WUSTOP

WUSTANDBY

Wakeup from Stop mode

Wakeup from Standby mode

mode

Regulator in low power mode

Typ @VDD

= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V

supply

Max Unit

µs

WUSLEEP

Wakeup from Sleep mode

6.3.8 PLL characteristics

The parameters given in Tab l e 37 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Tab le 1 6.

76/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 37. PLL characteristics

Val ue

Symbol Parameter

Unit

Min Typ Max

(1)

PLL_IN

PLL_OUT

LOCK

PLL input clock

PLL input clock duty cycle 40

PLL multiplier output clock 16

PLL lock time 200

Jitter Cycle-to-cycle jitter 300

1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

2. Guaranteed by design, not tested in production.

PLL_OUT

(2)

MHz

72 MHz

(2)

µs

6.3.9 Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

Doc ID 023353 Rev 1 77/119

Electrical characteristics STM32F302xx/STM32F303xx

Table 38. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max

(1)

Unit

prog

ERASE

16-bit programming time TA = –40 to +105 °C TBD TBD TBD µs

Page (1 KB) erase time TA = –40 to +105 °C TBD TBD ms

Mass erase time TA = –40 to +105 °C TBD TBD ms

Read mode, VDD = 3.3 V TBD mA

= 3.3 V TBD mA

Supply current

Write mode, V

Erase mode, V

Power-down / Halt mode, V

= 3.0 to 3.6 V

1. Guaranteed by design, not tested in production.

Table 39. Flash memory endurance and data retention

Programming voltage 2 3.6 V

prog

Symbol Parameter Conditions

= –40 to +85 °C (6 suffix versions)

END

RET

1. Data based on characterization results, not tested in production.

2. Cycling performed over the whole temperature range.

Endurance

Data retention

= –40 to +105 °C (7 suffix versions)

(2)

1 kcycle

10 kcycles

at TA = 85 °C

(2)

at TA = 105 °C TBD

(2)

at TA = 55 °C TBD

TBD µA

Val ue

Unit

Min

(1)

TBD kcycles

TBD

Ye a r s1 kcycle

78/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

6.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Tab l e 40 . They are based on the EMS levels and classes defined in application note AN1709.

Table 40. EMS characteristics

and

Symbol Parameter Conditions

= 3.3 V, LQFP100, TA = +25 °C,

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on VDD and V pins to induce a functional disturbance

= 72 MHz

HCLK

conforms to IEC 61000-4-2

= 3.3 V, LQFP100, TA = +25 °C,

= 72 MHz

HCLK

conforms to IEC 61000-4-4

Level/

Class

TBD

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

● Corrupted program counter

● Unexpected reset

● Critical Data corruption (control registers...)

Doc ID 023353 Rev 1 79/119

Electrical characteristics STM32F302xx/STM32F303xx

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Table 41. EMI characteristics

Symbol Parameter Conditions

= 3.3 V, TA = 25 °C,

EMI

Peak level

LQFP100 package compliant with IEC 61967-2

6.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 42. ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum value

Monitored

frequency band

Max vs. [f

72 MHz

HSE/fHCLK

]

Unit

0.1 to 30 MHz TBD

dBµV30 to 130 MHz TBD

130 MHz to 1GHz TBD

SAE EMI Level TBD -

(1)

(2)

Unit

ESD(HBM)

ESD(CDM)

1. TBD stands for “to be defined”.

2. Data based on characterization results, not tested in production.

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

TA = +25 °C, conforming to JESD22-A114

TA = +25 °C, conforming to JESD22-C101

80/119 Doc ID 023353 Rev 1

2TBD

II TBD

STM32F302xx/STM32F303xx Electrical characteristics

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 43. Electrical sensitivities

Symbol Parameter Conditions Class

(1)

LU Static latch-up class T

1. TBD stands for “to be defined”.

= +105 °C conforming to JESD78A TBD

6.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above V operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in Tab l e 44

Table 44. I/O current injection susceptibility

Symbol Description

(for standard, 3 V-capable I/O pins) should be avoided during normal product

(1)

Functional susceptibility

Negative injection

Positive

injection

Unit

Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins TBD TBD

INJ

1. TBD stands for “to be defined”.

Injected current on all FTf pins TBD TBD

Injected current on all TTa pins TBD TBD

Injected current on any other pin TBD TBD

TBD TBD

Doc ID 023353 Rev 1 81/119

Electrical characteristics STM32F302xx/STM32F303xx

6.3.13 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Ta bl e 4 5 are derived from tests performed under the conditions summarized in Tab l e 16 . All I/Os are CMOS and TTL compliant.

Table 45. I/O static characteristics

Symbol Parameter Conditions Min Typ

Max Unit

Standard I/O input low level voltage

TTa I/O input low level

voltage

FT and FTf low level voltage

(1)

I/O input

–0.3 0.3V

–0.3 0.475V

+0.07

-0.2

Standard I/O input high level voltage

TTa I/O input high level

voltage

FT and FTf high level voltage

(1)

I/O input

0.445V

0.5V

+0.398 VDD+0.3

+0.2 5.5

Standard I/O Schmitt trigger voltage hysteresis

TTa I/O Schmitt trigger

hys

voltage hysteresis

(2)

200

FT and FTf I/O Schmitt trigger voltage hysteresis

(2)

≤ VIN≤ V

I/O TC, FT and FTf

≤ VIN≤ V

V≤ V

≤ V

DDA

≤ 3.6 V

I/O TTa used in digital

100

±0.1

mode

= 5 V

Input leakage current

lkg

(3)

I/O FT and FTf

= 3.6 V,

V≤ V V

DDA =

≤ V

3.6 V

µA

I/O TTa used in digital

mode

≤ VIN≤ V

V≤ V

≤ V

DDA

≤ 3.6 V

I/O TTa used in analog

mode

82/119 Doc ID 023353 Rev 1

±0.2

STM32F302xx/STM32F303xx Electrical characteristics

MS30255V1

(V)

IHmin

2.0

ILmax

0.7

(V)

1.3

2.0 3.6

CMOS standard requirements V

IHmin

= 0.7V

ILmax

= 0.3V

+0.07

0.6

2.7 3.0 3.3

CMOS standard requirements V

ILmax

= 0.3V

IHmin

= 0.445V

+0.398

Input range not

guaranteed

MS30256V1

(V)

IHmin

2.0

ILmax

0.8

(V)

1.3

2.0 3.6

TTL standard requirements V

IHmin

= 2 V

ILmax

= 0.3V

+0.07

0.7

2.7 3.0 3.3

TTL standard requirements V

ILmax

= 0.8 V

IHmin

= 0.445V

+0.398

Input range not

guaranteed

Table 45. I/O static characteristics (continued)

Symbol Parameter Conditions Min Typ

Max Unit

Weak pull-up equivalent

(4)

resistor

Weak pull-down equivalent resistor

(4)

I/O pin capacitance 5 pF

= V

30 40 50 kΩ

1. To sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled.

2. Hysteresis voltage between Schmitt trigger switching levels. Data based on characterization, not tested in production.

3. Leakage could be higher than max. if negative current is injected on adjacent pins.

4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 16 and Figure 17 for standard I/Os.

Figure 16. TC and TTa I/O input characteristics - CMOS port

Figure 17. TC and TTa I/O input characteristics - TTL port

Doc ID 023353 Rev 1 83/119

Electrical characteristics STM32F302xx/STM32F303xx

MS30257V1

(V)

2.0

(V)

1.0

2.0 3.6

CMOS standard requirements V

IH min

= 0.7V

ILmax

= 0.475V

-0.2

0.5

CMOS standard requirements V

ILmax

= 0.3V

IHmin

= 0.5V

+0.2

Input range not

guaranteed

MS30258V1

(V)

2.0

(V)

1.0

2.0 3.6

ILmin

= 0.475V

-0.2

0.5

IHmin

= 0.5V

+0.2

Input range not

guaranteed

2.7

TTL standard requirements V

IHmin

= 2 V

TTL standard requirements V

ILmax

= 0.8 V

0.8

Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port

Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port

84/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V

OL/VOH

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2:

● The sum of the currents sourced by all the I/Os on V

consumption of the MCU sourced on V I

(see Ta bl e 1 4).

VDD

● The sum of the currents sunk by all the I/Os on V

consumption of the MCU sunk on V I

(see Ta bl e 1 4).

VSS

cannot exceed the absolute maximum rating

DD,

cannot exceed the absolute maximum rating

plus the maximum Run

DD,

plus the maximum Run

Output voltage levels

Unless otherwise specified, the parameters given in Ta bl e 4 6 are derived from tests performed under ambient temperature and V

Ta bl e 1 6. All I/Os (FT, TTa and Tc unless otherwise specified) are CMOS and TTL

compliant.

Table 46. Output voltage characteristics

supply voltage conditions summarized in

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at same time

Output high level voltage for an I/O pin

(3)

OLFM+

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed I

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 14 and the sum of IIO (I/O ports and control pins) must not exceed I

4. Data based on characterization results, not tested in production.

when 8 pins are sourced at same time

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at same time

Output low level voltage for an I/O pin

(1)(4)

when 8 pins are sunk at same time

Output high level voltage for an I/O pin

(3)(4)

when 8 pins are sourced at same time

Output low level voltage for an I/O pin

(1)(4)

when 8 pins are sunk at same time

Output high level voltage for an I/O pin

(3)(4)

when 8 pins are sourced at same time

Output low level voltage for an FTf I/O pin in FM+ mode

CMOS port

2.7 V < VDD < 3.6 V

TTL port I

2.7 V < V

= +20 mA

2.7 V < V

2 V < V

= +20 mA

2 V < V

= +8 mA

(2)

=+ 8mA

< 3.6 V

= +6 mA

< 2.7 V

< 3.6 V

VSS

(2)

VDD

TBD

Doc ID 023353 Rev 1 85/119

Electrical characteristics STM32F302xx/STM32F303xx

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 20 and

Ta bl e 4 7, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V

Table 47. I/O AC characteristics

supply voltage conditions summarized in Ta bl e 1 6.

(1)

OSPEEDRy

[1:0] value

FM+

configuration

(4)

Symbol Parameter Conditions Min Max Unit

(1)

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum frequency

Output high to low level fall time

Output low to high level rise time

(2)

CL = 50 pF, V

= 50 pF, V

CL = 50 pF, V

= 50 pF, V

CL = 30 pF, V

= 50 pF, VDD = 2.7 V to 3.6 V 30 MHz

= 50 pF, V

= 30 pF, V

= 50 pF, V

CL = 50 pF, V

= 30 pF, V

CL = 50 pF, V

= 2 V to 3.6 V 2 MHz

= 2 V to 3.6 V

= 2 V to 3.6 V 10 MHz

= 2 V to 3.6 V

= 2.7 V to 3.6 V 50 MHz

= 2 V to 2.7 V 20 MHz

= 2.7 V to 3.6 V 5

= 2.7 V to 3.6 V 8

= 2 V to 2.7 V 12

= 2.7 V to 3.6 V 5

= 2.7 V to 3.6 V 8

= 2 V to 2.7 V 12

125

(3)

Pulse width of external

-t

EXTIpw

signals detected by the

10 ns

EXTI controller

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 20.

3. Guaranteed by design, not tested in production.

4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F05xxx reference manual RM0091 for a description of FM+ I/O mode configuration.

MHz

86/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

ai14131

10%

90%

50%

r(IO)out

OUTPUT

EXTERNAL

ON 50pF

Maximum fr equency is achieved if (tr + tf) ≤ 2/3) T and if the duty cycle is (45-55%)

10 %

50%

90%

when loaded by 50pF

r(IO)out

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&

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

Figure 20. I/O AC characteristics definition

6.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

Unless otherwise specified, the parameters given in Ta bl e 4 8 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in

Ta bl e 1 6.

Table 48. NRST pin characteristics

(see Ta bl e 4 5).

Symbol Parameter Conditions Min Typ Max Unit

(1)

IL(NRST)

IH(NRST)

hys(NRST)

F(NRST)

NF(NRST)

NRST Input low level voltage –0.5 0.8

(1)

NRST Input high level voltage 2 VDD+0.5

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse 100 ns

(1)

NRST Input not filtered pulse 300 ns

(2)

= V

200 mV

30 40 50 kΩ

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

to the series resistance must be minimum (~10% order).

Figure 21. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 48. Otherwise the reset will not be taken into account by the device.

Doc ID 023353 Rev 1 87/119

max level specified in

IL(NRST)

Electrical characteristics STM32F302xx/STM32F303xx

6.3.15 Timer characteristics

The parameters given in Tab l e 49 are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 49. TIMx

Symbol Parameter Conditions Min Max Unit

(1)

characteristics

res(TIM)

Timer resolution time

TIMxCLK

x= 1.8

EXT

Timer external clock frequency on CH1 to CH4

TIMxCLK

x= 1.8

Res

COUNTER

MAX_COUNT

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17 timers.

Table 50. IWDG min/max timeout period at 40 kHz (LSI)

Timer resolution

TIM

16-bit counter clock period

Maximum possible count with 32-bit counter

Prescaler divider PR[2:0] bits

TIMx (except TIM2) 16

TIM2 32

Min timeout (ms) RL[11:0]=

= 72 MHz 13.9 ns

TIMxCLK

= 144MHz,

6.95 ns

TIMxCLK

= 72 MHz 0 36 MHz

= 144MHz,

072MHz

1 65536

= 72 MHz 0.0139 910 µs

TIMxCLK

65536 × 65536

= 72 MHz s

TIMxCLK

(1)

Max timeout (ms) RL[11:0]=

0x000

0xFFF

TIMxCLK

MHz

bit

TIMxCLK

/4 0 0.1 409.6

/8 1 0.2 819.2

/16 2 0.4 1638.4

/32 3 0.8 3276.8

/64 4 1.6 6553.6

/128 5 3.2 13107.2

/256 7 6.4 26214.4

1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

88/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 51. WWDG min-max timeout value @72 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value

10 TBD TBD

21 TBD TBD

42 TBD TBD

83 TBD TBD

Doc ID 023353 Rev 1 89/119

Electrical characteristics STM32F302xx/STM32F303xx

6.3.16 Communications interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Ta bl e 5 2 are derived from tests performed under ambient temperature, f summarized in Ta bl e 1 6.

The I

C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and V disabled, but is still present.

The I

C characteristics are described in Ta b le 5 2 . Refer also to Section 6.3.13: I/O port

characteristics

and SCL)

Table 52. I2C characteristics

Symbol Parameter

for more details on the input/output alternate function characteristics (SDA

(1)

Standard mode Fast mode Fast Mode Plus

Min Max Min Max Min Max

frequency and VDD supply voltage conditions

PCLK1

Unit

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA)

r(SCL)

f(SDA)

f(SCL)

h(STA)

su(STA)

su(STO)

w(STO:STA)

The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when

1. I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in production.

The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region

3. of the falling edge of SCL.

SCL clock low time 4.7 1.3 0.5

SCL clock high time 4.0 0.6 0.26

SDA setup time 250 100 50

SDA data hold time 0 3450

(2)

(3)

900

(2)

0450

SDA and SCL rise time 1000 300 120

SDA and SCL fall time 300 300 120

Start condition hold time 4.0 0.6 0.26

Repeated Start condition setup time

4.7 0.6 0.26

Stop condition setup time 4.0 0.6 0.26 μs

Stop to Start condition time (bus free)

Capacitive load for each bus

line

4.7 1.3 0.5 μs

400 400 550 pF

µs

Table 53. I2C analog filter characteristics

(1)

Symbol Parameter Min Max Unit

Pulse width of spikes that are suppressed by the analog filter

90/119 Doc ID 023353 Rev 1

50 260 ns

STM32F302xx/STM32F303xx Electrical characteristics

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34!24

3$ !

Ω

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3#,

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3#,

H34!

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1. Guaranteed by design, not tested in production.

Figure 22. I2C bus AC waveforms and measurement circuit

Measurement points are done at CMOS levels: 0.3V

and 0.7VDD.

Doc ID 023353 Rev 1 91/119

Electrical characteristics STM32F302xx/STM32F303xx

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Ta bl e 5 4 for SPI or in Ta bl e 5 5 for I2S are derived from tests performed under ambient temperature, f supply voltage conditions summarized in Ta b le 1 6.

frequency and VDD

PCLKx

Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I

Table 54. SPI characteristics

Symbol Parameter Conditions Min Max Unit

SCK

1/t

c(SCK)

r(SCK)

f(SCK)

DuCy(SCK)

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

h(MI)

h(SI)

(1)(2)

a(SO)

dis(SO)

v(SO)

v(MO)

h(SO)

h(MO)

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

SPI clock frequency

SPI clock rise and fall time

SPI slave input clock duty cycle

(1)

NSS setup time Slave mode TBD TBD

(1)

NSS hold time Slave mode TBD TBD

(1)

SCK high and low time

(1)

Data input setup time

(1)

Data input hold time

(1)

Data output access time Slave mode, f

(1)(3)

Data output disable time Slave mode TBD TBD

(1)

Data output valid time Slave mode (after enable edge) TBD TBD

(1)

Data output valid time Master mode (after enable edge) TBD TBD

(1)

Data output hold time

(1)

Master mode TBD TBD

Slave mode TBD TBD

Capacitive load: C = 30 pF TBD TBD ns

Slave mode TBD TBD %

Master mode, f presc = 4

= 36 MHz,

PCLK

TBD TBD

Master mode TBD TBD

Slave mode TBD TBD

Master mode TBD TBD

Slave mode TBD TBD

= 20 MHz TBD TBD

PCLK

Slave mode (after enable edge) TBD TBD

Master mode (after enable edge) TBD TBD

S).

MHz

92/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

ai14134c

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 OU T

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MS B O U T

MSB IN

BI T6 OU T

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

NSS input

Figure 23. SPI timing diagram - slave mode and CPHA = 0

Figure 24. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

(1)

Doc ID 023353 Rev 1 93/119

Electrical characteristics STM32F302xx/STM32F303xx

AI6

3#+/UTPUT

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C3#+

W3#+(

W3#+,

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F3#+

H-)

(IGH

3#+/UTPUT

#0(!

#0/,

#0/,

SU-)

V-/

H-/

Figure 25. SPI timing diagram - master mode

(1)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

94/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

Table 55. I2S characteristics

Symbol Parameter Conditions Min Max Unit

DuCy(SCK)

1/t

c(CK)

r(CK)

f(CK)

(1)

v(WS)

(1)

h(WS)

(1)

su(WS)

(1)

h(WS)

(1)

w(CKH)

(1)

w(CKL)

su(SD_MR)

su(SD_SR)

h(SD_MR)

h(SD_SR)

v(SD_ST)

h(SD_ST)

v(SD_MT)

I2S slave input clock duty cycle

I2S clock frequency

Slave mode TBD TBD %

Master mode (data: 16 bits, Audio frequency = 48 kHz)

TBD TBD

Slave mode TBD TBD

I2S clock rise and fall time Capacitive load CL=50pF TBD TBD

WS valid time Master mode TBD TBD

WS hold time Master mode TBD TBD

WS setup time Slave mode TBD TBD

WS hold time Slave mode TBD TBD

CK high and low time

(1)

Data input setup time Master receiver TBD TBD

(1)

Data input setup time Slave receiver TBD TBD

(1)(2)

Data input hold time

(1)(2)

Data output valid time

(1)

Data output hold time

(1)(2)

Data output valid time

Master f frequency = 48 kHz

Master receiver TBD TBD

Slave receiver TBD TBD

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

= 16 MHz, audio

PCLK

TBD TBD

MHz

(1)

h(SD_MT)

1. Data based on design simulation and/or characterization results, not tested in production.

2. Depends on f

Data output hold time

. For example, if f

PCLK

=8 MHz, then T

PCLK

Master transmitter (after enable edge)

PCLK

= 1/f

PLCLK

=125 ns.

Doc ID 023353 Rev 1 95/119

TBD TBD

Electrical characteristics STM32F302xx/STM32F303xx

CK Input

CPOL = 0

CPOL = 1

c(CK)

WS input

transmit

receive

w(CKH)

w(CKL)

su(WS)

v(SD_ST)

h(SD_ST)

h(WS)

su(SD_SR)

h(SD_SR)

MSB receive Bitn receive LSB receive

MSB transmit Bitn transmit LSB transmit

ai14881b

LSB receive

(2)

LSB transmit

(2)

CK output

CPOL = 0

CPOL = 1

c(CK)

WS output

receive

transmit

w(CKH)

w(CKL)

su(SD_MR)

v(SD_MT)

h(SD_MT)

h(WS)

h(SD_MR)

MSB receive Bitn receive LSB receive

MSB transmit Bitn transmit LSB transmit

ai14884b

f(CK)

r(CK)

v(WS)

LSB receive

(2)

LSB transmit

(2)

(1)

Figure 26. I2S slave timing diagram (Philips protocol)

1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 27. I2S master timing diagram (Philips protocol)

1. Data based on characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

96/119 Doc ID 023353 Rev 1

(1)

STM32F302xx/STM32F303xx Electrical characteristics

6.3.17 ADC characteristics

Table 56. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

DDA

ADC

TRIG

AIN

ADC

CAL

latr

TADCVREG

_STUP

CONV

1. Data guaranteed by design

Analog supply voltage for ADC ON

23.6V

ADC clock frequency TBD 72 MHz

(1)

Sampling rate

(1)

External trigger frequency

Resolution = 12 bits,

Fast Channel

Resolution = 10 bits,

Fast Channel

Resolution = 8 bits,

Fast Channel

Resolution = 6 bits,

Fast Channel

= 72MHz TBD kHz

ADC

TBD 5.14

TBD 6

TBD 7.2

TBD 9

Conversion voltage range 0 V

(1)

External input impedance TBD TBD kΩ

(1)

Sampling switch resistance TBD TBD kΩ

Internal sample and hold

(1)

capacitor

(1)

Calibration time

TBD TBD pF

TBD TBD µs

TBD TBD 1/f

(1)

Trigger conversion latency

TBD TBD µs

TBD TBD 1/f

= 72MHz 0.021 8.35 µs

(1)

Sampling time

ADC

1.5 601.5 1/f

ADC Voltage Regulator

(1)

Start-up time.

Total conversion time

(1)

(including sampling time)

Resolution = 12bits

TBD TBD TBD 10 µs

= 72MHz

ADC

0.19 3.5 µs

14 to 252 (t

for sampling +12.5 for

successive approximation)

TBD 1/f

DDA

MSPS

ADC

1/f

ADC

Doc ID 023353 Rev 1 97/119

Electrical characteristics STM32F302xx/STM32F303xx

Table 57. Minimum sampling time to be respected for fast and slow channels

Resolution

12-bit

Minimum sampling

AIN

(K Ohm)

time (ns)

Fast

channels

Slow

channels

01217

Resolution

AIN

(K Ohm)

07 11

Minimum sampling

time (ns)

Fast

channels

Slow

channels

0.05 16 21 0.05 10 14

0.1 20 25 0.1 13 16

0.2 27 33 0.2 18 22

0.5 52 58 0.5 35 38

19499 1 6366

8-bit

5 430 435 5 285 289

10 849 854 10 563 567

20 1690 1690 20 1120 1120

50 4190 4200 50 2780 2790

100 8350 8350 100 5550 5550

09 14

05 8

0.05 13 17 0.05 7 10

0.1 16 21 0.1 9 12

0.2 23 27 0.2 13 16

10-bit

0.5 43 48 0.5 26 28

17883 1 4749

6-bit

5 358 362 5 213 216

10 706 710 10 421 423

20 1400 1410 20 836 839

50 3490 3490 50 2080 2080

100 6950 6950 100 4150 4150

98/119 Doc ID 023353 Rev 1

STM32F302xx/STM32F303xx Electrical characteristics

1LSB

IDEAL

(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line

=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

=Offset Error: deviation between the first actual

transition and the first ideal one.

=Gain Error: deviation between the last ideal

transition and the last actual one.

=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

4095

4094

4093

12345 67

4093 4094 4095 4096

(1)

(2)

(3)

DDA

SSA

-36

1LSB

IDEAL





DDA

Table 58. ADC accuracy

(1)(2) (3)

Symbol Parameter Test conditions Typ Max

ET Total unadjusted error

EO Offset error TBD TBD

EG Gain error TBD TBD

ED Differential linearity error TBD TBD

EL Integral linearity error TBD TBD

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I affect the ADC accuracy.

3. Better performance may be achieved in restricted V

4. Data based on characterization results, not tested in production.

Figure 28. ADC accuracy characteristics

TBD

and ΣI

INJ(PIN)

, frequency and temperature ranges.

DDA

in Section 6.3.13 does not

INJ(PIN)

(4)

TBD TBD

Doc ID 023353 Rev 1 99/119

Electrical characteristics STM32F302xx/STM32F303xx

-36

!).X

),!

6

!).



PARASITIC

!).

6

!$#



BIT

CONVERTER

!$#



3AMPLEANDHOLD!$# CONVERTER

Figure 29. Typical connection diagram using the ADC

1. Refer to Tab l e 5 6 for the values of R

2. C pad capacitance (roughly 7 pF). A high C this, f

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

should be reduced.

ADC

AIN

, R

parasitic

ADC

and C

ADC

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

100/119 Doc ID 023353 Rev 1

ST STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Description

Table 2. STM32F30x family device features and peripheral counts

2 Device overview

Figure 1. STM32F302xx block diagram

Figure 2. STM32F303xx block diagram

Figure 3. Clock tree

3 Functional overview

3.1 ARM® Cortex™-M4 core with embedded Flash and SRAM

3.2 Memory protection unit

3.3 Nested vectored interrupt controller (NVIC)

3.4 Embedded Flash memory

3.5 CRC (cyclic redundancy check) calculation unit

3.6 Embedded SRAM

3.7 Clocks and startup

3.8 Boot modes

3.9 Power supply schemes

3.10 Power supply supervisor

3.11 Voltage regulator

3.12 Low-power modes

3.13 Real-time clock (RTC) and backup registers

3.14 DMA (direct memory access)

3.15 GPIOs (general-purpose inputs/outputs)

3.16 Fast ADC (analog-to-digital converter)

3.16.1 Temperature sensor

Table 3. Temperature sensor calibration values

Table 4. Temperature sensor calibration values

3.16.4 OPAMP reference voltage (VOPAMP)

3.17 DAC (digital-to-analog converter)

3.18 Operational amplifier

3.19 Fast comparators

3.20 Timers and watchdogs

Table 5. Timer feature comparison

3.20.1 Advanced timers (TIM1, TIM8)

3.20.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)

3.20.3 Basic timers (TIM6, TIM7)

3.20.4 Independent watchdog

3.20.5 Window watchdog

3.20.6 SysTick timer

3.21 Communication interfaces

3.21.1 I2C bus

Table 6. Comparison of I2C analog and digital filters

3.21.2 Universal synchronous/asynchronous receiver transmitter (USART)

3.21.3 Universal asynchronous receiver transmitter (UART)

3.21.5 Controller area network (CAN)

3.21.6 Universal serial bus (USB)

3.22 Touch sensing controller (TSC)

3.23 Development support

3.23.1 Serial wire JTAG debug port (SWJ-DP)

3.23.2 Embedded trace macrocell™

4 Pinouts and pin description

Figure 4. STM32F302xx/STM32F303xx LQFP48 pinout

Figure 5. STM32F302xx/STM32F303xx LQFP64 pinout

Figure 6. STM32F302xx/STM32F303xx LQFP100 pinout

Table 9. Legend/abbreviations used in the pinout table

Table 10. STM32F302xx/STM32F303xx pin definitions

Table 11. Alternate functions

5 Memory mapping

Figure 7. STM32F30x memory map

6 Electrical characteristics

6.1 Parameter conditions

6.1.1 Minimum and maximum values

6.1.2 Typical values

6.1.3 Typical curves

6.1.4 Loading capacitor

6.1.5 Pin input voltage

6.1.6 Power supply scheme

Figure 10. Power supply scheme

6.1.7 Current consumption measurement

Figure 11. Current consumption measurement scheme

6.2 Absolute maximum ratings

Table 13. Voltage characteristics

Table 14. Current characteristics

Table 15. Thermal characteristics

6.3 Operating conditions

6.3.1 General operating conditions