ST STM32F103C8, STM32F103R8, STM32F103V8, STM32F103T8, STM32F103RB User Manual

STM32F103x8

STM32F103xB

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces

Features

■ARM 32-bit Cortex™-M3 CPU Core

–72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access

–Single-cycle multiplication and hardware division

■Memories

–64 or 128 Kbytes of Flash memory

–20 Kbytes of SRAM

■Clock, reset and supply management

–2.0 to 3.6 V application supply and I/Os

–POR, PDR, and programmable voltage detector (PVD)

–4-to-16 MHz crystal oscillator

–Internal 8 MHz factory-trimmed RC

–Internal 40 kHz RC

–PLL for CPU clock

–32 kHz oscillator for RTC with calibration

■Low power

–Sleep, Stop and Standby modes

–VBAT supply for RTC and backup registers

■2 x 12-bit, 1 µs A/D converters (up to 16 channels)

–Conversion range: 0 to 3.6 V

–Dual-sample and hold capability

–Temperature sensor

■DMA

–7-channel DMA controller

–Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs

■Up to 80 fast I/O ports

–26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

VFQFPN48 7 × 7 mm				LQFP100 14 × 14 m
VFQFPN36 6 × 6 mm
				LQFP64 10	× 10 m
				LQFP48 7	× 7 m

BGA100 10 × 10 mm

BGA64 5 × 5 mm

■Debug mode

–Serial wire debug (SWD) & JTAG interfaces

■7 timers

–Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

–16-bit, motor control PWM timer with deadtime generation and emergency stop

–2 watchdog timers (Independent and Window)

–SysTick timer 24-bit downcounter

■Up to 9 communication interfaces

–Up to 2 x I2C interfaces (SMBus/PMBus)

–Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)

–Up to 2 SPIs (18 Mbit/s)

–CAN interface (2.0B Active)

–USB 2.0 full-speed interface

■CRC calculation unit, 96-bit unique ID

■Packages are ECOPACK®

Table 1. Device summary

Reference

Part number

STM32F103x8 STM32F103C8, STM32F103R8

STM32F103V8, STM32F103T8

STM32F103RB STM32F103VB,

STM32F103xB STM32F103CB, STM32F103TB

April 2011

Doc ID 13587 Rev 13

1/99

www.st.com

Contents	STM32F103x8, STM32F103xB

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
	2.1	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.2	Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	2.3	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 14 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17 2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.17Universal synchronous/asynchronous receiver transmitter (USART) . . 19

2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20

3	Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
4	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32

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5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		33
	5.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		35
5.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		36
	5.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	5.3.2	Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . .	37
	5.3.3	Embedded reset and power control block characteristics . . . . . . . . . . .	37
	5.3.4	Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
	5.3.5	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
	5.3.6	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
	5.3.7	Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	5.3.8	PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
	5.3.9	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
	5.3.10	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
	5.3.11	Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . .	58
	5.3.12	I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
	5.3.13	I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
	5.3.14	NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
	5.3.15	TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
	5.3.16	Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
	5.3.17	CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . .	72
	5.3.18	12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	73
	5.3.19	Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77

6	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			78
	6.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		78
	6.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		88
		6.2.1	Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	88
		6.2.2	Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . .	89

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7	Ordering information scheme . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . 91
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . 92

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STM32F103x8, STM32F103xB	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10 Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 12. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 13. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 14. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 42 Table 16. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 43 Table 17. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 18. Typical current consumption in Sleep mode, code running from Flash or

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 20. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 21. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 22. HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 24. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 25. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 26. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 27. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 28. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 29. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 30. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 31. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 32. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 33. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 36. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 37. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 38. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 39. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 40. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 41. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 43. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 44. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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Table 45. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 46. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 47. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 48. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 49. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 50. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 51. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 79 Table 52. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 80 Table 53. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 54. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 83 Table 55. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 84 Table 56. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 85 Table 57. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 87 Table 58. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 59. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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List of figures

Figure 1.	STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 2.	Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Figure 3.	STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 4.	STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 5.	STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 6.	STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 7.	STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 8.	STM32F103xx performance line VFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 9.	STM32F103xx performance line VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 10.	Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 11.	Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 12.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 13.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 14.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
Figure 15.	Typical current consumption in Run mode versus frequency (at 3.6 V) -
	code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . .	41
Figure 16.	Typical current consumption in Run mode versus frequency (at 3.6 V) -
	code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . .	41
Figure 17.	Typical current consumption on VBAT with RTC on versus temperature at different
	VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
Figure 18.	Typical current consumption in Stop mode with regulator in Run mode versus
	temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 19.	Typical current consumption in Stop mode with regulator in Low-power mode versus
	temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 20.	Typical current consumption in Standby mode versus temperature at
	VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
Figure 21.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 22.	Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 23.	Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
Figure 24.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
Figure 25.	Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
Figure 26.	Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
Figure 27.	5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
Figure 28.	5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
Figure 29.	I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
Figure 30.	Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
Figure 31.	I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
Figure 32.	SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
Figure 33.	SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
Figure 34.	SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 35.	USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . .	72
Figure 36.	ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	75
Figure 37.	Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76
Figure 38.	Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . .	76
Figure 39.	Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . .	77
Figure 40.	VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 79
Figure 41.	Recommended footprint (dimensions in mm)(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 79
Figure 42.	VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	80

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Figure 43. Recommended footprint (dimensions in mm)(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 44. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 45. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 82

Figure 46. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 83 Figure 47. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 48. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 84 Figure 49. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 50. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 85 Figure 51. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 86

Figure 52. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 87 Figure 53. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 54. LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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STM32F103x8, STM32F103xB	Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to

Section 2.2: Full compatibility throughout the family.

The medium-density STM32F103xx datasheet should be read in conjunction with the low-, mediumand high-density STM32F10xxx reference manual.

The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

2 Description

The STM32F103xx medium-density performance line family incorporates the highperformance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN.

The devices operate from a 2.0 to 3.6 V power supply. They are available in both the –40 to +85 °C temperature range and the –40 to +105 °C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F103xx medium-density performance line family includes devices in six different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the STM32F103xx medium-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.

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Description	STM32F103x8, STM32F103xB

2.1Device overview

Table 2.		STM32F103xx medium-density device features and peripheral counts
	Peripheral		STM32F103Tx				STM32F103Cx								STM32F103Rx											STM32F103Vx
Flash - Kbytes			64		128	64				128					64					128						64		128
SRAM - Kbytes				20					20										20								20
Timers	Advanced-control			1					1										1								1
	General-purpose			3					3										3								3
Communication	SPI			1					2										2								2
	I2C			1					2										2								2
	USART			2					3										3								3
	USB			1					1										1								1
	CAN			1					1										1								1
GPIOs				26					37										51								80
12-bit synchronized ADC				2					2										2								2
Number of channels			10 channels				10 channels									16 channels										16 channels
CPU frequency												72 MHz
Operating voltage											2.0 to 3.6 V
Operating temperatures			Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9)
			Junction temperature: –40 to + 125 °C (see Table 9)
Packages			VFQFPN36				LQFP48,										LQFP64,									LQFP100,
							VFQFPN48										TFBGA64									LFBGA100

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STM32F103x8, STM32F103xB	Description

Figure 1. STM32F103xx performance line block diagram

TRACECLK
TRACED[0:3]						TPIU
as AS
							Trace/trig
						SW/JTAG
NJTRST
JTDI						Cortex-M3 CPU
JTCK/SWCLK
JTMS/SWDIO
JTDO						Fmax : 7 2M Hz
as AF

			Trace
	pbu s
			Controlle r

								obl
		Ibu s							e
									Interfac
								flash
Dbus

		POWER
				VDD = 2 to 3.6V
		VOLT. REG.
Flash 128 KB		3.3V TO 1.8V		VSS
64 bit		@VDD

NRST

VDDA

VSSA

80AF

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

4 Channels

3 compl. Channels ETR and BKIN

MOSI,MISO,

SCK,NSS as AF

RX,TX, CTS, RTS,

Smart Card as AF

	S
NVIC		yst em

GP DMA

7 channels

@VDDA

SUPPLY

SUPERVISION

POR / PDR Rst

PVD		Int

EXTI

WAKEUP

GPIOA
GPIOB
GPIOC
GPIOD								MHz
GPIOE
		=48 / 72
								max
TIM1								F
								APB2 :
SPI1
USART1

		@VDDA
	16AF	12bit ADC1	IF
	VREF+
	VREF-	12bit ADC2	IF
		Temp sens or

AHB:F max=48/72 MHz

AHB2

APB2

SRAM 20 KB

PCLK1 PCLK2

HCLK

FCLK

RC 8 MHz

RC 40 kHz

@VDDA

AHB2

APB1

@VDD

PLL

&

OSC_IN

XTAL OSC

OSC_OUT

CLOCK

4-16 MHz

MANAGT

IWDG

Stand by

interface

VBAT

@VBAT

OSC32_IN

XTAL 32 kHz

OSC32_OUT

RTC

Back up

TAMPER-RTC

AWU

reg

Backu p interf ace

4 Channels

TIM2

4 Channels

TIM3

4 Channels

TIM 4

RX,TX, CTS, RTS,

USART2

CK, SmartCard as AF

RX,TX, CTS, RTS,

USART3

CK, SmartCard as AF

MOSI,MISO,SCK,NSS

SPI2

2x(8x16bit)

as AF

I2C1

SCL,SDA,SMBA

as AF

I2C2

SCL,SDA

as AF

bxCAN

USBDP/CAN_TX

USB 2.0 FS

USBDM/CAN_RX

SRAM 512B

W W D G

ai14390d

1.TA = –40 °C to +105 °C (junction temperature up to 125 °C).

2.AF = alternate function on I/O port pin.

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Description

STM32F103x8, STM32F103xB

Figure 2.

Clock tree

FLITFCLK

to Flash programming interface

8 MHz

HSI RC

HSI

USB

48 MHz

USBCLK

to USB interface

Prescaler

/2

/1, 1.5

HCLK

72 MHz max

to AHB bus, core,

Clock

memory and DMA

Enable (3

bits)

PLLSRC PLLMUL

SW

/8

to Cortex System timer

FCLK Cortex

free running clock

..., x16

HSI

SYSCLK

AHB

APB1

x2, x3, x4

Prescaler

Prescaler

36 MHz max

PCLK1

PLLCLK

72 MHz

to APB1

PLL

max

/1, 2..512

/1, 2, 4, 8, 16

peripherals

Peripheral

Clock

HSE

Enable (13 bits)

			TIM2,3, 4			to TIM2, 3
						and 4
	CSS		If (APB1 prescaler =1) x1			TIMXCLK
			else	x2	Peripheral Clock
					Enable (3 bits)
	PLLXTPRE		APB2	72 MHz max		PCLK2
			Prescaler
OSC_OUT						to APB2
			/1, 2, 4, 8, 16
						peripherals
4-16 MHz				Peripheral Clock
HSE OSC				Enable (11 bits)
OSC_IN	/2		TIM1 timer			to TIM1
			If (APB2 prescaler =1) x1
						TIM1CLK
	/128		else	x2 Peripheral Clock
			ADC		Enable (1 bit)
OSC32_IN		to RTC				to ADC
	LSE		Prescaler
LSE OSC				ADCCLK
32.768 kHz	RTCCLK		/2, 4, 6, 8
OSC32_OUT
	RTCSEL[1:0]

LSI RC

LSI

to Independent Watchdog (IWDG)

40 kHz

IWDGCLK

Legend:

HSE = high-speed external clock signal

Main

HSI = high-speed internal clock signal

/2

PLLCLK

LSI = low-speed internal clock signal

MCO

Clock Output

HSI

LSE = low-speed external clock signal

HSE

SYSCLK

MCO

ai14903

1.When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.

2.For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48 MHz.

3.To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.

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STM32F103x8, STM32F103xB	Description

2.2Full compatibility throughout the family

The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.

Lowand high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family.

The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices.

Table 3.

STM32F103xx family

Low-density devices

Medium-density devices

High-density devices

Pinout

16 KB

32 KB

64 KB

128 KB

256 KB

384 KB

512 KB

Flash

Flash(1)

Flash

Flash

Flash

Flash

Flash

6 KB RAM

10 KB RAM

20 KB RAM

20 KB RAM

48 KB RAM

64 KB RAM

64 KB RAM

144

5

× USARTs

4

× 16-bit timers, 2 × basic timers

100

3

× USARTs

3

× SPIs, 2 × I2Ss, 2 × I2Cs

2

× USARTs

USB, CAN, 2 × PWM timers

64

3

× 16-bit timers

3

× ADCs, 2 × DACs, 1 × SDIO

2

× 16-bit timers

2

× SPIs, 2 × I2Cs, USB,

FSMC (100 and 144 pins)

1

× SPI, 1 × I2C, USB,

CAN, 1 × PWM timer

48

CAN, 1 × PWM timer

2

× ADCs

2

× ADCs

36

1.For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices.

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2.3Overview

2.3.1ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2Embedded Flash memory

64 or 128 Kbytes of embedded Flash is available for storing programs and data.

2.3.3CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.3.4Embedded SRAM

Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.5Nested vectored interrupt controller (NVIC)

The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●Closely coupled NVIC gives low-latency interrupt processing

●Interrupt entry vector table address passed directly to the core

●Closely coupled NVIC core interface

●Allows early processing of interrupts

●Processing of late arriving higher priority interrupts

●Support for tail-chaining

●Processor state automatically saved

●Interrupt entry restored on interrupt exit with no instruction overhead

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STM32F103x8, STM32F103xB	Description

This hardware block provides flexible interrupt management features with minimal interrupt latency.

2.3.6External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.

2.3.7Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed APB domain is 36 MHz. See Figure 2 for details on the clock tree.

2.3.8Boot modes

At startup, boot pins are used to select one of three boot options:

●Boot from User Flash

●Boot from System Memory

●Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.

2.3.9Power supply schemes

●VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.

●VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.

●VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

For more details on how to connect power pins, refer to Figure 13: Power supply scheme.

2.3.10Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains

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Description	STM32F103x8, STM32F103xB

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher

than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.

2.3.11Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●MR is used in the nominal regulation mode (Run)

●LPR is used in the Stop mode

●Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.

2.3.12Low-power modes

The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

●Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

●Stop mode

The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.

●Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
	or Standby mode.

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STM32F103x8, STM32F103xB	Description

2.3.13DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and advanced-control timers TIMx and ADC.

2.3.14RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.15Timers and watchdogs

The medium-density STM32F103xx performance line devices include an advanced-control timer, three general-purpose timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the advanced-control and general-purpose timers.

Table 4.		Timer feature comparison
Timer		Counter	Counter	Prescaler	DMA request	Capture/compare	Complementary
		resolution	type	factor	generation	channels	outputs
			Up,	Any integer
TIM1		16-bit	down,	between 1	Yes	4	Yes
			up/down	and 65536
TIM2,			Up,	Any integer
TIM3,		16-bit	down,	between 1	Yes	4	No
TIM4			up/down	and 65536

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Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for

●Input capture

●Output compare

●PWM generation (edgeor center-aligned modes)

●One-pulse mode output

If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to three synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardwareor software-configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

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STM32F103x8, STM32F103xB	Description

SysTick timer

This timer is dedicated for OS, but could also be used as a standard downcounter. It features:

●A 24-bit downcounter

●Autoreload capability

●Maskable system interrupt generation when the counter reaches 0

●Programmable clock source

2.3.16I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

2.3.17Universal synchronous/asynchronous receiver transmitter (USART)

One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability.

All USART interfaces can be served by the DMA controller.

2.3.18Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

2.3.19Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.

2.3.20Universal serial bus (USB)

The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).

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2.3.21GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current- capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

2.3.22ADC (analog-to-digital converter)

Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

●Simultaneous sample and hold

●Interleaved sample and hold

●Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers.

2.3.23Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value.

2.3.24Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

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3 Pinouts and pin description

Figure 3. STM32F103xx performance line LFBGA100 ballout

		1	2	3	4	5	6	7	8	9	10
	A	PC14-	PC13-	PE2	PB9	PB7	PB4	PB3	PA15	PA14	PA13
		OSC32_INTAMPER-RTC
	B	PC15-		PE3	PB8	PB6	PD5	PD2	PC11
		OSC32_OUT VBAT								PC10	PA12
	C	OSC_IN	VSS_5	PE4	PE1	PB5	PD6	PD3	PC12	PA9	PA11
	D	OSC_OUT VDD_5		PE5	PE0	BOOT0	PD7	PD4	PD0	PA8	PA10
	E	NRST	PC2	PE6	VSS_4	VSS_3	VSS_2	VSS_1	PD1	PC9	PC7
	F	PC0	PC1	PC3	VDD_4	VDD_3	VDD_2	VDD_1	NC	PC8	PC6
	G	VSSA	PA0-WKUP	PA4	PC4	PB2	PE10	PE14	PB15	PD11	PD15
	H	VREF–	PA1	PA5	PC5	PE7	PE11	PE15	PB14	PD10	PD14
	J	VREF+	PA2	PA6	PB0	PE8	PE12	PB10	PB13	PD9	PD13
	K	VDDA	PA3	PA7	PB1	PE9	PE13	PB11	PB12	PD8	PD12

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Pinouts and pin description																			STM32F103x8, STM32F103xB
	Figure 4. STM32F103xx performance line LQFP100 pinout
		VDD 3	VSS 3	PE1	PE0	PB9	PB8	BOOT0	PB7	PB6	PB5	PB4	PB3	PD7	PD6	PD5	PD4	PD3	PD2	PD1	PD0	PC12	PC11	PC10	PA15	PA14
	PE2	100	99	98	97	96	95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	80	79	78	77	76
		1																								75	VDD_2
	PE3	2																								74	VSS_2
	PE4	3																								73	NC
	PE5	4																								72	PA 13
	PE6	5																								71	PA 12
	VBAT	6																								70	PA 11
	PC13-TAMPER-RTC 7																									69	PA 10
	PC14-OSC32_IN	8																								68	PA 9
	PC15-OSC32_OUT	9																								67	PA 8
	VSS_5	10																								66	PC9
	VDD_5	11																								65	PC8
	OSC_IN	12										LQFP100														64	PC7
	OSC_OUT	13																								63	PC6
	NRST	14																								62	PD15
	PC0	15																								61	PD14
	PC1	16																								60	PD13
	PC2	17																								59	PD12
	PC3	18																								58	PD11
	VSSA	19																								57	PD10
	VREF-	20																								56	PD9
	VREF+	21																								55	PD8
	VDDA	22																								54	PB15
	PA0-WKUP	23																								53	PB14
	PA1	24																								52	PB13
	PA2	25																								51	PB12
		26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50
		PA3	VSS 4	VDD 4	PA4	PA5	PA6	PA7	PC4	PC5	PB0	PB1	PB2	PE7	PE8	PE9	PE10	PE11	PE12	PE13	PE14	PE15	PB10	PB11	VSS 1	VDD 1
																											ai14391

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STM32F103x8, STM32F103xB

Pinouts and pin description

Figure 5. STM32F103xx performance line LQFP64 pinout

VDD 3

VSS 3

PB9

PB8

BOOT0

PB7

PB6 PB5 PB4 PB3

PD2

PC12

PC11

PC10

PA15

PA14

VBAT

VDD_2

PC13-TAMPER-RTC

VSS_2

PC14-OSC32_IN

PA13

PC15-OSC32_OUT

PA12

PD0 OSC_IN

PA11

PD1 OSC_OUT

PA10

NRST

PA9

PC0

LQFP64

PA8

PC1

PC9

PC2

PC8

PC3

PC7

VSSA

PC6

VDDA

PB15

PA0-WKUP

PB14

PA1

PB13

PA2

PB12

PA3

VSS 4

VDD 4

PA4

PA5

PA6

PA7 PC4 PC5 PB0

PB1

PB2

PB10

PB11

VSS 1

VDD 1

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	Pinouts and pin description						STM32F103x8, STM32F103xB
	Figure 6. STM32F103xx performance line TFBGA64 ballout
		1	2	3	4	5	6	7	8
	A	PC14-	PC13-	PB9	PB4	PB3	PA15	PA14	PA13
		OSC32_INTAMPER-RTC
	B	PC15-	VBAT	PB8	BOOT0	PD2	PC11	PC10	PA12
		OSC32_OUT
	C	OSC_IN	VSS_4	PB7	PB5	PC12	PA10	PA9	PA11
	D	OSC_OUT VDD_4		PB6	VSS_3	VSS_2	VSS_1	PA8	PC9
	E	NRST	PC1	PC0	VDD_3	VDD_2	VDD_1	PC7	PC8
	F	VSSA	PC2	PA2	PA5	PB0	PC6	PB15	PB14
	G	VREF+ PA0-WKUP		PA3	PA6	PB1	PB2	PB10	PB13
	H	VDDA	PA1	PA4	PA7	PC4	PC5	PB11	PB12
									AI15494

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STM32F103x8, STM32F103xB						Pinouts and pin description
	Figure 7. STM32F103xx performance line LQFP48 pinout
		VDD 3	VSS 3	PB9 PB8	BOOT0 PB7 PB6 PB5 PB4 PB3 PA15	PA14
	VBAT	48 47 46 45			44 43 42 41 40 39 38 37		VDD_2
		1				36
	PC13-TAMPER-RTC	2				35	VSS_2
	PC14-OSC32_IN	3				34	PA13
	PC15-OSC32_OUT	4				33	PA12
	PD0-OSC_IN	5				32	PA11
	PD1-OSC_OUT	6			LQFP48	31	PA10
	NRST	7				30	PA9
	VSSA	8				29	PA8
	VDDA	9				28	PB15
	PA0-WKUP	10				27	PB14
	PA1	11				26	PB13
	PA2	12				25	PB12
		13 14 15 16 17 18 19 20 21 22 23 24
		PA3	PA4	PA5 PA6	PA7 PB0 PB1 PB2 PB10 PB11 VSS 1	VDD 1
							ai14393b

Figure 8. STM32F103xx performance line VFQFPN48 pinout

	VDD_3	VSS_3	PB9	PB8 BOOT0 PB7 PB6 PB5	PB4	PB3 PA15	PA14
VBAT	48 47 46 45 44 43 42 41 40 39 38 37							VDD_2
	1						36
PC13-TAMPER-RTC	2						35	VSS_2
PC14-OSC32_IN	3						34	PA13
PC15-OSC32_OUT	4						33	PA12
PD0-OSC_IN	5						32	PA11
PD1-OSC_OUT	6			VFQFPN48			31	PA10
	7						30	PA9
NRST
VSSA	8						29	PA8
VDDA	9						28	PB15
							27
PA0-WKUP	10							PB14
							26
PA1	11							PB13
	12						25
PA2								PB12
	13 14 15 16 17 18 19 20 21 22 23 24
	PA3	PA4	PA5	PA6 PA7 PB0 PB1 PB2	PB10	PB11 VSS_1	VDD_1
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Pinouts and pin description								STM32F103x8, STM32F103xB
Figure 9. STM32F103xx performance line VFQFPN36 pinout
	V	BOOT0	PB7	PB6	PB5	PB4	PB3	PA15	PA14
	SS3
	36	35	34	33	32	31	30	29	28
VDD_3	1								27	VDD_2
OSC_IN/PD0	2								26	VSS_2
OSC_OUT/PD1	3								25	PA13
NRST	4								24	PA12
VSSA	5				QFN36				23	PA11
VDDA	6								22	PA10
PA0-WKUP	7								21	PA9
PA1	8								20	PA8
PA2	9								19	VDD_1
	10	11	12	13	14	15	16	17	18
	PA3	PA4	PA5	PA6	PA7	PB0	PB1	PB2	SS 1
									V
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Table 5.		Medium-density STM32F103xx pin definitions
		Pins								Alternate functions(4)
							Type	O/I Level
LFBGA100	LQFP48/VFQFPN48	TFBGA64	LQFP64	LQFP100	VFQFPN36
							(1)	(2)	Main
						Pin name			function(3)	Default	Remap
									(after reset)
A3	-		-	1	-	PE2	I/O	FT	PE2	TRACECK
B3	-		-	2	-	PE3	I/O	FT	PE3	TRACED0
C3	-		-	3	-	PE4	I/O	FT	PE4	TRACED1
D3	-		-	4	-	PE5	I/O	FT	PE5	TRACED2
E3	-		-	5	-	PE6	I/O	FT	PE6	TRACED3
B2	1	B2	1	6	-	VBAT	S		VBAT
A2	2	A2	2	7	-	PC13-TAMPER-	I/O		PC13(6)	TAMPER-RTC
						RTC(5)
A1	3	A1	3	8	-	PC14-OSC32_IN(5)	I/O		PC14(6)	OSC32_IN
B1	4	B1	4	9	-	PC15-	I/O		PC15(6)	OSC32_OUT
						OSC32_OUT(5)
C2	-	-	-	10	-	VSS_5	S		VSS_5
D2	-	-	-	11	-	VDD_5	S		VDD_5
C1	5	C1	5	12	2	OSC_IN	I		OSC_IN
D1	6	D1	6	13	3	OSC_OUT	O		OSC_OUT
E1	7	E1	7	14	4	NRST	I/O		NRST
F1	-	E3	8	15	-	PC0	I/O		PC0	ADC12_IN10
F2	-	E2	9	16	-	PC1	I/O		PC1	ADC12_IN11
E2	-	F2	10	17	-	PC2	I/O		PC2	ADC12_IN12
F3	-	-(7)	11	18	-	PC3	I/O		PC3	ADC12_IN13
G1	8	F1	12	19	5	VSSA	S		VSSA
H1	-	-	-	20	-	VREF-	S		VREF-
J1	-	G1(7)	-	21	-	VREF+	S		VREF+
K1	9	H1	13	22	6	VDDA	S		VDDA
										WKUP/
G2	10	G2	14	23	7	PA0-WKUP	I/O		PA0	USART2_CTS(8)/
										ADC12_IN0/
										TIM2_CH1_ETR(8)
										USART2_RTS(8)/
H2	11	H2	15	24	8	PA1	I/O		PA1	ADC12_IN1/
										TIM2_CH2(8)

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Pinouts and pin description

STM32F103x8, STM32F103xB

Table 5.

Medium-density STM32F103xx pin definitions (continued)

Pins

Alternate functions(4)

Type

O/I Level

LFBGA100

LQFP48/VFQFPN48

TFBGA64

LQFP64

LQFP100

VFQFPN36

(1)

(2)

Main

Pin name

function(3)

Default

Remap

(after reset)

USART2_TX(8)/

J2

12

F3

16

25

9

PA2

I/O

PA2

ADC12_IN2/

TIM2_CH3(8)

USART2_RX(8)/

K2

13

G3

17

26

10

PA3

I/O

PA3

ADC12_IN3/

TIM2_CH4(8)

E4

-

C2

18

27

-

VSS_4

S

VSS_4

F4

-

D2

19

28

-

VDD_4

S

VDD_4

SPI1_NSS(8)/

G3

14

H3

20

29

11

PA4

I/O

PA4

USART2_CK(8)/

ADC12_IN4

H3

15

F4

21

30

12

PA5

I/O

PA5

SPI1_SCK(8)/

ADC12_IN5

SPI1_MISO(8)/

J3

16

G4

22

31

13

PA6

I/O

PA6

ADC12_IN6/

TIM1_BKIN

TIM3_CH1(8)

SPI1_MOSI(8)/

K3

17

H4

23

32

14

PA7

I/O

PA7

ADC12_IN7/

TIM1_CH1N

TIM3_CH2(8)

G4

-

H5

24

33

PC4

I/O

PC4

ADC12_IN14

H4

-

H6

25

34

PC5

I/O

PC5

ADC12_IN15

J4

18

F5

26

35

15

PB0

I/O

PB0

ADC12_IN8/

TIM1_CH2N

TIM3_CH3(8)

K4

19

G5

27

36

16

PB1

I/O

PB1

ADC12_IN9/

TIM1_CH3N

TIM3_CH4(8)

G5

20

G6

28

37

17

PB2

I/O

FT

PB2/BOOT1

H5

-

-

-

38

-

PE7

I/O

FT

PE7

TIM1_ETR

J5

-

-

-

39

-

PE8

I/O

FT

PE8

TIM1_CH1N

K5

-

-

-

40

-

PE9

I/O

FT

PE9

TIM1_CH1

G6

-

-

-

41

-

PE10

I/O

FT

PE10

TIM1_CH2N

H6

-

-

-

42

-

PE11

I/O

FT

PE11

TIM1_CH2

J6

-

-

-

43

-

PE12

I/O

FT

PE12

TIM1_CH3N

K6

-

-

-

44

-

PE13

I/O

FT

PE13

TIM1_CH3

G7

-

-

-

45

-

PE14

I/O

FT

PE14

TIM1_CH4

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Pinouts and pin description

Table 5.

Medium-density STM32F103xx pin definitions (continued)

Pins

Alternate functions(4)

Type

O/I Level

LFBGA100

LQFP48/VFQFPN48

TFBGA64

LQFP64

LQFP100

VFQFPN36

(1)

(2)

Main

Pin name

function(3)

Default

Remap

(after reset)

H7

-

-

-

46

-

PE15

I/O

FT

PE15

TIM1_BKIN

J7

21

G7

29

47

-

PB10

I/O

FT

PB10

I2C2_SCL/

TIM2_CH3

USART3_TX(8)

K7

22

H7

30

48

-

PB11

I/O

FT

PB11

I2C2_SDA/

TIM2_CH4

USART3_RX(8)

E7

23

D6

31

49

18

VSS_1

S

VSS_1

F7

24

E6

32

50

19

VDD_1

S

VDD_1

SPI2_NSS/

K8

25

H8

33

51

-

PB12

I/O

FT

PB12

I2C2_SMBAl/

USART3_CK(8)/

TIM1_BKIN(8)

SPI2_SCK/

J8

26

G8

34

52

-

PB13

I/O

FT

PB13

USART3_CTS(8)/

TIM1_CH1N (8)

SPI2_MISO/

H8

27

F8

35

53

-

PB14

I/O

FT

PB14

USART3_RTS(8)

TIM1_CH2N (8)

G8

28

F7

36

54

-

PB15

I/O

FT

PB15

SPI2_MOSI/

TIM1_CH3N(8)

K9

-

-

-

55

-

PD8

I/O

FT

PD8

USART3_TX

J9

-

-

-

56

-

PD9

I/O

FT

PD9

USART3_RX

H9

-

-

-

57

-

PD10

I/O

FT

PD10

USART3_CK

G9

-

-

-

58

-

PD11

I/O

FT

PD11

USART3_CTS

K10

-

-

-

59

-

PD12

I/O

FT

PD12

TIM4_CH1 /

USART3_RTS

J10

-

-

-

60

-

PD13

I/O

FT

PD13

TIM4_CH2

H10

-

-

-

61

-

PD14

I/O

FT

PD14

TIM4_CH3

G10

-

-

-

62

-

PD15

I/O

FT

PD15

TIM4_CH4

F10

-

F6

37

63

-

PC6

I/O

FT

PC6

TIM3_CH1

E10

E7

38

64

-

PC7

I/O

FT

PC7

TIM3_CH2

F9

E8

39

65

-

PC8

I/O

FT

PC8

TIM3_CH3

E9

-

D8

40

66

-

PC9

I/O

FT

PC9

TIM3_CH4

D9

29

D7

41

67

20

PA8

I/O

FT

PA8

USART1_CK/

TIM1_CH1(8)/MCO

Doc ID 13587 Rev 13

29/99

Pinouts and pin description

STM32F103x8, STM32F103xB

Table 5.

Medium-density STM32F103xx pin definitions (continued)

Pins

Alternate functions(4)

Type

O/I Level

LFBGA100

LQFP48/VFQFPN48

TFBGA64

LQFP64

LQFP100

VFQFPN36

(1)

(2)

Main

Pin name

function(3)

Default

Remap

(after reset)

C9

30

C7

42

68

21

PA9

I/O

FT

PA9

USART1_TX(8)/

TIM1_CH2(8)

D10

31

C6

43

69

22

PA10

I/O

FT

PA10

USART1_RX(8)/

TIM1_CH3(8)

USART1_CTS/

C10

32

C8

44

70

23

PA11

I/O

FT

PA11

CANRX(8)/ USBDM

TIM1_CH4(8)

USART1_RTS/

B10

33

B8

45

71

24

PA12

I/O

FT

PA12

CANTX(8) //USBDP

TIM1_ETR(8)

A10

34

A8

46

72

25

PA13

I/O

FT

JTMS/SWDIO

PA13

F8

-

-

-

73

-

Not connected

E6

35

D5

47

74

26

VSS_2

S

VSS_2

F6

36

E5

48

75

27

VDD_2

S

VDD_2

A9

37

A7

49

76

28

PA14

I/O

FT

JTCK/SWCLK

PA14

A8

38

A6

50

77

29

PA15

I/O

FT

JTDI

TIM2_CH1_ETR/

PA15 /SPI1_NSS

B9

-

B7

51

78

PC10

I/O

FT

PC10

USART3_TX

B8

-

B6

52

79

PC11

I/O

FT

PC11

USART3_RX

C8

-

C5

53

80

PC12

I/O

FT

PC12

USART3_CK

D8

5

C1

5

81

2

PD0

I/O

FT

OSC_IN(9)

CANRX

E8

6

D1

6

82

3

PD1

I/O

FT

OSC_OUT(9)

CANTX

B7

B5

54

83

-

PD2

I/O

FT

PD2

TIM3_ETR

C7

-

-

-

84

-

PD3

I/O

FT

PD3

USART2_CTS

D7

-

-

-

85

-

PD4

I/O

FT

PD4

USART2_RTS

B6

-

-

-

86

-

PD5

I/O

FT

PD5

USART2_TX

C6

-

-

-

87

-

PD6

I/O

FT

PD6

USART2_RX

D6

-

-

-

88

-

PD7

I/O

FT

PD7

USART2_CK

TIM2_CH2 / PB3

A7

39

A5

55

89

30

PB3

I/O

FT

JTDO

TRACESWO

SPI1_SCK

A6

40

A4

56

90

31

PB4

I/O

FT

JNTRST

TIM3_CH1/ PB4/

SPI1_MISO

30/99

Doc ID 13587 Rev 13