ST STM32F101C8, STM32F101R8, STM32F101V8, STM32F101T8, STM32F101RB User Manual
...
Medium-density access line, ARM-based 32-bit MCU with 64 or
LQFP48
7 x 7 mm
LQFP100
14 x 14 mm
LQFP64
10 x 10 mm
VFQFPN36
6 × 6 mm
VFQFPN48
7 × 7 mm
128 KB Flash, 6 timers, ADC and 7 communication interfaces
Features
■ Core: ARM 32-bit Cortex™-M3
– 36 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
■ Memories
– 64 to 128 Kbytes of Flash memory
– 10 to 16 Kbytes of SRAM
■ Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
■ Low power
– Sleep, Stop and Standby modes
–V
■ Debug mode
– Serial wire debug (SWD) and JTAG
■ DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
■ 1 × 12-bit, 1 µs A/D converter (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
■ Up to 80 fast I/O ports
– 26/37/51/80 I/Os, all mappable on 16
supply for RTC and backup registers
BAT
interfaces
2
I
Cs and USARTs
external interrupt vectors and almost all
5 V-tolerant
CPU
STM32F101x8
STM32F101xB
■ Six timers
– Three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 2 watchdog timers (Independent and
Window)
– SysTick timer: 24-bit downcounter
■ Up to 7 communication interfaces
– Up to 2 x I
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
■ CRC calculation unit, 96-bit unique ID
■ ECOPACK
Table 1. Device summary
Reference Part number
STM32F101x8
STM32F101xB
2
C interfaces (SMBus/PMBus)
®
packages
STM32F101C8,
STM32F101R8
STM32F101V8,
STM32F101T8
STM32F101RB,
STM32F101VB,
STM32F101CB
STM32F101TB
April 2011 Doc ID 13586 Rev 14 1/87
www.st.com
1
Contents STM32F101x8, STM32F101xB
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15
2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15
2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.18 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.19 I
²
C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.23 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Contents
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 33
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 52
5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2.2 Evaluating the maximum junction temperature for an application . . . . . 78
Doc ID 13586 Rev 14 3/87
Contents STM32F101x8, STM32F101xB
7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Device features and peripheral counts (STM32F101xx medium-density
access line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Medium-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Maximum current consumption in Sleep mode, code running from Flash
or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 38
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 42
Table 18. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 20. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 22. LSE oscillator characteristics (f
Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 26. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 27. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 29. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 30. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 31. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 32. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 33. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 35. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 36. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 37. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 38. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 39. I
Table 40. SCL frequency (f
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PCLK1
Table 41. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 42. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 43. R
max for f
AIN
= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
ADC
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LSE
Doc ID 13586 Rev 14 5/87
List of tables STM32F101x8, STM32F101xB
Table 44. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 45. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 46. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 47. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 72
Table 48. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 73
Table 49. LQPF100 – 14 x14 mm, 100-pin low-profile quad flat package mechanical data. . . . . . . . 74
Table 50. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 75
Table 51. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 76
Table 52. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 53. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB List of figures
List of figures
Figure 1. STM32F101xx medium-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32F101xx medium-density access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. STM32F101xx medium-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. STM32F101xx medium-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. STM32F101xx medium-density access line VFQPFN48 pinout . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. STM32F101xx medium-density access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 37
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 37
Figure 15. Typical current consumption on V
V
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
BAT
Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at V
= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DD
Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at V
= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DD
Figure 18. Typical current consumption in Standby mode versus temperature at V
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 20. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 23. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 24. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 27. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 29. I
2
C bus AC waveforms and measurement circuit
Figure 30. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 31. SPI timing diagram - slave mode and CPHA = 1
Figure 32. SPI timing diagram - master mode
Figure 33. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 35. Power supply and reference decoupling (V
Figure 36. Power supply and reference decoupling (V
Figure 37. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline
Figure 38. Recommended footprint (dimensions in mm)
Figure 39. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline
Figure 40. Recommended footprint (dimensions in mm)
Figure 41. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 74
Figure 42. Recommended footprint
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
with RTC on versus temperature at different
BAT
= 3.3 V and
DD
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
REF+
REF+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
not connected to V
connected to V
(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DDA
). . . . . . . . . . . . . . 69
DDA
). . . . . . . . . . . . . . . . . 70
Doc ID 13586 Rev 14 7/87
List of figures STM32F101x8, STM32F101xB
Figure 43. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 75
Figure 44. Recommended footprint
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 45. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 46. Recommended footprint
Figure 47. LQFP64 P
max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
D
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F101x8 and STM32F101xB medium-density access line microcontrollers. For
more details on the whole STMicroelectronics STM32F101xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The medium-density STM32F101xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
Doc ID 13586 Rev 14 9/87
Description STM32F101x8, STM32F101xB
2 Description
The STM32F101xB and STM32F101x8 medium-density access line family incorporates the
high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency,
high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 16
Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB
buses. All devices offer standard communication interfaces (two I
three USARTs), one 12-bit ADC and three general-purpose 16-bit timers.
The STM32F101xx medium-density access line family operates in the –40 to +85 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F101xx medium-density access line family includes devices in four different
packages ranging from 36 pins to 100 pins. Depending on the device chosen, different sets
of peripherals are included, the description below gives an overview of the complete range
of peripherals proposed in this family.
These features make the STM32F101xx medium-density access line microcontroller family
suitable for a wide range of applications such as application control and user interface,
medical and handheld equipment, PC peripherals, gaming and GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, Video intercoms, and
HVACs.
2
Cs, two SPIs, and up to
10/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Description
2.1 Device overview
Figure 1 shows the general block diagram of the device family.
Table 2. Device features and peripheral counts (STM32F101xx medium-density
access line)
Peripheral
Flash - Kbytes 64 128 64 128 64 128 64 128
SRAM - Kbytes 10 16 10 16 10 16 10 16
General -purpose 33 3 3
Timers
SPI 12 2 2
2
I
C 12 2 2
USART 23 3 3
Communication
12-bit synchronized ADC
number of channels
STM32F101Tx STM32F101Cx STM32F101Rx STM32F101Vx
1
10 channels
1
10 channels
1
16 channels
1
16 channels
GPIOs 26 37 51 80
CPU frequency 36 MHz
Operating voltage 2.0 to 3.6 V
Operating temperatures
Packages VFQFPN36
Ambient temperature: –40 to +85 °C (see Ta b le 8 )
Junction temperature: –40 to +105 °C (see Ta b le 8 )
LQFP48,
VFQFPN48
LQFP64 LQFP100
Doc ID 13586 Rev 14 11/87
Description STM32F101x8, STM32F101xB
Temp sen sor
PA[15: 0]
EXTI
W W D G
NVIC
12bit A DC1
SWD
16AF
JTDI
JTCK/ SWCLK
JTMS/SWDIO
JNTRST
JTDO
NRST
V
DD
= 2 to 3.6V
80AF
PB[15: 0]
PC[15:0 ]
AHB2
MOSI,MISO,SCK,NSS
SRAM
2x(8x16bit )
WAKEUP
GPIOA
GPIOB
GPIOC
F
max
: 36 MHz
V
SS
SCL,SDA
I2C2
V
REF+
GP DMA
TIM2
TIM3
XTAL OSC
4-16 MHz
XTAL 32 k Hz
OSC_IN
OSC_OUT
OSC32_OUT
OSC32_IN
PLL &
APB1 : F
max
=24 / 36 MHz
PCLK1
HCLK
CLOCK
MANAG T
PCLK 2
as AF
as AF
VOLT. REG.
3.3V TO 1.8V
POWER
Backu p in terface
as AF
16 KB
RTC
RC 8 MHz
Cortex M3 CPU
USART1
USART2
SPI2
7 chan nels
Back up
reg
SCL,SDA ,SMBAL
I2C1
as AF
RX,TX, CTS, RTS,
USART3
V
REF-
PD[15: 0]
GPIOD
AHB: F
max
=36 MHz
4 Chann els
4 Chann els
FCLK
RC 42 kHz
Stand by
IWDG
@VDD
@VBAT
POR / PDR
SUPPLY
@VDDA
VDDA
VSSA
@VDDA
V
BAT
CK, SmartCard as AF
RX,TX, CTS, RTS,
Smart Card as AF
RX,TX, CTS, RTS,
APB2 : F
max
= 36 MHz
NVIC
SPI1
MOSI,MISO,
SCK,NSS as AF
IF
int erface
@VDDA
SUPERVISION
PVD
Rst
Int
@VDD
AHB2
APB2
APB1
AWU
TAMPER-RTC
PE[15:0]
GPIOE
Flash 128 KB
BusM atrix
64 bit
Interfac e
Ibus
Dbus
pbus
obl
Flash
Trac e
Cont roll er
Syst em
TIM4
4 Channe ls
ai14385B
TRACECLK
TRACED[0:3]
as AS
SW/JTAG
TPIU
Trace/trig
CK, SmartCard as AF
Figure 1. STM32F101xx medium-density access line block diagram
12/87 Doc ID 13586 Rev 14
1. AF = alternate function on I/O port pin.
= –40 °C to +85 °C (junction temperature up to 105 °C).
2. T
A
STM32F101x8, STM32F101xB Description
Figure 2. Clock tree
FLITFCLK
to Flash programming interface
36 MHz max
/8
AHB
Prescaler
/1, 2..512
Prescaler
/1, 2, 4, 8, 16
TIM2,3, 4
If (APB1 prescaler =1) x1
else x2
Prescaler
/1, 2, 4, 8, 16
HCLK
to AHB bus, core,
Clock
Enable (3 bits)
APB1
APB2
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
memory and DMA
to Cortex System timer
FCLK Cortex
free running clock
36 MHz max
Peripheral Clock
Enable (13 bits)
36 MHz max
Peripheral Clock
Enable (11 bits)
ADC
Prescaler
/2, 4, 6, 8
PCLK1
to APB1
peripherals
to TIM2, 3
and 4
TIMXCLK
eripheral Clock
P
Enable (3 bits)
PCLK2
to APB2
peripherals
ADCCLK
to ADC
ai15104
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
MCO
8 MHz
HSI RC
PLLSRC
4-16 MHz
HSE OSC
LSE OSC
32.768 kHz
LSI RC
40 kHz
Main
Clock Output
HSI
PLLMUL
..., x16
x2, x3, x4
PLL
PLLXTPRE
/2
MCO
/2
/128
LSE
RTCSEL[1:0]
LSI
/2
PLLCLK
HSE
SYSCLK
SW
HSI
HSE
SYSCLK
36 MHz
max
PLLCLK
CSS
RTCCLK
to RTC
to Independent Watchdog (IWDG)
IWDGCLK
HSI
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
Doc ID 13586 Rev 14 13/87
Description STM32F101x8, STM32F101xB
2.2 Full compatibility throughout the family
The STM32F101xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are
referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as
medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are
referred to as high-density devices.
Low- and high-density devices are an extension of the STM32F101x8/B devices, they are
specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities and a timer less. Highdensity devices have higher Flash memory and RAM capacities, and additional peripherals
like FSMC and DAC, while remaining fully compatible with the other members of the
STM32F101xx family.
The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE
are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the
user to try different memory densities and providing a greater degree of freedom during the
development cycle.
Moreover, the STM32F101xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3. STM32F101xx family
Memory size
Low-density devices Medium-density devices High-density devices
Pinout
16 KB
Flash
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM
144
100
64
2 × USARTs
2 × 16-bit timers
48
1 × SPI, 1 × I2C
1 × ADC
36
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.
32 KB
Flash
(1)
64 KB
Flash
3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs,
1 × ADC
128 KB
Flash
256 KB
Flash
32 KB
RAM
384 KB
Flash
48 KB
RAM
512 KB
Flash
48 KB
RAM
5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I
2
Cs, 1 × ADC,
2 × DACs, FSMC (100 and 144 pins)
14/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Description
2.3 Overview
2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xx medium-density access line family having an embedded ARM core, is
therefore compatible with all ARM tools and software.
2.3.2 Embedded Flash memory
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
2.3.3 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.3.4 Embedded SRAM
Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.3.5 Nested vectored interrupt controller (NVIC)
The STM32F101xx medium-density access line embeds a nested vectored interrupt
controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.
● Closely coupled NVIC gives low latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Closely coupled NVIC core interface
● Allows early processing of interrupts
● Processing of late arriving higher priority interrupts
● Support for tail-chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
Doc ID 13586 Rev 14 15/87
Description STM32F101x8, STM32F101xB
2.3.6 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
2.3.7 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See Figure 2 for details on the clock tree.
2.3.8 Boot modes
At startup, boot pins are used to select one of three boot options:
● Boot from User Flash
● Boot from System Memory
● Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.3.9 Power supply schemes
● V
● V
● V
For more details on how to connect power pins, refer to Figure 11: Power supply scheme.
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
DD
Provided externally through V
, V
SSA
= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
DDA
and PLL (minimum voltage to be applied to V
V
and V
DDA
BAT
SSA
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V
2.3.10 Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
pins.
DD
must be connected to V
is below a specified threshold, V
DD
DD
DD
is 2.4 V when the ADC is used).
DDA
and VSS, respectively.
is not present.
POR/PDR
, without the need for an
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD/VDDA
generated when V
16/87 Doc ID 13586 Rev 14
power supply and compares it to the V
DD/VDDA
drops below the V
PVD
threshold. An interrupt can be
PVD
threshold and/or when VDD/V
DDA
is higher
STM32F101x8, STM32F101xB Description
than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 10: Embedded reset and power control block characteristics for the values of
V
POR/PDR
and V
PVD
.
2.3.11 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
● MR is used in the nominal regulation mode (Run)
● LPR is used in the Stop mode
● Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.3.12 Low-power modes
The STM32F101xx medium-density access line supports three low-power modes to achieve
the best compromise between low power consumption, short startup time and available
wakeup sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
● Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.3.13 DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Doc ID 13586 Rev 14 17/87
Description STM32F101x8, STM32F101xB
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I
2
C, USART, general purpose timers
TIMx and ADC.
2.3.14 RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
supply when present or through the V
DD
registers used to store 20 bytes of user application data when V
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
pin. The backup registers are ten 16-bit
BAT
power is not present.
DD
2.3.15 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
2.3.16 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
2.3.17 SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source
2.3.18 General-purpose timers (TIMx)
There are three synchronizable general-purpose timers embedded in the STM32F101xx
medium-density access line devices. These timers are based on a 16-bit auto-reload
up/down counter, a 16-bit prescaler and feature 4 independent channels each for input
18/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Description
capture, output compare, PWM or one pulse mode output. This gives up to 12 input
captures / output compares / PWMs on the largest packages.
The general-purpose timers can work together via the Timer Link feature for synchronization
or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs. They all have independent DMA request
generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
2.3.19 I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
2.3.20 Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
2.3.21 Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
2.3.22 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.3.23 ADC (analog to digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
Doc ID 13586 Rev 14 19/87
Description STM32F101x8, STM32F101xB
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
2.3.24 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
< 3.6 V. The temperature sensor is internally
DDA
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.3.25 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
20/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Pinouts and pin description
100999897969594939291908988878685848382818079787776
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
PE3
PE4
PE5
PE6
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA 0- W K UP
PA 1
PA 2
VDD_2
VSS_2
NC
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA 3
VSS_4
VDD_4
PA 4
PA 5
PA 6
PA 7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
26272829303132333435363738394041424344454647484950
ai14386b
LQFP100
PC13-TAMPER-RTC
3 Pinouts and pin description
Figure 3. STM32F101xx medium-density access line LQFP100 pinout
Doc ID 13586 Rev 14 21/87
Pinouts and pin description STM32F101x8, STM32F101xB
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA 0- W K UP
PA 1
PA 2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA 1 5
PA 14
VDD_2
VSS_2
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA 3
VSS_4
VDD_4
PA 4
PA 5
PA 6
PA 7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
LQFP64
ai14387b
PC13-TAMPER-RTC
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18
19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
LQFP48
PA 3
PA 4
PA 5
PA 6
PA 7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VDD_2
VSS_2
PA1 3
PA1 2
PA1 1
PA1 0
PA9
PA8
PB15
PB14
PB13
PB12
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
VSSA
VDDA
PA 0- W K UP
PA 1
PA 2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA 1 5
PA 14
ai14378d
PC13-TAMPER-RTC
Figure 4. STM32F101xx medium-density access line LQFP64 pinout
Figure 5. STM32F101xx medium-density access line LQFP48 pinout
22/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Pinouts and pin description
ai18300
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
PA 3
PA 4
PA 5
PA 6
PA 7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA 1
PA 2
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA 9
PA 8
PB15
PB14
PB13
PB12
48
VFQFPN48
47 46
45 444342 41
40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
13
14 15
16 171819 20
21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
V
SS_3
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
36 35 34 33 32 31 30 29 28
V
DD_3
1
27
V
DD_2
OSC_IN/PD0
2
26
V
SS_2
OSC_OUT/PD1
3
25
PA13
NRST
4
QFN36
24
PA12
V
SSA
5
23 PA11
V
DDA
6
22
PA10
PA0-WKUP
7
21
PA 9
PA 1
8
20
PA 8
PA 2 9
19
V
DD_1
10 11 12 13 14 15 16 17 18
PA 3
PA 4
PA 5
PA 6
PA 7
PB0
PB1
PB2
V
SS_1
ai14654
Figure 6. STM32F101xx medium-density access line VFQPFN48 pinout
Figure 7. STM32F101xx medium-density access line VFQPFN36 pinout
Doc ID 13586 Rev 14 23/87
Pinouts and pin description STM32F101x8, STM32F101xB
Pins
(2)
(1)
Table 4. Medium-density STM32F101xx pin definitions
Pin name
Type
LQFP64
LQFP48/
VFQFPN48
LQFP100
VFQFPN36
- - 1 - PE2 I/O
- - 2 - PE3 I/O
- - 3 - PE4 I/O
- - 4 - PE5 I/O
- - 5 - PE6 I/O
116- V
227-
338-
449-
--10- V
--11- V
BAT
PC13-TAMPER-
RTC
(5)
PC14-
OSC32_IN
PC15-
OSC32_OUT
SS_5
DD_5
(5)
SV
I/O PC13
I/O PC14
I/O PC15
(5)
SV
SV
I / O level
FT
FT
FT
FT
FT
5 5 12 2 OSC_IN I OSC_IN
6 6 13 3 OSC_OUT O OSC_OUT
7 7 14 4 NRST I/O NRST
- 8 15 - PC0 I/O PC0 ADC_IN10
- 9 16 - PC1 I/O PC1 ADC_IN11
- 10 17 - PC2 I/O PC2 ADC_IN12
- 11 18 - PC3 I/O PC3 ADC_IN13
812195 V
--20- V
--21- V
913226 V
SSA
REF-
REF+
DDA
SV
SV
SV
SV
10 14 23 7 PA0-WKUP I/O PA0
11 15 24 8 PA1 I/O PA1
12 16 25 9 PA2 I/O PA2
13 17 26 10 PA3 I/O PA3
-1827- V
SS_4
SV
Main
function
(after reset)
(3)
Default Remap
PE2 TRACECLK
PE3 TRACED0
PE4 TRACED1
PE5 TRACED2
PE6 TRACED3
BAT
(6)
(6)
(6)
SS_5
DD_5
SSA
REF-
REF+
DDA
TAMPER-RTC
OSC32_IN
OSC32_OUT
WKUP/USART2_CTS
ADC_IN0/
TIM2_CH1_ETR
USART2_RTS
ADC_IN1/TIM2_CH2
USART2_TX
ADC_IN2/TIM2_CH3
USART2_RX
ADC_IN3/TIM2_CH4
SS_4
Alternate functions
(8)
/
(8)
(8)
/
(8)
(8)
/
(8)
(8)
/
(8)
(3)(4)
24/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Pinouts and pin description
Table 4. Medium-density STM32F101xx pin definitions (continued)
Pins
Pin name
LQFP64
LQFP48/
VFQFPN48
-1928- V
LQFP100
VFQFPN36
DD_4
14 20 29 11 PA4 I/O PA4
(2)
(1)
Typ e
Main
function
(3)
(after reset)
I / O level
SV
DD_4
SPI1_NSS
15 21 30 12 PA5 I/O PA5 SPI1_SCK
16 22 31 13 PA6 I/O PA6
17 23 32 14 PA7 I/O PA7
SPI1_MISO
SPI1_MOSI
Alternate functions
Default Remap
(8)
/ADC_IN4
USART2_CK
TIM3_CH1
TIM3_CH2
(8)
(8)
/ADC_IN5
(8)
/ADC_IN6
(8)
(8)
/ADC_IN7
(8)
/
- 24 33 PC4 I/O PC4 ADC_IN14
- 25 34 PC5 I/O PC5 ADC_IN15
18 26 35 15 PB0 I/O PB0 ADC_IN8/TIM3_CH3
19 27 36 16 PB1 I/O PB1 ADC_IN9/TIM3_CH4
(8)
(8)
20 28 37 17 PB2 I/O FT PB2/BOOT1
- - 38 - PE7 I/O FT PE7
- - 39 - PE8 I/O FT PE8
- - 40 - PE9 I/O FT PE9
--41- PE10 I/OFT PE10
--42- PE11 I/OFT PE11
--43- PE12 I/OFT PE12
--44- PE13 I/OFT PE13
--45- PE14 I/OFT PE14
--46- PE15 I/OFT PE15
21 29 47 - PB10 I/O FT PB10
22 30 48 - PB11 I/O FT PB11
23 31 49 18 V
24 32 50 19 V
SS_1
DD_1
25 33 51 - PB12 I/O FT PB12
26 34 52 - PB13 I/O FT PB13
SV
SV
SS_1
DD_1
SPI2_NSS / I2C2_SMBA /
27 35 53 - PB14 I/O FT PB14
I2C2_SCL/
USART3_TX
I2C2_SDA/
USART3_RX
USART3_CK
SPI2_SCK/
USART3_CTS
SPI2_MISO/
USART3_RTS
(8)
(8)
(8)
(8)
(8)
28 36 54 - PB15 I/O FT PB15 SPI2_MOSI
(3)(4)
TIM2_CH3
TIM2_CH4
Doc ID 13586 Rev 14 25/87
Pinouts and pin description STM32F101x8, STM32F101xB
Table 4. Medium-density STM32F101xx pin definitions (continued)
Pins
LQFP64
LQFP48/
VFQFPN48
LQFP100
Pin name
VFQFPN36
(1)
(2)
Typ e
Main
function
(3)
(after reset)
I / O level
Alternate functions
Default Remap
- - 55 - PD8 I/O FT PD8 USART3_TX
- - 56 - PD9 I/O FT PD9 USART3_RX
- - 57 - PD10 I/O FT PD10 USART3_CK
- - 58 - PD11 I/O FT PD11 USART3_CTS
- - 59 - PD12 I/O FT PD12
- - 60 - PD13 I/O FT PD13 TIM4_CH2
- - 61 - PD14 I/O FT PD14 TIM4_CH3
- - 62 - PD15 I/O FT PD15 TIM4_CH4
- 37 63 - PC6 I/O FT PC6 TIM3_CH1
38 64 - PC7 I/O FT PC7 TIM3_CH2
39 65 - PC8 I/O FT PC8 TIM3_CH3
- 40 66 - PC9 I/O FT PC9 TIM3_CH4
29 41 67 20 PA8 I/O FT PA8 USART1_CK/MCO
30 42 68 21 PA9 I/O FT PA9 USART1_TX
31 43 69 22 PA10 I/O FT PA10 USART1_RX
(8)
(8)
32 44 70 23 PA11 I/O FT PA11 USART1_CTS
33 45 71 24 PA12 I/O FT PA12 USART1_RTS
34 46 72 25 PA13 I/O FT JTMS-SWDIO PA13
- - 73 - Not connected
35 47 74 26 V
36 48 75 27 V
SS_2
DD_2
SV
SV
SS_2
DD_2
37 49 76 28 PA14 I/O FT JTCK/SWCLK PA14
38 50 77 29 PA15 I/O FT JTDI
- 51 78 PC10 I/O FT PC10 USART3_TX
- 52 79 PC11 I/O FT PC11 USART3_RX
- 53 80 PC12 I/O FT PC12 USART3_CK
55812 PD0 I/OFTOSC_IN
6 6 82 3 PD1 I/O FT OSC_OUT
(7)
(7)
54 83 - PD2 I/O FT PD2 TIM3_ETR
- - 84 - PD3 I/O FT PD3 USART2_CTS
- - 85 - PD4 I/O FT PD4 USART2_RTS
(3)(4)
TIM4_CH1 /
USART3_RTS
TIM2_CH1_ETR/
PA15/ SPI1_NSS
26/87 Doc ID 13586 Rev 14
STM32F101x8, STM32F101xB Pinouts and pin description
Table 4. Medium-density STM32F101xx pin definitions (continued)
Pins
LQFP64
LQFP48/
VFQFPN48
LQFP100
Pin name
VFQFPN36
(1)
(2)
Typ e
Main
function
(3)
(after reset)
I / O level
Alternate functions
Default Remap
- - 86 - PD5 I/O FT PD5 USART2_TX
- - 87 - PD6 I/O FT PD6 USART2_RX
- - 88 - PD7 I/O FT PD7 USART2_CK
39 55 89 30 PB3 I/O FT JTDO
40 56 90 31 PB4 I/O FT JNTRST
41 57 91 32 PB5 I/O PB5 I2C1_SMBAl
42 58 92 33 PB6 I/O FT PB6
43 59 93 34 PB7 I/O FT PB7
I2C1_SCL
TIM4_CH1
I2C1_SDA
TIM4_CH2
(8)
(8)
(8)
(8)
/
/
44 60 94 35 BOOT0 I BOOT0
45 61 95 - PB8 I/O FT PB8 TIM4_CH3
46 62 96 - PB9 I/O FT PB9 TIM4_CH4
(8)
(8)
- - 97 - PE0 I/O FT PE0 TIM4_ETR
- - 98 - PE1 I/O FT PE1
47 63 99 36 V
48 64 100 1 V
SS_3
DD_3
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to
the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
SV
SV
SS_3
DD_3
(3)(4)
TIM2_CH2 / PB3
TRACESWO
SPI1_SCK
PB4 / TIM3_CH1
SPI1_MISO
TIM3_CH2 /
SPI1_MOSI
USART1_TX
USART1_RX
I2C1_SCL
I2C1_SDA
Doc ID 13586 Rev 14 27/87
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