ST STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG User Manual

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XL-density access line, ARM-based 32-bit MCU with 768 KB

LQFP144

20 × 2

0 mm

LQFP64

× 10 mm

LQFP100

× 14 mm

to 1 MB Flash, 15 timers, 1 ADC and 10 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU with MPU

– 36 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) performance

– Single-cycle multiplication and hardware

division

■ Memories

– 768 Kbytes to 1 Mbyte of Flash memory

(dual bank with read-while-write capability) – 80 Kbytes of SRAM – Flexible static memory controller with 4

Chip Select. Supports Compact Flash,

SRAM, PSRAM, NOR and NAND

memories – LCD parallel interface, 8080/6800 modes

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage

detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC with calibration

capability – 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes –V

■ 1 x 12-bit, 1 µs A/D converters (up to 16

channels) – Conversion range: 0 to 3.6 V – Temperature sensor

■ 2 × 12-bit D/A converters

■ DMA

– 12-channel DMA controller – Peripherals supported: timers, ADC, DAC,

■ Up to 112 fast I/O ports

supply for RTC and backup registers

BAT

SPIs, I

Cs and USARTs

STM32F101xF

STM32F101xG

Preliminary data

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors and almost all 5 V-tolerant

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces – Cortex-M3 Embedded Trace Macrocell™

■ Up to 15 timers

– Up to ten 16-bit timers, with up to 4

IC/OC/PWM or pulse counters

– 2 × watchdog timers (Independent and

Window) – SysTick timer: a 24-bit downcounter – 2 × 16-bit basic timers to drive the DAC

■ Up to 10 communication interfaces

– Up to 2 x I – Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control) – Up to 3 SPIs (18 Mbit/s)

■ CRC calculation unit, 96-bit unique ID

■ ECOPACK

Table 1. Device summary

Reference Part number

STM32F101xF

STM32F101xG

C interfaces (SMBus/PMBus)

packages

STM32F101RF STM32F101VF STM32F101ZF

STM32F101RG STM32F101VG STM32F101ZG

November 2010 Doc ID 17143 Rev 2 1/108

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

www.st.com

STM32F101xF, STM32F101xG

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15

2.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15

2.3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.6 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.7 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.8 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16

2.3.9 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.11 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.12 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.13 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.14 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.15 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.16 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19

2.3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.19 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.20 Universal synchronous/asynchronous receiver transmitters (USARTs) 21

2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.23 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.24 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.26 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.27 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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STM32F101xF, STM32F101xG

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 38

5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 78

5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Doc ID 17143 Rev 2 3/108

STM32F101xF, STM32F101xG

6.2.2 Evaluating the maximum junction temperature for an application . . . . 105

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F101xF and STM32F101xG features and peripheral counts . . . . . . . . . . . . . . . . . 11

Table 3. STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. STM32F101xF and STM32F101xG timer feature comparison . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. STM32F101xF and STM32F101xG pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 12. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 13. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 14. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 15. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 43

Table 17. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 43

Table 18. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 47

Table 20. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 21. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 22. Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 23. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 24. LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

LSE

Table 25. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 26. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 28. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 58

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 59

Table 33. Asynchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 34. Asynchronous multiplexed NOR/PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 35. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 36. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 37. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 38. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 39. Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 73

Table 40. Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 76

Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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STM32F101xF, STM32F101xG

Table 50. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 51. I Table 52. SCL frequency (f

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

PCLK1

Table 53. STM32F10xxx SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 54. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 55. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 56. R

max for f

AIN

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

ADC

Table 57. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 58. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 59. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 60. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 61. LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . 101

Table 62. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . 102

Table 63. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . 103

Table 64. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 65. STM32F101xF and STM32F101xG ordering information scheme . . . . . . . . . . . . . . . . . . 106

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STM32F101xF, STM32F101xG List of figures

List of figures

Figure 1. STM32F101xF and STM32F101xG access line block diagram . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. STM32F101xF and STM32F101xG access line LQFP144 pinout . . . . . . . . . . . . . . . . . . . 23

Figure 4. STM32F101xF and STM32F101xG LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 5. STM32F101xF and STM32F101xG LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 6. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 7. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42

Figure 13. Typical current consumption on V

different V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

BAT

Figure 14. Typical current consumption in Stop mode with regulator in run mode

versus temperature at different V Figure 15. Typical current consumption in Stop mode with regulator in low-power

mode versus temperature at different V Figure 16. Typical current consumption in Standby mode versus temperature at

different V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 18. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 58

Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 59

Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 25. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 26. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 28. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 29. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 69

Figure 30. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 70

Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 33. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 72

Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 73

Figure 35. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 36. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 37. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 75

Figure 38. NAND controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . 76

Figure 39. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 40. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

with RTC on vs. temperature at

BAT

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Doc ID 17143 Rev 2 7/108

List of figures STM32F101xF, STM32F101xG

Figure 41. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 42. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 43. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 44. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 45. I

Figure 46. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 47. SPI timing diagram - slave mode and CPHA=1 Figure 48. SPI timing diagram - master mode

C bus AC waveforms and measurement circuit

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 49. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 50. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 51. Power supply and reference decoupling (V

not connected to V

REF+

). . . . . . . . . . . . . . 96

DDA

Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 97

Figure 53. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 54. LQFP144, 20 x 20 mm, 144-pin thin quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 55. Recommended footprint

Figure 56. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 102

Figure 57. Recommended footprint

Figure 58. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 103

Figure 59. Recommended footprint Figure 60. LQFP64 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F101xF and STM32F101xG XL-density access line microcontrollers. For more

details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2:

Full compatibility throughout the family.

The XL-density STM32F101xx datasheet should be read in conjunction with the

STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Doc ID 17143 Rev 2 9/108

Description STM32F101xF, STM32F101xG

2 Description

The STM32F101xF and STM32F101xG access line family incorporates the high-

performance ARM

Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM of 80 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer one 12-bit ADC, ten general-purpose 16-bit timers, as well as standard and advanced communication interfaces: up to two I

Cs, three SPIs and five USARTs.

The STM32F101xx XL-density access line family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

These features make the STM32F101xx XL-density access line microcontroller family suitable for a wide range of applications such as medical and handheld equipment, PC peripherals and gaming, GPS platforms, industrial applications, PLC, printers, scanners alarm systems , power meters, and video intercom.

10/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Description

2.1 Device overview

The STM32F101xx XL-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

●

Figure 1 shows the general block diagram of the device family.

Table 2. STM32F101xF and STM32F101xG features and peripheral counts

Peripherals STM32F101Rx STM32F101Vx STM32F101Zx

Flash memory 768 KB 1 MB 768 KB 1 MB 768 KB 1 MB

SRAM in Kbytes 80 80 80

FSMC No Yes Yes

Timers

General-purpose 10

Basic 2

SPI 3 Communication interfaces

USART 5

GPIOs 51 80 112

12-bit ADC Number of channels

12-bit DAC Number of channels

2 2

CPU frequency 36 MHz

Operating voltage 2.0 to 3.6 V

Operating temperatures

Package LQFP64 LQFP100

1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.

Ambient temperature: –40 to +85 °C (see Ta bl e 1 0)

Junction temperature: –40 to +105 °C (see Ta bl e 1 0 )

(1)

LQFP144

Doc ID 17143 Rev 2 11/108

Description STM32F101xF, STM32F101xG

Figure 1. STM32F101xF and STM32F101xG access line block diagram

TRACECLK TRACED[0:3] as AS

NJTRST

JTDI JTCK/SWCLK JTMS/SWDIO

JTDO as AF

A[25:0] D[15:0]

CLK NOE NWE

NE[4:1]

NBL[1:0]

NWAIT

as AF

112AF

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

2 channels as AF

1 channel as AF

MOSI, MISO, SCK, NSS as AF

RX, TX, CTS, RTS as AF

ADC_IN[0:15]

REF–

REF+

TPIU

Trace/trig

SW/JTAG

MPU

Cortex-M3 CPU

: 36 MHz

max

NVIC

GP DMA1

7 channels

GP DMA2

5 channels

EXT.IT WKUP

GPIO port A

GPIO port B

GPIO port C

GPIO port D

GPIO port E

GPIO port F

GPIO port G

TIM9

TIM10

TIM11

SPI1

USART1

Temp. sensor

12-bit ADC

@ V

DDA

ETM

FSMC

Pbus

Dbus

System

Ibus

APB2: Fmax = 24/36 MHz

Trace controller

Bus matrix

AHB2

APB2

SRAM

80 Kbyte

AHB2

APB1

obl

Flash 512 Kbyte

Flash

interface

obl

Flash 512 Kbyte

Flash

interface

Reset & clock control

WWDG

TIM6

TIM7

64 bit

RC 8 MHz

RC 40 kHz

PCLK1 PCLK2 HCLK FCLK

PLL

DDA

POR

Reset

Int

= 24/36 MHz

max

APB1: F

Volt. reg.

3.3 V to 1.8 V

Supply supervision

POR / PDR

IWDG

Standby

interface

XTAL 32kHz

RTC

AWU

Backup interface

TIM2

TIM12

TIM13

TIM14

USART 2

USART 3

UART4

UART5

12bit DAC1

IFIF IF

12bit DAC 2

Power

DDA

PVD

XTAL OSC 4-16 MHz

BAT

Backup

reg

TIM3

TIM4

TIM5

SPI2

SPI3

I2C1

I2C2

DDA

NRST V

DDA

SSA

OSC_IN OSC_OUT

=1.8 V to 3.6 V

BAT

OSC32_IN OSC32_OUT

TAMPER-RTC/ ALARM/SECOND OUT

4 channels as AF

2 channels as AF

1 channel as AF

RX, TX, CTS, RTS CK, as AF RX, TX, CTS, RT S, CK, as AF

RX,TX as AF

MOSI, MISO SCK, NSS as AF

MOSI, MISO

SCK, NSS as AF

SCL, SDA, SMBA as AF

DAC_OUT1 as AF

DAC_OUT2 as AF

REF+

ai15830

1. TA = –40 °C to +85 °C (junction temperature up to 105 °C).

2. AF = alternate function on I/O port pin.

12/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Description

(3%/3#

-(Z

/3#?).

/3#?/54

/3#?).

/3#?/54

,3%/3# K(Z

(3)2#

-(Z

,3)2# K(Z

TOINDEPENDENTWATCHDOG)7$'

0,,

XXX

0,,-5,

(3%(IGHSPEEDEXTERNALCLOCKSIGNALIG

,3%

,3)

(3)

,EGEND

-#/

#LOCK/UTPUT

-AIN

0,,8402%



X

!(" 0RESCALER 



0,,#,+

(3)

(3%

!0"

0RESCALER



!$# 0RESCALER 

!$##,+

0#,+

(#,+

0,,#,+

TO!("BUSCORE MEMORYAND$-!

TO!$#

,3%

,3)

(3)





(3)

(3%

PERIPHERALS

TO!0"

0ERIPHERAL#LOCK

%NABLE

%NABLE

0ERIPHERAL#LOCK

!0"

0RESCALER



0#,+

TO!0"PERIPHERALS

0ERIPHERAL#LOCK

%NABLE

-(ZMAX

-(Z

-(ZMAX

TO24#

0,,32#

-#/

#33

TO#ORTEX3YSTEMTIMER



#LOCK

%NABLE

393#,+

MAX

24##,+

24#3%,;=

4)-X#,+

)7$'#,+

393#,+

&#,+#ORTEX FREERUNNINGCLOCK

4)-

TO4)- AND

TO&3-#

&3-##,+

0ERIPHERALCLOCK ENABLE

AI

)F!0"PRESCALERX

ELSEX

(IGHSPEEDINTERNALCLOCKSIGNAL

,OWSPEEDEXTERNALCLOCKSIGNAL

,OWSPEEDINTERNALCLOCKSIGNAL

0ERIPHERAL#LOCK %NABLE

4)-X#,+

4)-

TO4)-4)- AND4)-

)F!0"PRESCALERX

ELSEX

&,)4&#,+

TO&LASHPROGRAMMING INTERFACE

Figure 2. Clock tree

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz.

2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

Doc ID 17143 Rev 2 13/108

Description STM32F101xF, STM32F101xG

2.2 Full compatibility throughout the family

The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are identified as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, the STM32F101xC, STM32F101xD, STM32F101xE are referred to as high-density devices, and the STM32F101xF and STM32F101xG are referred to as XL-density devices.

Low-, high-density and XL-density devices are an extension of the STM32F101x8/B medium-density devices, they are specified in the STM32F101x4/6, STM32F101xC/D/E and STM32F101xF/G datasheets, respectively.

Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM densities, and additional peripherals like FSMC and DAC. XL-density devices bring greater Flash and RAM capacities, and more features, namely an MPU, a higher number of timers and a dual bank Flash memory, while remaining fully compatible with the other members of the family.

The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD, STM32F101xE, STM32F101xF and STM32F101xG are a drop-in replacement for the STM32F101x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F101xx access line family is fully compatible with all existing STM32F103xx performance line and STM32F102xx USB access line devices.

Table 3. STM32F101xx family

Pinout

144

100

1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.

Memory size

Low-density devices Medium-density devices High-density devices XL-density devices

16 KB

Flash

4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM

32 KB

Flash

(1)

64 KB

Flash

128 KB

Flash

256 KB

Flash

32 KB

RAM

384 KB

Flash

48 KB

RAM

512 KB

Flash

48 KB

RAM

768 KB

80 KB

5 × USARTs 10 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I 1 × ADC, 1 × DAC FSMC (100 and 144 pins), Cortex-M3 with MPU, Dual bank Flash memory

2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I

1 × ADC

3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC

5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I

Cs, 1 × ADC, 1 × DAC FSMC (100 and 144 pins)

Flash

RAM

1 MB

Flash

80 KB

RAM

Cs,

14/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Description

2.3 Overview

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The STM32F101xF and STM32F101xG access line family having an embedded ARM core, is therefore compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2 Memory protection unit

The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

2.3.3 Embedded Flash memory

768 Kbytes to 1 Mbyte of embedded Flash are available for storing programs and data. The Flash memory is organized as two banks. The first bank has a size of 512 Kbytes. The second bank is either 256 or 512 Kbytes depending on the device. This gives the device the capability of writing to one bank while executing code from the other bank (read-while-write capability).

2.3.4 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

Doc ID 17143 Rev 2 15/108

Description STM32F101xF, STM32F101xG

2.3.5 Embedded SRAM

80 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.6 FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F101xF and STM32F101xG access line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND.

Functionality overview:

● The three FSMC interrupt lines are ORed in order to be connected to the NVIC

● Write FIFO

● Code execution from external memory except for NAND Flash and PC Card

● The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at

36 MHz

2.3.7 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

2.3.8 Nested vectored interrupt controller (NVIC)

The STM32F101xF and STM32F101xG access line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low-latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

2.3.9 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines.

16/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Description

2.3.10 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and APB domains is 36 MHz. See Figure 2 for details on the clock tree.

2.3.11 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes.

● Boot from system memory

● Boot from embedded SRAM

The bootloader is located in system memory. It is used to reprogram the Flash memory by using USART1.

2.3.12 Power supply schemes

● V

For more details on how to connect power pins, refer to Figure 9: Power supply scheme.

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

, V

SSA

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

DDA

RCs and PLL (minimum voltage to be applied to V used). V

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

BAT

DDA

and V

registers (through power switch) when V

2.3.13 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the V

DD/VDDA

generated when V than the V message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

POR/PDR

power supply and compares it to the V

DD/VDDA

threshold. The interrupt service routine can then generate a warning

PVD

and V

PVD

pins.

must be connected to VDD and VSS, respectively.

SSA

is below a specified threshold, V

drops below the V

PVD

is 2.4 V when the ADC or DAC is

DDA

is not present.

POR/PDR

threshold. An interrupt can be

PVD

, without the need for an

threshold and/or when VDD/V

is higher

DDA

Doc ID 17143 Rev 2 17/108

Description STM32F101xF, STM32F101xG

2.3.14 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop modes.

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.15 Low-power modes

The STM32F101xF and STM32F101xG access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.16 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers.

The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

18/108 Doc ID 17143 Rev 2

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose and basic

timers TIMx, DAC and ADC.

STM32F101xF, STM32F101xG Description

2.3.17 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on V

supply when present or through the V

registers used to store 84 bytes of user application data when V

pin. The backup registers are forty-two 16-bit

BAT

power is not present.

They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.18 Timers and watchdogs

The XL-density STM32F101xx access line devices include up to ten general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.

Table 4: STM32F101xF and STM32F101xG timer feature comparison compares the

features of the general-purpose and basic timers.

Table 4. STM32F101xF and STM32F101xG timer feature comparison

Timer

TIM2, TIM3, TIM4, TIM5

TIM9, TIM12 16-bit Up

TIM10, TIM11, TIM13, TIM14

TIM6, TIM7 16-bit Up

Counter

resolution

16-bit

16-bit Up

Counter

type

Up, down,

up/down

Prescaler factor

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

DMA

request

generation

Ye s 4 No

No 2 No

No 1 No

Ye s 0 No

General-purpose timers (TIMx)

There are 10 synchronizable general-purpose timers embedded in the STM32F101xF and STM32F101xG XL-density access line devices (see Ta bl e 4 for differences).

● TIM2, TIM3, TIM4, TIM5

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F101xF and STM32F101xG access line devices.

These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or

Capture/compare

channels

Complementary

outputs

Doc ID 17143 Rev 2 19/108

Description STM32F101xF, STM32F101xG

one-pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages.

Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

● TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

● TIM13, TIM14 and TIM12

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13 and TIM14 feature one independent channel, whereas TIM12 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

20/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Description

2.3.19 I²C bus

Up to two I²C bus interfaces can operate in multi-master and slave modes. They support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus.

2.3.20 Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F101xF and STM32F101xG access line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.

2.3.21 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2.3.22 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

2.3.23 ADC (analog to digital converter)

A 12-bit analog-to-digital converter is embedded into STM32F101xF and STM32F101xG access line devices. It has up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

Doc ID 17143 Rev 2 21/108

Description STM32F101xF, STM32F101xG

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

2.3.24 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

● two DAC converters: one for each output channel

● 8-bit or 12-bit monotonic output

● left or right data alignment in 12-bit mode

● synchronized update capability

● noise-wave generation

● triangular-wave generation

● dual DAC channel independent or simultaneous conversions

● DMA capability for each channel

● external triggers for conversion

● input voltage reference V

Seven DAC trigger inputs are used in the STM32F101xF and STM32F101xG access line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

REF+

2.3.25 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

2.3.26 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.3.27 Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

< 3.6 V. The temperature sensor is internally

DDA

22/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Pinouts and pin descriptions

DD_3VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PG15

DD_11VSS_11

PG14

PG13

PG12

PG11

PG10

PG9

PD7

PD6

DD_10VSS_10

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

PE2

DD_2

PE3

SS_2

PE4

PE5

PA13

PE6

PA12

VBAT

PA11

PC13-TAMPER-RTC

PA10

PC14-OSC32_IN

PA9

PC15-OSC32_OUT

PA8

PF0

PC9

PF1

PC8

PF2

PC7

PF3

PC6

PF4

DD_9

PF5

SS_9

SS_5

PG8

DD_5

PG7

PF6

PG6

PF7

PG5

PF8

PG4

PF9

PG3

PF10

PG2

OSC_IN

PD15

OSC_OUT

PD14

NRST

DD_8

PC0

SS_8

PC1

PD13

PC2

PD12

PC3

PD11

SSA

PD10

REF-

PD9

REF+

PD8

DDA

PB15

PA0-WKUP

PB14

PA1

PB13

PA2

PB12

PA3

SS_4

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PF11

PF12

VSS_6

DD_6

PF13

PF14

PF15

PG0

PG1

PE7

PE8

PE9

SS_7

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

SS_1

DD_1

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

109

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84

3738394041424344454647484950515253545556575859

LQFP144

120

119

118

117

116

115

114

113

112

111

110

6162636465666768697071

26 27 28 29 30 31 32 33 34 35 36

83 82 81 80 79 78 77 76 75 74 73

ai14667

3 Pinouts and pin descriptions

Figure 3. STM32F101xF and STM32F101xG access line LQFP144 pinout

Doc ID 17143 Rev 2 23/108

Pinouts and pin descriptions STM32F101xF, STM32F101xG

100

9998979695949392919089888786858483828180797877

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

VDD_2 VSS_2 NC PA 1 3 PA 1 2 PA 1 1 PA 1 0 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS_1

VDD_1

VDD_3

VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

26272829303132333435363738394041424344454647484950

PE2 PE3 PE4 PE5 PE6

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

OSC_IN

OSC_OUT

NRST

PC0 PC1 PC2 PC3

VSSA

VREF-

VREF+

VDDA

PA 0- W K UP

PA 1 PA 2

ai14391

LQFP100

Figure 4. STM32F101xF and STM32F101xG LQFP100 pinout

24/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Pinouts and pin descriptions

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

47 46

45 44 43

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

2 3

5 6

10 11 12

14 15

BAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

PC0 PC1 PC2 PC3

SSA

DDA

PA 0- W K UP

PA 1 PA 2

DD_3

SS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA 1 5

PA 14

DD_2

SS_2

PA 1 3 PA 1 2 PA 1 1 PA 1 0 PA 9 PA 8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12

PA 3

SS_4

DD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

SS_1

DD_1

LQFP64

ai14392

Figure 5. STM32F101xF and STM32F101xG LQFP64 pinout

Table 5. STM32F101xF and STM32F101xG pin definitions

Pins

LQFP64

LQFP144

LQFP100

Pin name

(1)

(2)

Typ e

Main

function

(after reset)

I / O level

(3)

Alternate functions

Default Remap

(4)

1 - 1 PE2 I/O FT PE2 TRACECLK / FSMC_A23

2 - 2 PE3 I/O FT PE3 TRACED0 / FSMC_A19

3 - 3 PE4 I/O FT PE4 TRACED1 / FSMC_A20

4 - 4 PE5 I/O FT PE5 TRACED2 / FSMC_A21 TIM9_CH1

5 - 5 PE6 I/O FT PE6 TRACED3 / FSMC_A22 TIM9_CH2

616 V

BAT

7 2 7 PC13-TAMPER-RTC

8 3 8 PC14-OSC32_IN

9 4 9 PC15-OSC32_OUT

(5)

I/O PC13

(5)

I/O PC14

(5)

I/O PC15

BAT

(6)

TAMPER-RTC

OSC32_IN

OSC32_OUT

10 - - PF0 I/O FT PF0 FSMC_A0

11 - - PF1 I/O FT PF1 FSMC_A1

12 - - PF2 I/O FT PF2 FSMC_A2

13 - - PF3 I/O FT PF3 FSMC_A3

14 - - PF4 I/O FT PF4 FSMC_A4

15 - - PF5 I/O FT PF5 FSMC_A5

16 - 10 V

17 - 11 V

SS_5

DD_5

SS_5

DD_5

Doc ID 17143 Rev 2 25/108

Pinouts and pin descriptions STM32F101xF, STM32F101xG

Table 5. STM32F101xF and STM32F101xG pin definitions (continued)

Pins

LQFP144

LQFP64

(2)

Pin name

(1)

Typ e

LQFP100

Main

function

(after reset)

I / O level

(3)

Alternate functions

Default Remap

18 - - PF6 I/O PF6 FSMC_NIORD TIM10_CH1

19 - - PF7 I/O PF7 FSMC_NREG TIM11_CH1

20 - - PF8 I/O PF8 FSMC_NIOWR TIM3_CH1

21 - - PF9 I/O PF9 FSMC_CD TIM14_CH1

22 - - PF10 I/O PF10 FSMC_INTR

23 5 12 OSC_IN I OSC_IN

24 6 13 OSC_OUT O OSC_OUT

25 7 14 NRST I/O NRST

26 8 15 PC0 I/O PC0 ADC_IN10

27 9 16 PC1 I/O PC1 ADC_IN11

28 10 17 PC2 I/O PC2 ADC_IN12

29 11 18 PC3 I/O PC3 ADC_IN13

30 12 19 V

31 - 20 V

32 - 21 V

33 13 22 V

SSA

REF-

REF+

DDA

34 14 23 PA0-WKUP I/O PA0

35 15 24 PA1 I/O PA1

36 16 25 PA2 I/O PA2

37 17 26 PA3 I/O PA3

SSA

REF-

REF+

DDA

USART2_RX

WKUP/ USART2_CTS

ADC_IN0 / TIM5_CH1/

TIM2_CH1_ETR

USART2_RTS

ADC_IN1 / TIM5_CH2

TIM2_CH2

USART2_TX

TIM5_CH3 / ADC_IN2/

TIM2_CH3

(7)

/ TIM9_CH1

/ TIM5_CH4/

ADC_IN3 / TIM2_CH4

(7)

TIM9_CH2

38 18 27 V

39 19 28 V

SS_4

DD_4

40 20 29 PA4 I/O PA4

41 21 30 PA5 I/O PA5

42 22 31 PA6 I/O PA6

SS_4

DD_4

SPI1_NSS/ DAC_OUT1 /

ADC_IN4 / USART2_CK

SPI1_SCK / DAC_OUT2 /

ADC_IN5

SPI1_MISO / ADC_IN6 /

TIM3_CH1

(7)

/ TIM13_CH1

(7)

(4)

26/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Pinouts and pin descriptions

Table 5. STM32F101xF and STM32F101xG pin definitions (continued)

Pins

Pin name

LQFP64

LQFP144

LQFP100

43 23 32 PA7 I/O PA7

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O level

SPI1_MOSI / ADC_IN7 /

TIM3_CH2

44 24 33 PC4 I/O PC4 ADC_IN14

45 25 34 PC5 I/O PC5 ADC_IN15

46 26 35 PB0 I/O PB0 ADC_IN8 / TIM3_CH3

47 27 36 PB1 I/O PB1 ADC_IN9 / TIM3_CH4

48 28 37

PB2 I/O FT PB2/BOOT1

49 - - PF11 I/O FT PF11 FSMC_NIOS16

50 - - PF12 I/O FT PF12 FSMC_A6

51 - - V

52 - - V

SS_6

DD_6

53 - - PF13 I/O

SS_6

DD_6

PF13 FSMC_A7

54 - - PF14 I/O FT PF14 FSMC_A8

55 - - PF15 I/O

PF15 FSMC_A9

56 - - PG0 I/O FT PG0 FSMC_A10

57 - - PG1 I/O

PG1 FSMC_A11

58 - 38 PE7 I/O FT PE7 FSMC_D4

59 - 39 PE8 I/O FT PE8 FSMC_D5

60 - 40 PE9 I/O FT PE9 FSMC_D6

61 - - V

62 - - V

SS_7

DD_7

SS_7

DD_7

63 - 41 PE10 I/O FT PE10 FSMC_D7

64 - 42 PE11 I/O FT PE11 FSMC_D8

65 - 43 PE12 I/O FT PE12 FSMC_D9

66 - 44 PE13 I/O FT PE13 FSMC_D10

67 - 45 PE14 I/O FT PE14 FSMC_D11

68 - 46 PE15 I/O FT PE15 FSMC_D12

69 29 47 PB10 I/O FT PB10 I2C2_SCL / USART3_TX

70 30 48 PB11 I/O FT PB11 I2C2_SDA / USART3_RX

71 31 49 V

72 32 50 V

SS_1

DD_1

73 33 51 PB12 I/O FT PB12

SS_1

DD_1

SPI2_NSS

USART3_CK

Alternate functions

Default Remap

(7)

/ TIM14_CH1

(7)

/ I2C2_SMBA /

(7)

(4)

TIM2_CH3

TIM2_CH4

Doc ID 17143 Rev 2 27/108

Pinouts and pin descriptions STM32F101xF, STM32F101xG

Table 5. STM32F101xF and STM32F101xG pin definitions (continued)

Pins

LQFP144

LQFP64

Pin name

LQFP100

(2)

(1)

Typ e

Main

function

(after reset)

I / O level

74 34 52 PB13 I/O FT PB13

75 35 53 PB14 I/O FT PB14

(3)

USART3_RTS

Alternate functions

Default Remap

(7)

SPI2_SCK

USART3_CTS

SPI2_MISO

TIM12_CH1

76 36 54 PB15 I/O FT PB15 SPI2_MOSI

(7)

/ TIM12_CH2

77 - 55 PD8 I/O FT PD8 FSMC_D13 USART3_TX

78 - 56 PD9 I/O FT PD9 FSMC_D14 USART3_RX

79 - 57 PD10 I/O FT PD10 FSMC_D15 USART3_CK

80 - 58 PD11 I/O FT PD11 FSMC_A16 USART3_CTS

81 - 59 PD12 I/O FT PD12 FSMC_A17

82 - 60 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2

83 - - V

84 - - V

SS_8

DD_8

SS_8

DD_8

85 - 61 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3

86 - 62 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4

87 - - PG2 I/O FT PG2 FSMC_A12

88 - - PG3 I/O FT PG3 FSMC_A13

89 - - PG4 I/O FT PG4 FSMC_A14

90 - - PG5 I/O FT PG5 FSMC_A15

91 - - PG6 I/O FT PG6 FSMC_INT2

92 - - PG7 I/O FT PG7 FSMC_INT3

93 - - PG8 I/O FT PG8

94 - - V

95 - - V

SS_9

DD_9

SS_9

DD_9

96 37 63 PC6 I/O FT PC6 TIM3_CH1

97 38 64 PC7 I/O FT PC7 TIM3_CH2

98 39 65 PC8 I/O FT PC8 TIM3_CH3

99 40 66 PC9 I/O FT PC9 TIM3_CH4

100 41 67 PA8 I/O FT PA8 USART1_CK / MCO

101 42 68 PA9 I/O FT PA9 USART1_TX

102 43 69 PA10 I/O FT PA10 USART1_RX

(7)

103 44 70 PA11 I/O FT PA11 USART1_CTS

(4)

TIM4_CH1 /

USART3_RTS

28/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Pinouts and pin descriptions

Table 5. STM32F101xF and STM32F101xG pin definitions (continued)

Pins

LQFP144

LQFP64

Pin name

LQFP100

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O level

104 45 71 PA12 I/O FT PA12 USART1_RTS

105 46 72 PA13 I/O FT JTMS-SWDIO

106 - 73 Not connected

107 47 74

108 48 75

109 49 76

110 50 77

111 51 78

112 52 79

113 53 80

114 5 81

115 6 82

116 54 83

117 - 84

118 - 85

119 - 86

120 - -

121 - -

122 - 87

123 - 88

124 - -

125 - -

126 - -

127 - -

128 - -

129 - -

130 - -

131 - -

132 - -

SS_2

DD_2

PA 1 4 I / O FT

SS_2

DD_2

JTCK-

SWCLK

PA15 I/O FT JTDI SPI3_NSS

PC10 I/O FT PC10 UART4_TX

PC11 I/O FT PC11 UART4_RX

PC12 I/O FT PC12 UART5_TX

PD0 I/O FT OSC_IN

PD1 I/O FT OSC_OUT

(8)

PD2 I/O FT PD2 TIM3_ETR / UART5_RX

PD3 I/O FT PD3 FSMC_CLK

PD4 I/O FT PD4 FSMC_NOE

PD5 I/O FT PD5 FSMC_NWE

SS_10

DD_10

SS_10

DD_10

PD6 I/O FT PD6 FSMC_NWAIT

PD7 I/O FT PD7 FSMC_NE1 /

PG9 I/O FT PG9 FSMC_NE2 /

PG10 I/O FT PG10

PG11 I/O FT PG11

FSMC_NCE4_1

FSMC_NCE4_2

PG12 I/O FT PG12 FSMC_NE4

PG13 I/O FT PG13 FSMC_A24

PG14 I/O FT PG14 FSMC_A25

SS_11

DD_11

SS_11

DD_11

PG15 I/O FT PG15

Alternate functions

Default Remap

FSMC_D2

FSMC_D3

(9)

FSMC_NCE2 USART2_CK

FSMC_NCE3

FSMC_NE3 /

(4)

TIM2_CH1_ETR/ PA15 /

USART3_TX

USART3_RX

USART3_CK

USART2_CTS

USART2_RTS

USART2_TX

USART2_RX

PA 1 3

PA 1 4

SPI1_NSS

Doc ID 17143 Rev 2 29/108

Pinouts and pin descriptions STM32F101xF, STM32F101xG

Table 5. STM32F101xF and STM32F101xG pin definitions (continued)

Pins

LQFP64

LQFP144

133 55 89

134 56 90

(2)

Pin name

(1)

Typ e

LQFP100

Main

function

(after reset)

I / O level

(3)

PB3 I/O FT JTDO SPI3_SCK

PB4 I/O FT NJTRST SPI3_MISO

Alternate functions

Default Remap

135 57 91 PB5 I/O PB5 I2C1_SMBA/ SPI3_MOSI

136 58 92 PB6 I/O FT PB6 I2C1_SCL / TIM4_CH1

137 59 93 PB7 I/O FT PB7

I2C1_SDA / FSMC_NADV /

TIM4_CH2

(7)

138 60 94 BOOT0 I BOOT0

139 61 95 PB8 I/O FT PB8 TIM4_CH3

140 62 96 PB9 I/O FT PB9 TIM4_CH4

141 - 97 PE0 I/O FT PE0 TIM4_ETR

(7)

/ FSMC_NBL0

142 - 98 PE1 I/O FT PE1 FSMC_NBL1

143 63 99 V

144 64 100 V

SS_3

DD_3

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.

7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.

8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual

9. For devices delivered in LQFP64 packages, the FSMC function is not available.

SS_3

DD_3

(4)

TIM2_CH2 /

TRACESWO

SPI1_SCK

TIM3_CH1

PB4 /

SPI1_MISO

TIM3_CH2 / SPI1_MOSI

USART1_TX

USART1_RX

I2C1_SCL

I2C1_SDA

PB3

30/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Pinouts and pin descriptions

Table 6. FSMC pin definition

FSMC

Pins

CF CF/IDE

NOR/PSRAM/

SRAM

NOR/PSRAM

Mux

NAND 16 bit

LQFP100

PE2 A23 A23 Yes

PE3 A19 A19 Yes

PE4 A20 A20 Yes

PE5 A21 A21 Yes

PE6 A22 A22 Yes

PF0 A0 A0 A0 -

PF1 A1 A1 A1 -

PF2 A2 A2 A2 -

PF3 A3 A3 -

PF4 A4 A4 -

PF5 A5 A5 -

PF6 NIORD NIORD -

PF7 NREG NREG -

(1)

PF8 NIOWR NIOWR -

PF9 CD CD -

PF10 INTR INTR -

PF11 NIOS16 NIOS16 -

PF12 A6 A6 -

PF13 A7 A7 -

PF14 A8 A8 -

PF15 A9 A9 -

PG0 A10 A10 -

PG1 A11 -

PE7 D4 D4 D4 DA4 D4 Yes

PE8 D5 D5 D5 DA5 D5 Yes

PE9 D6 D6 D6 DA6 D6 Yes

PE10 D7 D7 D7 DA7 D7 Yes

PE11 D8 D8 D8 DA8 D8 Yes

PE12 D9 D9 D9 DA9 D9 Yes

PE13 D10 D10 D10 DA10 D10 Yes

PE14 D11 D11 D11 DA11 D11 Yes

PE15 D12 D12 D12 DA12 D12 Yes

PD8 D13 D13 D13 DA13 D13 Yes

Doc ID 17143 Rev 2 31/108

Pinouts and pin descriptions STM32F101xF, STM32F101xG

Table 6. FSMC pin definition (continued)

FSMC

Pins

CF CF/IDE

NOR/PSRAM/

SRAM

NOR/PSRAM

Mux

NAND 16 bit

LQFP100

PD9 D14 D14 D14 DA14 D14 Yes

PD10 D15 D15 D15 DA15 D15 Yes

PD11 A16 A16 CLE Yes

PD12 A17 A17 ALE Yes

PD13 A18 A18 Yes

PD14 D0 D0 D0 DA0 D0 Yes

PD15 D1 D1 D1 DA1 D1 Yes

PG2 A12 -

PG3 A13 -

PG4 A14 -

PG5 A15 -

PG6 INT2 -

PG7 INT3 -

PD0 D2 D2 D2 DA2 D2 Yes

(1)

PD1 D3 D3 D3 DA3 D3 Yes

PD3 CLK CLK Yes

PD4 NOE NOE NOE NOE NOE Yes

PD5 NWE NWE NWE NWE NWE Yes

PD6 NWAIT NWAIT NWAIT NWAIT NWAIT Yes

PD7 NE1 NE1 NCE2 Yes

PG9 NE2 NE2 NCE3 -

PG10 NCE4_1 NCE4_1 NE3 NE3 -

PG11 NCE4_2 NCE4_2 -

PG12 NE4 NE4 -

PG13 A24 A24 -

PG14 A25 A25 -

PB7 NADV NADV Yes

PE0 NBL0 NBL0 Yes

PE1 NBL1 NBL1 Yes

1. Ports F and G are not available in devices delivered in 100-pin packages.

32/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Memory mapping

512-Mbyte

block 7

Cortex-M3's

internal

peripherals

512-Mbyte

block 6

Not used

512-Mbyte

block 5

FSMC register

512-Mbyte

block 4

FSMC bank3

& bank4

512-Mbyte

block 3

FSMC bank1

& bank2

512-Mbyte

block 2

Peripherals

512-Mbyte

block 1

SRAM

0x0000 0000

0x1FFF FFFF

0x2000 0000

0x3FFF FFFF

0x4000 0000

0x5FFF FFFF

0x6000 0000

0x7FFF FFFF

0x8000 0000

0x9FFF FFFF

0xA000 0000

0xBFFF FFFF

0xC000 0000

0xDFFF FFFF

0xE000 0000

0xFFFF FFFF

512-Mbyte

block 0

Code

Flash memory bank 1

(512 KB)

0x0810 0000 - 0x1FFF DFFF

0x1FFF E000- 0x1FFF F7FF

0x1FFF F800 - 0x1FFF F80F

0x0800 0000 - 0x0807 FFFF

0x0010 0000 - 0x07FF FFFF

0x0000 0000

0x000F FFFF

System memory

Reserved

Aliased to Flash or system

memory depending on

BOOT pins

SRAM (80 KB aliased

by bit-banding)

Reserved

0x2000 0000 - 0x2001 3FFF

0x2001 4000

0x3FFF FFFF

TIM2

TIM3

0x4000 0000 - 0x4000 03FF

TIM4

TIM5

TIM6

TIM7

Reserved

0x4000 0400 - 0x4000 07FF

0x4000 0800 - 0x4000 0BFF

0x4000 0C00 - 0x4000 0FFF

0x4000 1000 - 0x4000 13FF

0x4000 1400 - 0x4000 17FF

0x4000 2400 - 0x4000 27FF

RTC

0x4000 2800 - 0x4000 2BFF

WWDG

0x4000 2C00 - 0x4000 2FFF

IWDG

0x4000 3000 - 0x4000 33FF

Reserved

0x4000 3400 - 0x4000 37FF

SPI2

0x4000 3800 - 0x4000 3BFF

SPI3

0x4000 3C00 - 0x4000 3FFF

Reserved

0x4000 4000 - 0x4000 43FF

USART2

0x4000 4400 - 0x4000 47FF

0x4000 4800 - 0x4000 4BFF

USART3

UART4

0x4000 4C00 - 0x4000 4FFF

UART5

0x4000 5000 - 0x4000 53FF

I2C1

0x4000 5400 - 0x4000 57FF

I2C2

0x4000 5800 - 0x4000 5BFF

Reserved

0x4000 5C00 - 0x4000 6BFF

BKP

0x4000 6C00 - 0x4000 6FFF

PWR

0x4000 7000 - 0x4000 73FF

DAC

0x4000 7400 - 0x4000 77FF

Reserved

0x4000 7800 - 0x4000 FFFF

AFIO

0x4001 0000 - 0x4001 03FF

Port A

EXTI

0x4001 0400 - 0x4001 07FF

0x4001 0800 - 0x4001 0BFF

Port B

0x4001 0C00 - 0x4001 0FFF

Port C

0x4001 1000 - 0x4001 13FF

Port D

0x4001 1400 - 0x4001 17FF

Port E

0x4001 1800 - 0x4001 1BFF

Port F

0x4001 1C00 - 0x4001 1FFF

Port G

0x4001 2000 - 0x4001 23FF

ADC1

0x4001 2400 - 0x4001 27FF

0x4001 2800 - 0x4001 2FFF

SPI1

0x4001 3000 - 0x4001 33FF

0x4001 3400 - 0x4001 37FF

USART1

0x4001 3800 - 0x4001 3BFF

TIM10

DMA1

0x4002 0000 - 0x4002 03FF

DMA2

0x4002 0400 - 0x4002 07FF

Reserved

0x4002 0400 - 0x4002 0FFF

RCC

0x4002 1000 - 0x4002 13FF

Reserved

0x4002 1400 - 0x4002 1FFF

Flash interfaces 1 & 2

0x4002 2000 - 0x4002 23FF

FSMC bank 1 NOR/PSRAM 1

0x6000 0000 - 0x63FF FFFF

FSMC bank 1 NOR/PSRAM 2

0x6400 0000 - 0x67FF FFFF

FSMC bank 1 NOR/PSRAM 3

0x6800 0000 - 0x6BFF FFFF

FSMC bank 1 NOR/PSRAM 4

0x6C00 0000 - 0x6FFF FFFF

FSMC bank 2 NAND (NAND1)

0x7000 0000 - 0x7FFF FFFF

FSMC bank 3 NAND (NAND2)

0x8000 0000 - 0x8FFF FFFF

FSMC bank 4 PCCARD

0x9000 0000 - 0x9FFF FFFF

FSMC register

0xA000 0000 - 0xA000 0FFF

Reserved

0xA000 1000 - 0xBFFF FFFF

ai15831

Option Bytes

Reserved

0x4001 5400 - 0x4001 57FF

0x4001 5800 - 0x4001 FFFF

TIM11

Reserved

0x4001 5000 - 0x4001 53FF

Reserved

0x4002 3000 - 0x4002 33FF

0x4002 3400 - 0x5FFF FFFF

Reserved

CRC

Reserved

0x4002 2400 - 0x4002 2FFF

TIM9

0x4001 4C00 - 0x4001 4FFF

Reserved

0x4001 3C00 - 0x4001 4BFF

TIM12

TIM13

TIM14

0x4000 1800 - 0x4000 1BFF

0x4000 1C00 - 0x4000 1FFF

0x4000 2000 - 0x4000 23FF

Flash memory bank 2

(256 KB or 512 KB)

0x0808 0000 - 0x080F FFFF

4 Memory mapping

The memory map is shown in Figure 6.

Figure 6. Memory map

Doc ID 17143 Rev 2 33/108

Electrical characteristics STM32F101xF, STM32F101xG

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3).

5.1.2 Typical values

= 25 °C and TA = TAmax (given by

Unless otherwise specified, typical data are based on TA = 25 °C, V 2V V

 3.6 V voltage range). They are given only as design guidelines and are not

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 7.

(mean±2).

= 3.3 V (for the

34/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

ai14123

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STM32F101 PIN

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5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8.

Figure 7. Pin loading conditions Figure 8. Pin input voltage

5.1.6 Power supply scheme

Figure 9. Power supply scheme

Caution: In Figure 9, the 4.7 µF capacitor must be connected to V

Doc ID 17143 Rev 2 35/108

DD3

Electrical characteristics STM32F101xF, STM32F101xG

ai14126

BAT

DDA

IDD_V

BAT

5.1.7 Current consumption measurement

Figure 10. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics,

Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 7. Voltage characteristics

Symbol Ratings Min Max Unit

VDD V

|V

DDx

VSS|

SSX

ESD(HBM)

1. All main power (VDD, V supply, in the permitted range.

2. Positive injection is not possible on these I/Os. VIN maximum must always be respected. I never be exceeded. A negative injection is induced by V

3. I

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I injection is induced by V

External main supply voltage (including

and VDD)

DDA

Input voltage on five volt tolerant pin

Input voltage on any other pin

| Variations between different V

(1)

(2)

(3)

power pins 50

Variations between all the different ground pins

Electrostatic discharge voltage (human body model)

) and ground (VSS, V

DDA

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

while a negative injection is induced by VIN<V

IN>VDD

) pins must always be connected to the external power

SSA

IN<VSS

–0.3 4.0

 0.3 VDD+4 V

VSS 0.3 4.0

see Section 5.3.12: Absolute

maximum ratings (electrical

sensitivity)

INJ(PIN)

value. A positive

must

36/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

Table 8. Current characteristics

Symbol Ratings Max. Unit

(1)

(5)

value. A positive

INJ(PIN)

is the absolute sum of the

INJ(PIN)

150

-5/+0

± 5

± 25

INJ(PIN)

must

VDD

VSS

Total current into VDD/V

Total current out of V

power lines (source)

DDA

ground lines (sink)

Output current sunk by any I/O and control pin 25

INJ(PIN)

I

INJ(PIN)

1. All main power (VDD, V supply, in the permitted range.

2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.18: 12-bit ADC

characteristics.

3. Positive injection is not possible on these I/Os. VIN maximum must always be respected. I never be exceeded. A negative injection is induced by VIN<VSS.

4. I

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.

5. When several inputs are submitted to a current injection, the maximum I positive and negative injected currents (instantaneous values). These results are based on characterization with I

Output current source by any I/Os and control pin  25

Injected current on five volt tolerant pins

(2)

Injected current on any other pin

(3)

(4)

Total injected current (sum of all I/O and control pins)

) and ground (VSS, V

DDA

maximum current injection on four I/O port pins of the device.

INJ(PIN)

) pins must always be connected to the external power

SSA

Table 9. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

Doc ID 17143 Rev 2 37/108

Electrical characteristics STM32F101xF, STM32F101xG

5.3 Operating conditions

5.3.1 General operating conditions

Table 10. General operating conditions

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK1

PCLK2

DDA

Internal AHB clock frequency 0 36

Internal APB1 clock frequency 0 36

Internal APB2 clock frequency 0 36

Standard operating voltage 2 3.6 V

Analog operating voltage (ADC not used)

(1)

Analog operating voltage

Must be the same potential

(2)

as V

(ADC used)

Backup operating voltage 1.8 3.6 V

BAT

23.6

2.4 3.6

MHzf

LQFP144 666

Power dissipation at T

85 °C

(3)

mWLQFP100 434

LQFP64 444

Maximum power dissipation –40 85 °C

A Ambient temperature

Low power dissipation

J Junction temperature range –40 105 °C

1. When the ADC is used, refer to Table 55: ADC characteristics.

2. It is recommended to power VDD and V between VDD and V

3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal

characteristics on page 104).

4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see

Table 6.2: Thermal characteristics on page 104).

can be tolerated during power-up and operation.

DDA

from the same source. A maximum difference of 300 mV

DDA

(4)

–40 105 °C

5.3.2 Operating conditions at power-up / power-down

The parameters given in Tab l e 1 1 are derived from tests performed under the ambient temperature condition summarized in Ta bl e 1 0 .

Table 11. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate 0

VDD

fall time rate 20

5.3.3 Embedded reset and power control block characteristics

The parameters given in Tab l e 1 2 are derived from tests performed under ambient temperature and V

38/108 Doc ID 17143 Rev 2

supply voltage conditions summarized in Tab l e 1 0 .



µs/V



STM32F101xF, STM32F101xG Electrical characteristics

Table 12. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V

PLS[2:0]=000 (falling edge) 2 2.08 2.16 V

PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V

PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V

PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V

PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V

PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V

PVD

Programmable voltage detector level selection

PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V

PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V

PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V

PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V

PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V

PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V

PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V

PLS[2:0]=111 (rising edge) 2.76 2.88 3 V

PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V

(2)

PVDhyst

POR/PDR

PDRhyst

RSTTEMPO

1. The product behavior is guaranteed by design down to the minimum V

2. Guaranteed by design, not tested in production.

PVD hysteresis 100 mV

(1)

Power on/power down reset threshold

(2)

PDR hysteresis 40 mV

(2)

Reset temporization 1.5 2.5 3.5 ms

Falling edge

Rising edge 1.84 1.92 2.0 V

POR/PDR

1.8

value.

1.88 1.96 V

Doc ID 17143 Rev 2 39/108

Electrical characteristics STM32F101xF, STM32F101xG

5.3.4 Embedded reference voltage

The parameters given in Tab l e 1 3 are derived from tests performed under ambient temperature and V

Table 13. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

supply voltage conditions summarized in Tab l e 1 0 .

REFINT

S_vrefint

RERINT

Coeff

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

Internal reference voltage –40 °C < TA < +85 °C 1.16 1.20 1.24 V

ADC sampling time when reading

(1)

the internal reference voltage

Internal reference voltage spread

(2)

over the temperature range

(2)

Temperature coefficient 100

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 10: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

5.1

17.1

= 3 V ±10 mV 10 mV

(2)

µs

ppm/

°C

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned

● The Flash access time is adjusted to f

wait state from 24 to 36 MHz)

● Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

The parameters given in Tab l e 1 4 are derived from tests performed under ambient temperature and V

Table 14. Maximum current consumption in Run mode, code with data processing

supply voltage conditions summarized in Tab l e 1 0 .

running from Flash

40/108 Doc ID 17143 Rev 2

Symbol Parameter Conditions f

HCLK

PCLK1

or VSS (no load)

frequency (0 wait state from 0 to 24 MHz, 1

= f

HCLK/2

, f

PCLK2

HCLK

= f

HCLK

Max

= 85 °C

(1)

Unit

STM32F101xF, STM32F101xG Electrical characteristics

Table 14. Maximum current consumption in Run mode, code with data processing

running from Flash

(1)

Max

Symbol Parameter Conditions f

HCLK

= 85 °C

Unit

36 MHz 41

(2)

External clock

, all

peripherals enabled

Supply current in Run mode

External clock

(2)

, all

peripherals disabled

24 MHz 29

16 MHz 22

8 MHz 12.5

36 MHz 24

24 MHz 17.5

16 MHz 14

8 MHz 8.5

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f

Table 15. Maximum current consumption in Run mode, code with data processing

HCLK

> 8 MHz.

running from RAM

(1)

Max

Symbol Parameter Conditions f

36 MHz 37

External clock

(2)

, all

peripherals enabled

Supply current in Run mode

External clock

(2)

all

peripherals disabled

24 MHz 26.5

16 MHz 19

8 MHz 11.5

36 MHz 20.5

24 MHz 15

16 MHz 11

8 MHz 7.5

HCLK

= 85 °C

Unit

1. Based on characterization, tested in production at V

2. External clock is 8 MHz and PLL is on when f

HCLK

max, f

> 8 MHz.

HCLK

max.

Doc ID 17143 Rev 2 41/108

Electrical characteristics STM32F101xF, STM32F101xG

-45257085

8 MHz

16 MHz

24 MHz

36 MHz

-45 25 70 85

Consumption

8 MHz

16 MHz

24 MHz 36 MHz

Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled

Consumption (mA)

Temperature (°C)

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled

(mA)

Temperat ure (°C)

42/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

Table 16. Maximum current consumption in Sleep mode, code running from Flash

or RAM

(1)

Max

Symbol Parameter Conditions f

36 MHz 27.5

External clock

(2)

all

peripherals enabled

24 MHz 20

16 MHz 15

HCLK

= 85 °C

Unit

Supply current in Sleep mode

External clock

(2)

, all

peripherals disabled

8 MHz 9

36 MHz 6.9

24 MHz 5.9

16 MHz 5.4

8 MHz 4.7

1. Based on characterization, tested in production at V

2. External clock is 8 MHz and PLL is on when f

Table 17. Typical and maximum current consumptions in Stop and Standby modes

HCLK

Symbol Parameter Conditions

max, f

> 8 MHz.

max with peripherals enabled.

HCLK

(1)

Typ

/ V

= 2.0 V

BAT

/ V

BAT

= 2.4 V

DD/VBAT

= 3.3 V

Regulator in Run mode,

Supply current in Stop mode

Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)

Regulator in Low-power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)

Low-speed internal RC oscillator and independent watchdog ON

34.5 35 379

24.5 25 365

33.8

Max

85 °C

Unit

µA

Supply current in Standby mode

Low-speed internal RC oscillator ON, independent watchdog OFF

Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF

DD_VBAT

1. Typical values are measured at TA = 25 °C.

2. Based on characterization, not tested in production.

Backup domain supply current

Low-speed oscillator and RTC ON 1.05 1.1 1.4 2

2.8 3.6

1.9 2.1 5

(2)

Doc ID 17143 Rev 2 43/108

Electrical characteristics STM32F101xF, STM32F101xG

0.5

1.5

2.5

–45 25 85105

Temperature (°C)

Consumption (µA)

1.8 V

2 V

2.4 V

3.3 V

3.6 V

ai17337

100

150

200

250

300

-45 25 70 85

2.4V

2.7V

3.0V

3.3V

3.6V

Figure 13. Typical current consumption on V

different V

BAT

values

with RTC on vs. temperature at

BAT

Figure 14. Typical current consumption in Stop mode with regulator in run mode

versus temperature at different V

values

Consumption (µA)

Temperature (°C)

44/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

100

150

200

250

300

-45 25 70 85

2.4V

2.7V

3.0V

3.3V

3.6V

0.5

1.5

2.5

3.5

-45257085

2.4V

2.7V

3.0V

3.3V

3.6V

Figure 15. Typical current consumption in Stop mode with regulator in low-power

mode versus temperature at different V

Consumption (µA)

values

Temperature (°C)

Figure 16. Typical current consumption in Standby mode versus temperature at

different V

Consumption (µA)

values

Temperature (°C)

Doc ID 17143 Rev 2 45/108

Electrical characteristics STM32F101xF, STM32F101xG

Typical current consumption

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned

● The Flash access time is adjusted to f

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

wait state from 24 to 36 MHz)

● Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

PCLK2

● When the peripherals are enabled f

PCLK1

= f

HCLK/4

HCLK

The parameters given in Tab l e 1 8 are derived from tests performed under ambient temperature and V

Table 18. Typical current consumption in Run mode, code with data processing

supply voltage conditions summarized in Tab l e 1 0 .

running from Flash

Symbol Parameter Conditions f

HCLK

All peripherals

or VSS (no load)

, f

PCLK2

, f

PCLK2

(1)

Typ

enabled

(2)

= f

HCLK/2

HCLK

, f

ADCCLK

, f

ADCCLK

Typ

= f

(1)

All peripherals

disabled

PCLK2

Unit

36 MHz 28.5 18.7

24 MHz 24.1 12.8

16 MHz 14 9.2

8 MHz 7.7 5.4

External

(3)

clock

4 MHz 4.6 3.4

2 MHz 3 2.3

1 MHz 2.2 1.8

500 kHz 1.7 1.5

Supply

current in Run mode

125 kHz 1.4 1.3

36 MHz 27.5 17.5

24 MHz 18.9 11.6

Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency

16 MHz 12.2 8.2

8 MHz 7.2 4.8

4 MHz 4 2.7

2 MHz 2.3 1.7

1 MHz 1.5 1.2

500 kHz 1.1 0.9

125 kHz 0.75 0.7

1. Typical values are measures at TA = 25 °C, V

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

= 3.3 V.

> 8 MHz.

46/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

Table 19. Typical current consumption in Sleep mode, code running from Flash or

RAM

Symbol Parameter Conditions f

External clock

(3)

Supply

current in Sleep mode

Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency

(1)

Typ

HCLK

All peripherals

enabled

(2)

All peripherals

36 MHz 17.7 4

24 MHz 12.2 3.1

16 MHz 8.4 2.3

8 MHz 4.6 1.5

4 MHz 3 1.3

2 MHz 2.15 1.25

1 MHz 1.7 1.2

500 kHz 1.5 1.15

125 kHz 1.35 1.15

36 MHz 17 3.35

24 MHz 11.6 2.3

16 MHz 7.7 1.6

8 MHz 3.9 0.8

4 MHz 2.3 0.7

2 MHz 1.5 0.6

1 MHz 1.1 0.5

(1)

Typ

disabled

Unit

500 kHz 0.9 0.5

125 kHz 0.7 0.5

1. Typical values are measures at TA = 25 °C, V

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

= 3.3 V.

> 8 MHz.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Ta bl e 2 0 . The MCU is placed under the following conditions:

● all I/O pins are in input mode with a static value at V

● all peripherals are disabled unless otherwise mentioned

● the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

● ambient operating temperature and V

supply voltage conditions summarized in

Ta bl e 7 .

or VSS (no load)

Doc ID 17143 Rev 2 47/108

Electrical characteristics STM32F101xF, STM32F101xG

Table 20. Peripheral current consumption

Peripheral Typical consumption at 25 °C

TIM2 0.8

TIM3 0.8

TIM4 0.8

TIM5 0.75

TIM6 0.3

TIM7 0.3

TIM12 0.5

TIM13 0.4

TIM14 0.4

(1)

Unit

APB1

SPI2 0.3

SPI3 0.3

USART2 0.35

USART3 0.35

USART4 0.35

USART5 0.35

I2C1 0.3

I2C2 0.3

CAN 0.45

DAC

(2)

1.05

48/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

Table 20. Peripheral current consumption (continued)

(1)

Unit

APB2

Peripheral Typical consumption at 25 °C

GPIOA 0.35

GPIOB 0.4

GPIOC 0.4

GPIOD 0.4

GPIOE 0.4

GPIOF 0.4

GPIOG 0.4

TIM1 1

TIM8 1

TIM9 0.5

TIM10 0.4

TIM11 0.4

ADC1

ADC2

ADC3

(3)

1.4

SPI1 0.3

USART1 0.6

1. f

2. Specific conditions for DAC: EN1, EN2 bits in the DAC_CR register are set to 1 and the converted value

3. Specific conditions for ADC: f

= 36 MHz, f

HCLK

APB1

= f

HCLK/2

, f

set to 0x800.

in the ADC_CR2 register is set to 1.

HCLK

= f

APB2

= 28 MHz, f

5.3.6 External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Tab l e 2 1 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Ta bl e 1 0 .

, default prescaler value for each peripheral.

HCLK

APB1

= f

HCLK/2

, f

APB2

= f

HCLK

, f

ADCCLK

= f

APB2

/2, ADON bit

Doc ID 17143 Rev 2 49/108

Electrical characteristics STM32F101xF, STM32F101xG

Table 21. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

HSE_ext

HSEH

w(HSE)

r(HSE)

f(HSE)

in(HSE)

DuCy

HSEL

User external clock source frequency

(1)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN input capacitance

Duty cycle 45 55 %

(HSE)

OSC_IN Input leakage current VSS VIN V

(1)

1825MHz

0.7V

5pF

0.3V

±1 µA

1. Guaranteed by design, not tested in production

Low-speed external user clock generated from an external source

The characteristics given in Tab l e 2 2 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Ta bl e 1 0 .

Table 22. Low-speed user external clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

LSE_ext

LSEH

User external clock source frequency

(1)

OSC32_IN input pin high level voltage

0.7V

32.768 1000 kHz

LSEL

w(LSE)

r(LSE)

f(LSE)

in(LSE)

DuCy

1. Guaranteed by design, not tested in production.

OSC32_IN input pin low level voltage

(1)

 VIN V

OSC32_IN high or low time

OSC32_IN rise or fall time

OSC32_IN input capacitance

Duty cycle 30 70 %

(LSE)

OSC32_IN Input leakage

current

(1)

450

0.3V

5pF

±1 µA

50/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

ai14127b

OS C _I N

External clock source

STM32F10xxx

HSEH

f(HSE)

W(HSE)

90%

10%

HSE

r(HSE)

W(HSE)

HSE_ext

HSEL

ai14140c

OSC32_IN

External clock source

STM32F10xxx

LSEH

f(LSE)

W(LSE)

90%

10%

LSE

r(LSE)

W(LSE)

LSE_ext

LSEL

Figure 17. High-speed external clock source AC timing diagram

Figure 18. Low-speed external clock source AC timing diagram

Doc ID 17143 Rev 2 51/108

Electrical characteristics STM32F101xF, STM32F101xG

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Ta bl e 2 3. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 23. HSE 4-16 MHz oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)(2)

OSC_IN

Oscillator frequency 4 8 16 MHz

Feedback resistor 200 k

Recommended load capacitance

versus equivalent serial resistance of the crystal (R

HSE driving current

RS = 30 30 pF

(3)

)

= 3.3 V

VIN = V

with 30 pF

1mA

load

SU(HSE)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization results, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Oscillator transconductance Startup 25 mA/V

(4)

Startup time VDD is stabilized 2 ms

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 19). C

and C

are usually the

same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing C

and CL2. Refer to the application note AN2867 “Oscillator design guide for ST

microcontrollers” available from the ST website www.st.com.

52/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

ai14128b

OSC_OUT

OSC_IN

HSE

STM32F10xxx

8 MHz resonator

Resonator with integrated capacitors

Bias

controlled

gain

EXT

(1)

Figure 19. Typical application with an 8 MHz crystal

1. R

value depends on the crystal characteristics.

EXT

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Ta bl e 2 4. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 24. LSE oscillator characteristics (f

= 32.768 kHz)

LSE

Symbol Parameter Conditions Min Typ Max Unit

Feedback resistor 5 M

Recommended load capacitance

SU(LSE)

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. t

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

versus equivalent serial resistance of the crystal (R

LSE driving current

)

RS = 30 K 15 pF

= 3.3 V

VIN = V

Oscillator transconductance 5 µA/V

(3)

Startup time

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

stabilized

(1) (2)

TA = 50 °C 1.5

= 25 °C 2.5

= 10 °C 4

= 0 °C 6

= -10 °C 10

= -20 °C 17

= -30 °C 32

= -40 °C 60

1.4 µA

Doc ID 17143 Rev 2 53/108

Electrical characteristics STM32F101xF, STM32F101xG

ai14129b

OSC32_OUT

OSC32_IN

LSE

STM32F10xxx

32.768 KHz resonator

Resonator with integrated capacitors

Bias

controlled

gain

Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator. C

and C

L2,

are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C Load capacitance C C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C

and CL2.

stray

where

between 2 pF and 7 pF.

Caution: To avoid exceeding the maximum value of C

to use a resonator with a load capacitance C

capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of C then C

= CL2 = 8 pF.

Figure 20. Typical application with a 32.768 kHz crystal

5.3.7 Internal clock source characteristics

The parameters given in Tab l e 2 5 are derived from tests performed under ambient temperature and V

High-speed internal (HSI) RC oscillator

supply voltage conditions summarized in Tab l e 1 0 .

and CL2 (15 pF) it is strongly recommended



7 pF. Never use a resonator with a load

= 6 pF, and C

stray

= 2 pF,

54/108 Doc ID 17143 Rev 2

Table 25. HSI oscillator characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

Frequency 8 MHz

Duty cycle 45 55 %

(HSI)

User-trimmed with the RCC_CR

(2)

Accuracy of the HSI

HSI

oscillator

Factorycalibrated

HSI oscillator startup

(4)

time

HSI oscillator power

(4)

consumption

= 3.3 V, TA = –40 to 85 °C unless otherwise specified.

TA = –40 to 105 °C –2 2.5 %

= –10 to 85 °C –1.5 2.2 %

(4)

= 0 to 70 °C –1.3 2 %

= 25 °C –1.1 1.8 %

12µs

80 100 µA

DuCy

ACC

su(HSI)

DD(HSI)

1. V

HSI

(3)

STM32F101xF, STM32F101xG Electrical characteristics

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from

the ST website www.st.com.

3. Guaranteed by design, not tested in production.

4. Based on characterization, not tested in production.

Low-speed internal (LSI) RC oscillator

Table 26. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

(2)

LSI

su(LSI)

DD(LSI)

1. V

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Frequency 30 40 60 kHz

(3)

LSI oscillator startup time 85 µs

(3)

LSI oscillator power consumption 0.65 1.2 µA

= 3 V, TA = –40 to 85 °C unless otherwise specified.

(1)

Wakeup time from low-power mode

The wakeup times given in Tab le 2 7 are measured on a wakeup phase with an 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

● Stop or Standby mode: the clock source is the RC oscillator

● Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V

supply

voltage conditions summarized in Tabl e 1 0.

Table 27. Low-power mode wakeup timings

Symbol Parameter Typ Unit

(1)

WUSLEEP

WUSTOP

WUSTDBY

1. The wakeup times are measured from the wakeup event to the point at which the user application code

reads the first instruction.

Wakeup from Sleep mode 1.8 µs

Wakeup from Stop mode (regulator in run mode) 3.6

(1)

Wakeup from Stop mode (regulator in low-power mode) 5.4

(1)

Wakeup from Standby mode 50 µs

µs

Doc ID 17143 Rev 2 55/108

Electrical characteristics STM32F101xF, STM32F101xG

5.3.8 PLL characteristics

The parameters given in Tab l e 2 8 are derived from tests performed under ambient temperature and V

Table 28. PLL characteristics

Symbol Parameter

PLL_IN

PLL_OUT

LOCK

Jitter Cycle-to-cycle jitter 300 ps

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

the range defined by f

supply voltage conditions summarized in Tab l e 1 0 .

Val ue

(1)

Unit

PLL input clock

(2)

Min

(1)

Typ Max

18.025MHz

PLL input clock duty cycle 40 60 %

PLL multiplier output clock 16 36 MHz

PLL lock time 200 µs

PLL_OUT

5.3.9 Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 85 °C unless otherwise specified.

Table 29. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max

prog

ERASE

16-bit programming time TA–40 to +85 °C 40 52.5 70 µs

Page (2 KB) erase time TA –40 to +85 °C 20 40 ms

Mass erase time TA –40 to +85 °C 20 40 ms

Read mode

= 36 MHz with 1

HCLK

wait state, V

= 3.3 V

Write mode

= 36 MHz, VDD =

HCLK

Supply current

3.3 V

Erase mode

= 36 MHz, VDD =

HCLK

3.3 V

Power-down mode / Halt,

= 3.0 to 3.6 V

prog

1. Guaranteed by design, not tested in production.

Programming voltage 2 3.6 V

(1)

Unit

28 mA

7mA

5mA

50 µA

56/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

Table 30. Flash memory endurance and data retention

Val ue

Symbol Parameter Conditions

Min

(1)

Unit

RET

END

Endurance TA = –40 °C to 85 °C

Data retention

1. Based on characterization, not tested in production.

2. Cycling performed over the whole temperature range.

5.3.10 FSMC characteristics

Asynchronous waveforms and timings

Figure 21 through Figure 24 represent asynchronous waveforms and Tab le 3 1 through Ta bl e 3 4 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

● AddressSetupTime = 0

● AddressHoldTime = 1

● DataSetupTime = 1

= 85 °C, 1 kcycle

= 55 °C, 10 kcycle

(2)

kcycles

Years

Doc ID 17143 Rev 2 57/108

Electrical characteristics STM32F101xF, STM32F101xG

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Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

Symbol Parameter Min Max Unit

w(NE)

v(NOE_NE)

w(NOE)

h(NE_NOE)

v(A_NE)

h(A_NOE)

v(BL_NE)

h(BL_NOE)

su(Data_NE)

su(Data_NOE)

h(Data_NOE)

h(Data_NE)

58/108 Doc ID 17143 Rev 2

FSMC_NE low time 5T

FSMC_NEx low to FSMC_NOE low 0.5 1.5 ns

FSMC_NOE low time 5T

FSMC_NOE high to FSMC_NE high hold time –1.5 ns

FSMC_NEx low to FSMC_A valid 7 ns

Address hold time after FSMC_NOE high 0.1 ns

FSMC_NEx low to FSMC_BL valid 0 ns

FSMC_BL hold time after FSMC_NOE high 0 ns

Data to FSMC_NEx high setup time 2T

Data to FSMC_NOEx high setup time 2T

Data hold time after FSMC_NOE high 0 ns

Data hold time after FSMC_NEx high 0 ns

– 1.5 5T

HCLK

– 1.5 5T

HCLK

+ 25 ns

HCLK

+ 25 ns

HCLK

(1) (2)

+ 2 ns

+ 1.5 ns

STM32F101xF, STM32F101xG Electrical characteristics

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

(1) (2)

Symbol Parameter Min Max Unit

v(NADV_NE)

w(NADV)

1. CL = 15 pF.

2. Preliminary values.

FSMC_NEx low to FSMC_NADV low 5 ns

FSMC_NADV low time T

+ 1.5 ns

HCLK

Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

w(NE)

FSMC_NEx

FSMC_NOE

Address

NBL

w(NWE)

h(Data_NWE)

h(A_NWE)

h(BL_NWE)

Data

h(NE_NWE)

FSMC_NWE

FSMC_A[25:0]

FSMC_NBL[1:0]

FSMC_D[15:0]

FSMC_NADV

v(NWE_NE)

v(A_NE)

v(BL_NE)

v(Data_NE)

v(NADV_NE)

(1)

w(NADV)

ai14990

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

(1)(2)

Symbol Parameter Min Max Unit

w(NE)

v(NWE_NE)

w(NWE)

h(NE_NWE)

v(A_NE)

h(A_NWE)

v(BL_NE)

h(BL_NWE)

v(Data_NE)

h(Data_NWE)

FSMC_NE low time 3T

FSMC_NEx low to FSMC_NWE low T

FSMC_NWE low time T

FSMC_NWE high to FSMC_NE high hold time T

FSMC_NEx low to FSMC_A valid 7.5 ns

Address hold time after FSMC_NWE high T

FSMC_NEx low to FSMC_BL valid 1.5 ns

FSMC_BL hold time after FSMC_NWE high T

FSMC_NEx low to Data valid T

Data hold time after FSMC_NWE high T

– 1 3T

HCLK

– 0.5 T

HCLK

– 0.5 T

HCLK

– 0.5 ns

HCLK

+ 2 ns

+ 1.5 ns

+ 7 ns

Doc ID 17143 Rev 2 59/108

Electrical characteristics STM32F101xF, STM32F101xG

NBL

Data

FSMC_NBL[1:0]

FSMC_

AD[15:0]

v(BL_NE)

h(Data_NE)

Address

FSMC_A[25:16]

v(A_NE)

FSMC_NWE

v(A_NE)

ai14892b

Address

FSMC_NADV

v(NADV_NE)

w(NADV)

su(Data_NE)

h(AD_NADV)

FSMC_NE

FSMC_NOE

w(NE)

w(NOE)

v(NOE_NE)

h(NE_NOE)

h(A_NOE)

h(BL_NOE)

su(Data_NOE)

h(Data_NOE)

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

Symbol Parameter Min Max Unit

v(NADV_NE)

w(NADV)

1. CL = 15 pF.

2. Preliminary values.

FSMC_NEx low to FSMC_NADV low 5.5 ns

FSMC_NADV low time T

+ 1.5 ns

HCLK

Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms

(1)(2)

Table 33. Asynchronous multiplexed NOR/PSRAM read timings

Symbol Parameter Min Max Unit

60/108 Doc ID 17143 Rev 2

w(NE)

v(NOE_NE)

w(NOE)

h(NE_NOE)

v(A_NE)

v(NADV_NE)

w(NADV)

h(AD_NADV)

h(A_NOE)

FSMC_NE low time 7T

FSMC_NEx low to FSMC_NOE low 3T

FSMC_NOE low time 4T

FSMC_NOE high to FSMC_NE high hold time –1 ns

FSMC_NEx low to FSMC_A valid 0 ns

FSMC_NEx low to FSMC_NADV low 3 5 ns

FSMC_NADV low time T

FSMC_AD (address) valid hold time after FSMC_NADV high

Address hold time after FSMC_NOE high T

HCLK

–1.5 T

(1)(2)

– 2 7T

– 0.5 3T

– 1 4T

HCLK

+ 2 ns

+ 1.5 ns

+ 2 ns

+ 1.5 ns

STM32F101xF, STM32F101xG Electrical characteristics

Table 33. Asynchronous multiplexed NOR/PSRAM read timings

(1)(2)

(continued)

Symbol Parameter Min Max Unit

h(BL_NOE)

v(BL_NE)

su(Data_NE)

su(Data_NOE)

h(Data_NE)

h(Data_NOE)

1. CL = 15 pF.

2. Preliminary values.

FSMC_BL hold time after FSMC_NOE high 0 ns

FSMC_NEx low to FSMC_BL valid 0 ns

Data to FSMC_NEx high setup time 2T

Data to FSMC_NOE high setup time 2T

+ 24 ns

HCLK

+ 25 ns

HCLK

Data hold time after FSMC_NEx high 0 ns

Data hold time after FSMC_NOE high 0 ns

Doc ID 17143 Rev 2 61/108

Electrical characteristics STM32F101xF, STM32F101xG

NBL

Data

FSMC_NEx

FSMC_NBL[1:0]

FSMC_

AD[15:0]

v(BL_NE)

h(Data_NWE)

FSMC_NOE

Address

FSMC_A[25:16]

v(A_NE)

w(NWE)

FSMC_NWE

v(NWE_NE)

h(NE_NWE)

h(A_NWE)

h(BL_NWE)

v(A_NE)

w(NE)

ai14891B

Address

FSMC_NADV

v(NADV_NE)

w(NADV)

v(Data_NADV)

h(AD_NADV)

Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms

62/108 Doc ID 17143 Rev 2

Table 34. Asynchronous multiplexed NOR/PSRAM write timings

(1)(2)

Symbol Parameter Min Max Unit

w(NE)

v(NWE_NE)

w(NWE)

h(NE_NWE)

v(A_NE)

v(NADV_NE)

w(NADV)

h(AD_NADV)

h(A_NWE)

v(BL_NE)

h(BL_NWE)

v(Data_NADV)

h(Data_NWE)

1. C

= 15 pF.

2. Preliminary values.

FSMC_NE low time 5T

FSMC_NEx low to FSMC_NWE low 2T

FSMC_NWE low time 2T

FSMC_NWE high to FSMC_NE high hold time T

FSMC_NEx low to FSMC_A valid 7 ns

FSMC_NEx low to FSMC_NADV low 3 5 ns

FSMC_NADV low time T

FSMC_AD (address) valid hold time after FSMC_NADV high

Address hold time after FSMC_NWE high 4T

FSMC_NEx low to FSMC_BL valid 1.6 ns

FSMC_BL hold time after FSMC_NWE high T

FSMC_NADV high to Data valid T

Data hold time after FSMC_NWE high T

– 1 5T

HCLK

– 1 2T

HCLK

– 1 ns

HCLK

– 1 T

HCLK

– 3 ns

HCLK

– 1.5 ns

HCLK

– 5 ns

HCLK

+ 2 ns

+ 1 ns

+ 2 ns

+ 1 ns

+ 1.5 ns

STM32F101xF, STM32F101xG Electrical characteristics

Synchronous waveforms and timings

Figure 25 through Figure 28 represent synchronous waveforms and Ta bl e 3 6 through Ta bl e 3 8 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

● BurstAccessMode = FSMC_BurstAccessMode_Enable;

● MemoryType = FSMC_MemoryType_CRAM;

● WriteBurst = FSMC_WriteBurst_Enable;

● CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)

● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

Figure 25. Synchronous multiplexed NOR/PSRAM read timings

w(CLK)

FSMC_CLK

FSMC_NEx

d(CLKL-NADVL)

FSMC_NADV

FSMC_A[25:16]

FSMC_NOE

d(CLKL-ADIV)

d(CLKL-ADV)

FSMC_AD[15:0]

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

w(CLK)

Data latency = 1

d(CLKL-NExL)

d(CLKL-NADVH)

d(CLKL-AV)

d(CLKL-NOEL)

su(ADV-CLKH)

d(CLKH-NExH)

d(CLKH-NOEH)

h(CLKH-ADV)

AD[15:0] D1 D2

su(NWAITV-CLKH)

h(CLKH-NWAITV)

BUSTURN = 0

d(CLKH-AIV)

h(CLKH-ADV)

h(CLKH-NWAITV)

ai14893e

Doc ID 17143 Rev 2 63/108

Electrical characteristics STM32F101xF, STM32F101xG

Table 35. Synchronous multiplexed NOR/PSRAM read timings

(1)(2)

Symbol Parameter Min Max Unit

w(CLK)

d(CLKL-NExL)

d(CLKH-NExH)

d(CLKL-NADVL)

d(CLKL-NADVH)

d(CLKL-AV)

d(CLKH-AIV)

d(CLKL-NOEL)

d(CLKH-NOEH)

d(CLKL-ADV)

d(CLKL-ADIV)

su(ADV-CLKH)

h(CLKH-ADV)

su(NWAITV-CLKH)

h(CLKH-NWAITV)

= 15 pF.

1. C

2. Preliminary values.

FSMC_CLK period 27.7 ns

FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns

FSMC_CLK high to FSMC_NEx high (x = 0...2) T

+ 2 ns

HCLK

FSMC_CLK low to FSMC_NADV low 4 ns

FSMC_CLK low to FSMC_NADV high 5 ns

FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns

FSMC_CLK high to FSMC_Ax invalid (x = 16...25) T

FSMC_CLK low to FSMC_NOE low T

FSMC_CLK high to FSMC_NOE high T

+ 2 ns

HCLK

+ 0.5 ns

HCLK

FSMC_CLK low to FSMC_AD[15:0] valid 12 ns

FSMC_CLK low to FSMC_AD[15:0] invalid 0 ns

FSMC_A/D[15:0] valid data before FSMC_CLK high

FSMC_A/D[15:0] valid data after FSMC_CLK high T

6 ns

– 10 ns

HCLK

FSMC_NWAIT valid before FSMC_CLK high 8 ns

FSMC_NWAIT valid after FSMC_CLK high 2 ns

+1 ns

64/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

FSMC_CLK

FSMC_NEx

FSMC_NADV

FSMC_A[25:16]

FSMC_NWE

FSMC_AD[15:0]

AD[15:0] D1 D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

w(CLK)

Data latency = 1

BUSTURN = 0

d(CLKL-NExL)

d(CLKH-NExH)

d(CLKL-NADVL)

d(CLKL-AV)

d(CLKL-NADVH)

d(CLKH-AIV)

d(CLKH-NWEH)

d(CLKL-NWEL)

d(CLKL-NBLH)

d(CLKL-ADV)

d(CLKL-ADIV)

d(CLKL-Data)

su(NWAITV-CLKH)

h(CLKH-NWAITV)

ai14992d

d(CLKL-Data)

FSMC_NBL

Figure 26. Synchronous multiplexed PSRAM write timings

Doc ID 17143 Rev 2 65/108

Electrical characteristics STM32F101xF, STM32F101xG

Table 36. Synchronous multiplexed PSRAM write timings

(1)(2)

Symbol Parameter Min Max Unit

w(CLK)

d(CLKL-NExL)

d(CLKH-NExH)

d(CLKL-NADVL)

d(CLKL-NADVH)

d(CLKL-AV)

d(CLKH-AIV)

d(CLKL-NWEL)

d(CLKH-NWEH)

d(CLKL-ADV)

d(CLKL-ADIV)

d(CLKL-Data)

su(NWAITV-CLKH)

h(CLKH-NWAITV)

d(CLKL-NBLH)

1. C

= 15 pF.

2. Preliminary values.

FSMC_CLK period 27.7 ns

FSMC_CLK low to FSMC_Nex low (x = 0...2) 2 ns

FSMC_CLK high to FSMC_NEx high (x = 0...2) T

+ 2 ns

HCLK

FSMC_CLK low to FSMC_NADV low 4 ns

FSMC_CLK low to FSMC_NADV high 5 ns

FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns

FSMC_CLK high to FSMC_Ax invalid (x = 16...25) TCK + 2 ns

FSMC_CLK low to FSMC_NWE low 1 ns

FSMC_CLK high to FSMC_NWE high T

+1 ns

HCLK

FSMC_CLK low to FSMC_AD[15:0] valid 12 ns

FSMC_CLK low to FSMC_AD[15:0] invalid 3 ns

FSMC_A/D[15:0] valid after FSMC_CLK low 6 ns

FSMC_NWAIT valid before FSMC_CLK high 7 ns

FSMC_NWAIT valid after FSMC_CLK high 2 ns

FSMC_CLK low to FSMC_NBL high 1 ns

66/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

FSMC_CLK

FSMC_NEx

FSMC_A[25:0]

FSMC_NOE

FSMC_D[15:0]

D1 D2

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

w(CLK)

Data latency = 1

BUSTURN = 0

d(CLKL-NExL)

d(CLKH-NExH)

d(CLKL-AV)

d(CLKH-AIV)

d(CLKL-NOEL)

d(CLKH-NOEH)

su(DV-CLKH)

h(CLKH-DV)

su(DV-CLKH)

h(CLKH-DV)

su(NWAITV-CLKH)

h(CLKH-NWAITV)

su(NWAITV-CLKH)

h(CLKH-NWAITV)

su(NWAITV-CLKH)

h(CLKH-NWAITV)

ai14894d

FSMC_NADV

d(CLKL-NADVL)

d(CLKL-NADVH)

Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings

Table 37. Synchronous non-multiplexed NOR/PSRAM read timings

Symbol Parameter Min Max Unit

w(CLK)

d(CLKL-NExL)

d(CLKH-NExH)

d(CLKL-NADVL)

d(CLKL-NADVH)

d(CLKL-AV)

d(CLKH-AIV)

d(CLKL-NOEL)

d(CLKH-NOEH)

su(DV-CLKH)

h(CLKH-DV)

su(NWAITV-CLKH)

h(CLKH-NWAITV)

1. C

= 15 pF.

2. Preliminary values.

FSMC_CLK period 27.7 ns

FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns

FSMC_CLK high to FSMC_NEx high (x = 0...2) T

HCLK

FSMC_CLK low to FSMC_NADV low 4 ns

FSMC_CLK low to FSMC_NADV high 5 ns

FSMC_CLK low to FSMC_Ax valid (x = 0...25) 0 ns

FSMC_CLK high to FSMC_Ax invalid (x = 0...25) T

HCLK

FSMC_CLK low to FSMC_NOE low T

FSMC_CLK high to FSMC_NOE high T

HCLK

FSMC_D[15:0] valid data before FSMC_CLK high 6.5 ns

FSMC_D[15:0] valid data after FSMC_CLK high 7 ns

FSMC_NWAIT valid before FSMC_SMCLK high 7 ns

FSMC_NWAIT valid after FSMC_CLK high 2 ns

Doc ID 17143 Rev 2 67/108

(1)(2)

+ 2 ns

+ 4 ns

+ 1.5 ns

HCLK

+ 1.5 ns

Electrical characteristics STM32F101xF, STM32F101xG

Figure 28. Synchronous non-multiplexed PSRAM write timings

BUSTURN = 0

FSMC_CLK

w(CLK)

d(CLKL-NExL)

Data latency = 1

d(CLKH-NExH)

FSMC_NEx

d(CLKL-NADVL)

d(CLKL-NADVH)

FSMC_NADV

d(CLKL-AV)

d(CLKH-AIV)

FSMC_A[25:0]

d(CLKL-NWEL)

d(CLKH-NWEH)

FSMC_NWE

d(CLKL-Data)

FSMC_D[15:0]

d(CLKL-Data)

D1 D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

su(NWAITV-CLKH)

d(CLKL-NBLH)

h(CLKH-NWAITV)

FSMC_NBL

Table 38. Synchronous non-multiplexed PSRAM write timings

(1)(2)

Symbol Parameter Min Max Unit

ai14993e

w(CLK)

d(CLKL-NExL)

d(CLKH-NExH)

d(CLKL-NADVL)

d(CLKL-NADVH)

d(CLKL-AV)

d(CLKH-AIV)

d(CLKL-NWEL)

d(CLKH-NWEH)

d(CLKL-Data)

su(NWAITV-CLKH)

h(CLKH-NWAITV)

d(CLKL-NBLH)

1. C

= 15 pF.

FSMC_CLK period 27.7 ns

FSMC_CLK low to FSMC_NEx low (x = 0...2) 2 ns

FSMC_CLK high to FSMC_NEx high (x = 0...2) T

FSMC_CLK low to FSMC_NADV low 4 ns

FSMC_CLK low to FSMC_NADV high 5 ns

FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns

FSMC_CLK high to FSMC_Ax invalid (x = 16...25) TCK + 2 ns

FSMC_CLK low to FSMC_NWE low 1 ns

FSMC_CLK high to FSMC_NWE high T

FSMC_D[15:0] valid data after FSMC_CLK low 6 ns

FSMC_NWAIT valid before FSMC_CLK high 7 ns

FSMC_NWAIT valid after FSMC_CLK high 2 ns

FSMC_CLK low to FSMC_NBL high 1 ns

2. Preliminary values.

68/108 Doc ID 17143 Rev 2

+ 2 ns

HCLK

+ 1 ns

HCLK

STM32F101xF, STM32F101xG Electrical characteristics

PC Card/CompactFlash controller waveforms and timings

Figure 29 through Figure 34 represent synchronous waveforms and Ta bl e 3 9 provides the

corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

● COM.FSMC_SetupTime = 0x04;

● COM.FSMC_WaitSetupTime = 0x07;

● COM.FSMC_HoldSetupTime = 0x04;

● COM.FSMC_HiZSetupTime = 0x00;

● ATT.FSMC_SetupTime = 0x04;

● ATT.FSMC_WaitSetupTime = 0x07;

● ATT.FSMC_HoldSetupTime = 0x04;

● ATT.FSMC_HiZSetupTime = 0x00;

● IO.FSMC_SetupTime = 0x04;

● IO.FSMC_WaitSetupTime = 0x07;

● IO.FSMC_HoldSetupTime = 0x04;

● IO.FSMC_HiZSetupTime = 0x00;

● TCLRSetupTime = 0;

● TARSetupTime = 0;

Figure 29. PC Card/CompactFlash controller waveforms for common memory read

access

FSMC_NCE4_2

FSMC_NCE4_1

FSMC_A[10:0]

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

FSMC_NWE

FSMC_N

FSMC_D[15:0]

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

(1)

d(NCE4_1-NOE)

v(NCEx-A)

d(NREG-NCEx)

d(NIORD-NCEx)

w(NOE)

su(D-NOE)

h(NCEx-AI)

h(NCEx-NREG)

h(NCEx-NIORD)

h(NCEx-

NIOWR

h(NOE-D)

)

ai14895b

Doc ID 17143 Rev 2 69/108

Electrical characteristics STM32F101xF, STM32F101xG

d(NCE4_1-NWE)

w(NWE)

h(NWE-D)

v(NCE4_1-A)

d(NREG-NCE4_1)

d(NIORD-NCE4_1)

h(NCE4_1-AI)

MEMxHIZ =1

v(NWE-D)

h(NCE4_1-NREG)

h(NCE4_1-NIORD)

h(NCE4_1-NIOWR)

ai14896b

FSMC_NWE

FSMC_N

FSMC_D[15:0]

FSMC_A[10:0]

FSMC_NCE4_1

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

d(NWE-NCE4_1)

d(D-NWE)

FSMC_NCE4_2

High

Figure 30. PC Card/CompactFlash controller waveforms for common memory write

access

70/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

d(NCE4_1-NOE)

w(NOE)

su(D-NOE)

h(NOE-D)

v(NCE4_1-A)

h(NCE4_1-AI)

d(NREG-NCE4_1)

h(NCE4_1-NREG)

ai14897b

FSMC_NWE

FSMC_NOE

FSMC_D[15:0]

(1)

FSMC_A[10:0]

FSMC_NCE4_2

FSMC_NCE4_1

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

d(NOE-NCE4_1)

High

Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read

access

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

Doc ID 17143 Rev 2 71/108

Electrical characteristics STM32F101xF, STM32F101xG

Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write

access

FSMC_NCE4_1

FSMC_NCE4_2

High

v(NCE4_1-A)

h(NCE4_1-AI)

FSMC_A[10:0]

FSMC_NIOWR

FSMC_NIORD

d(NREG-NCE4_1)

h(NCE4_1-NREG)

FSMC_NREG

d(NCE4_1-NWE)

w(NWE)

FSMC_NWE

d(NWE-NCE4_1)

FSMC_NOE

v(NWE-D)

FSMC_D[7:0](1)

ai14898b

1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).

Figure 33. PC Card/CompactFlash controller waveforms for I/O space read access

FSMC_NCE4_1

FSMC_NCE4_2

v(NCEx-A)

FSMC_A[10:0]

FSMC_NREG

FSMC_NWE

FSMC_NOE

FSMC_NIOWR

d(NIORD-NCE4_1)

FSMC_NIORD

FSMC_D[15:0]

72/108 Doc ID 17143 Rev 2

su(D-NIORD)

h(NCE4_1-AI)

w(NIORD)

d(NIORD-D)

ai14899B

STM32F101xF, STM32F101xG Electrical characteristics

d(NCE4_1-NIOWR)

w(NIOWR)

v(NCEx-A)

h(NCE4_1-AI)

h(NIOWR-D)

ATTxHIZ =1

v(NIOWR-D)

ai14900b

FSMC_NWE

FSMC_NOE

FSMC_D[15:0]

FSMC_A[10:0]

FSMC_NCE4_2

FSMC_NCE4_1

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access

Table 39. Switching characteristics for PC Card/CF read and write cycles

(1)(2)

Symbol Parameter Min Max Unit

FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y =

v(NCEx-A)

v(NCE4_1-A)

0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y =

0 ns

0...10)

FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x =

h(NCEx-AI)

h(NCE4_1-AI)

0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x

2.5 ns

= 0...10)

d(NREG-NCEx)

d(NREG-NCE4_1)

h(NCEx-NREG)

h(NCE4_1-NREG)

d(NCE4_1-NOE)

w(NOE)

d(NOE-NCE4_1

su(D-NOE)

h(NOE-D)

w(NWE)

d(NWE-NCE4_1)

d(NCE4_1-NWE)

v(NWE-D)

h(NWE-D)

FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid

FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 high to FSMC_NREG invalid

HCLK

FSMC_NCE4_1 low to FSMC_NOE low 5T

FSMC_NOE low width 8T

FSMC_NOE high to FSMC_NCE4_1 high 5T

HCLK

+ 3 ns

5 ns

HCLK

–1.5 8T

HCLK

+ 2 ns

FSMC_D[15:0] valid data before FSMC_NOE high 25 ns

FSMC_D[15:0] valid data after FSMC_NOE high 15 ns

FSMC_NWE low width 8T

FSMC_NWE high to FSMC_NCE4_1 high 5T

FSMC_NCE4_1 low to FSMC_NWE low 5T

– 1 8T

HCLK

+ 2 ns

HCLK

FSMC_NWE low to FSMC_D[15:0] valid 0 ns

FSMC_NWE high to FSMC_D[15:0] invalid 11T

Doc ID 17143 Rev 2 73/108

HCLK

+ 2 ns

+ 1 ns

+ 2 ns

+ 1.5 ns

Electrical characteristics STM32F101xF, STM32F101xG

Table 39. Switching characteristics for PC Card/CF read and write cycles

(1)(2)

(continued)

Symbol Parameter Min Max Unit

d(D-NWE)

w(NIOWR)

v(NIOWR-D)

h(NIOWR-D)

d(NCE4_1-NIOWR)

h(NCEx-NIOWR)

h(NCE4_1-NIOWR)

d(NIORD-NCEx)

d(NIORD-NCE4_1)

h(NCEx-NIORD)

h(NCE4_1-NIORD)

su(D-NIORD)

d(NIORD-D)

w(NIORD)

1. CL = 15 pF.

2. Preliminary values.

FSMC_D[15:0] valid before FSMC_NWE high 13T

FSMC_NIOWR low width 8T

FSMC_NIOWR low to FSMC_D[15:0] valid 5T

FSMC_NIOWR high to FSMC_D[15:0] invalid 11T

FSMC_NCE4_1 low to FSMC_NIOWR valid 5T

FSMC_NCEx high to FSMC_NIOWR invalid FSMC_NCE4_1 high to FSMC_NIOWR invalid

FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1 low to FSMC_NIORD valid

FSMC_NCEx high to FSMC_NIORD invalid FSMC_NCE4_1 high to FSMC_NIORD invalid

HCLK

+ 3 ns

HCLK

– 5 ns

HCLK

– 5 ns

HCLK

FSMC_D[15:0] valid before FSMC_NIORD high 4.5 ns

FSMC_D[15:0] valid after FSMC_NIORD high 9 ns

FSMC_NIORD low width 8T

+ 2 ns

HCLK

+1 ns

+3ns ns

+ 2.5 ns

NAND controller waveforms and timings

Figure 35 through Figure 38 represent synchronous waveforms and Ta bl e 4 0 provides the

corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

● COM.FSMC_SetupTime = 0x01;

● COM.FSMC_WaitSetupTime = 0x03;

● COM.FSMC_HoldSetupTime = 0x02;

● COM.FSMC_HiZSetupTime = 0x01;

● ATT.FSMC_SetupTime = 0x01;

● ATT.FSMC_WaitSetupTime = 0x03;

● ATT.FSMC_HoldSetupTime = 0x02;

● ATT.FSMC_HiZSetupTime = 0x01;

● Bank = FSMC_Bank_NAND;

● MemoryDataWidth = FSMC_MemoryDataWidth_16b;

● ECC = FSMC_ECC_Enable;

● ECCPageSize = FSMC_ECCPageSize_512Bytes;

● TCLRSetupTime = 0;

● TARSetupTime = 0;

74/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

FSMC_NWE

FSMC_NOE (NRE)

FSMC_D[15:0]

su(D-NOE)

h(NOE-D)

ai14901b

ALE (FSMC_A17) CLE (FSMC_A16)

FSMC_NCEx

Low

d(ALE-NOE)th(NOE-ALE)

h(NWE-D)

v(NWE-D)

ai14902b

FSMC_NWE

FSMC_NOE (NRE)

FSMC_D[15:0]

ALE (FSMC_A17) CLE (FSMC_A16)

FSMC_NCEx

Low

d(ALE-NWE)th(NWE-ALE)

Figure 35. NAND controller waveforms for read access

Figure 36. NAND controller waveforms for write access

Figure 37. NAND controller waveforms for common memory read access

FSMC_NCEx

ALE (FSMC_A17) CLE (FSMC_A16)

FSMC_NWE

FSMC_N

FSMC_D[15:0]

Low

d(ALE-NOE)

w(NOE)

su(D-NOE)

h(NOE-ALE)

h(NOE-D)

Doc ID 17143 Rev 2 75/108

ai14912b

Electrical characteristics STM32F101xF, STM32F101xG

w(NWE)

h(NWE-D)

v(NWE-D)

ai14913b

FSMC_NWE

FSMC_N

FSMC_D[15:0]

d(D-NWE)

ALE (FSMC_A17) CLE (FSMC_A16)

FSMC_NCEx

Low

d(ALE-NOE)

h(NOE-ALE)

Figure 38. NAND controller waveforms for common memory write access

Table 40. Switching characteristics for NAND Flash read and write cycles

(1)

Symbol Parameter Min Max Unit

(2)

d(D-NWE)

w(NOE)

su(D-NOE)

h(NOE-D)

w(NWE)

v(NWE-D)

h(NWE-D)

d(ALE-NWE)

h(NWE-ALE)

d(ALE-NOE)

h(NOE-ALE)

= 15 pF.

1. C

(2)

FSMC_D[15:0] valid before FSMC_NWE high 6T

FSMC_NOE low width 4T

FSMC_D[15:0] valid data before FSMC_NOE

(2)

high

(2)

FSMC_D[15:0] valid data after FSMC_NOE high 7 ns

FSMC_NWE low width 4T

(2)

FSMC_NWE low to FSMC_D[15:0] valid 0 ns

(2)

FSMC_NWE high to FSMC_D[15:0] invalid 10T

(3)

FSMC_ALE valid before FSMC_NWE low 3T

(3)

FSMC_NWE high to FSMC_ALE invalid 3T

(3)

FSMC_ALE valid before FSMC_NOE low 3T

(3)

FSMC_NWE high to FSMC_ALE invalid 3T

2. Preliminary values.

3. Guaranteed by design, not tested in production.

+ 12 ns

HCLK

– 1.5 4T

HCLK

+ 1.5 ns

25 ns

– 1 4T

HCLK

+ 4 ns

HCLK

+ 4.5 ns

HCLK

+ 4.5 ns

HCLK

+ 2.5 ns

+ 1.5 ns

+ 2 ns

76/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Tab l e 41 . They are based on the EMS levels and classes defined in application note AN1709.

Table 41. EMS characteristics

Symbol Parameter Conditions Level/Class

and

3.3 V, LQFP144,

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on VDD and V

pins to induce a functional disturbance

TA +25 °C, f

HCLK

 36 MHz

conforms to IEC 61000-4-2

VDD3.3 V, LQFP144, TA +25 °C, f

HCLK

36 MHz

conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

● Corrupted program counter

● Unexpected reset

● Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Doc ID 17143 Rev 2 77/108

Electrical characteristics STM32F101xF, STM32F101xG

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Table 42. EMI characteristics

Symbol Parameter Conditions

Monitored

frequency band

0.1 MHz to 30 MHz 8

3.3 V, TA 25 °C,

EMI

Peak level

LQFP144 package compliant with IEC 61967-2

130 MHz to 1 GHz 26

SAE EMI Level 4 -

5.3.12 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 43. ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum value

Max vs. [f

8/36 MHz

HSE/fHCLK

]

Unit

dBµV30 MHz to 130 MHz 27

(1)

Unit

ESD(HBM)

ESD(CDM)

1. Based on characterization results, not tested in production.

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78 IC latch-up standard.

78/108 Doc ID 17143 Rev 2

Table 44. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class T

TA +25 °C, conforming to JESD22-A114

TA +25 °C, conforming to JESD22-C101

2 2000

II 500

+85 °C conforming to JESD78A II level A

STM32F101xF, STM32F101xG Electrical characteristics

5.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above V operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in Tab l e 45

Table 45. I/O current injection susceptibility

Symbol Description

(for standard, 3 V-capable I/O pins) should be avoided during normal product

Functional susceptibility

Negative injection

Positive

injection

Unit

INJ

Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins -5 +0

-0 +0

Injected current on any other pin -5 +5

Doc ID 17143 Rev 2 79/108

Electrical characteristics STM32F101xF, STM32F101xG

5.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Ta bl e 4 6 are derived from tests performed under the conditions summarized in Tab l e 10 . All I/Os are CMOS and TTL compliant.

Table 46. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

Standard IO input low level voltage

IO FT

(1)

voltage

Standard IO input high level voltage

IO FT

(1)

voltage

input low level

input high level

–0.3 0.28*(V

–0.3 0.32*(V

0.41*(V

> 2 V

 2 V 5.2

0.42*(V

-2 V)+1.3 V VDD+0.3 V

-2 V)+1 V

-2 V)+0.8 V V

-2V)+0.75 V V

5.5

Standard IO Schmitt trigger voltage

hys

hysteresis

IO FT Schmitt trigger voltage hysteresis

Input leakage current

lkg

(2)

(4)

 VIN V

Standard I/Os

= 5 V

I/O FT

1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.5 the internal pull-up/pull-down resistors must be

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

Weak pull-up equivalent

(5)

resistor

Weak pull-down equivalent resistor

(5)

I/O pin capacitance 5 pF

V

disabled.

PMOS/NMOS contribution

to the series resistance is minimum (~10% order).

200 mV

(3)

5% V

1

30 40 50 k

µA

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 39 and Figure 40 for standard I/Os, and in Figure 41 and Figure 42 for 5 V tolerant I/Os.

80/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

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Figure 39. Standard I/O input characteristics - CMOS port

Figure 40. Standard I/O input characteristics - TTL port

Doc ID 17143 Rev 2 81/108

Electrical characteristics STM32F101xF, STM32F101xG

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Figure 41. 5 V tolerant I/O input characteristics - CMOS port

Figure 42. 5 V tolerant I/O input characteristics - TTL port

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:

● The sum of the currents sourced by all the I/Os on V

consumption of the MCU sourced on V I

(see Ta bl e 8 ).

VDD

● The sum of the currents sunk by all the I/Os on V

consumption of the MCU sunk on V I

(see Ta bl e 8 ).

VSS

82/108 Doc ID 17143 Rev 2

OL/VOH

plus the maximum Run

cannot exceed the absolute maximum rating

DD,

plus the maximum Run

cannot exceed the absolute maximum rating

STM32F101xF, STM32F101xG Electrical characteristics

Output voltage levels

Unless otherwise specified, the parameters given in Ta bl e 4 7 are derived from tests performed under ambient temperature and V

Ta bl e 1 0 . All I/Os are CMOS and TTL compliant.

Table 47. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

Output Low level voltage for an I/O pin

(1)

when 8 pins are sunk at the same time

Output High level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in

4. Based on characterization data, not tested in production.

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

and the sum of I

Table 8 and the sum of I

(I/O ports and control pins) must not exceed I

supply voltage conditions summarized in

CMOS port

= +8 mA,

(2)

2.7 V < VDD < 3.6 V

TTL port

2.7 V < V

= +20 mA

(2)

= +8 mA

< 3.6 V

(4)

2.7 V < VDD < 3.6 V

= +6 mA

(4)

2 V < VDD < 2.7 V

VSS

VDD

VDD–0.4

2.4

VDD–1.3

–0.4

0.4

1.3

0.4

Doc ID 17143 Rev 2 83/108

Electrical characteristics STM32F101xF, STM32F101xG

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 43 and

Ta bl e 4 8 , respectively.

Unless otherwise specified, the parameters given in Ta bl e 4 8 are derived from tests performed under ambient temperature and V

Ta bl e 1 0 .

Table 48. I/O AC characteristics

MODEx [1:0] bit value

Symbol Parameter Conditions Max Unit

(1)

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum Frequency

Output high to low level fall time

Output low to high level rise time

Pulse width of external

-t

EXTIpw

signals detected by the EXTI controller

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a

description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 43.

3. Guaranteed by design, not tested in production.

(1)

(2)

supply voltage conditions summarized in

CL = 50 pF, V

= 2 V to 3.6 V 2 MHz

125

= 50 pF, V

= 2 V to 3.6 V

125

CL= 50 pF, V

= 50 pF, V

CL= 30 pF, V

= 50 pF, V

CL = 30 pF, V

= 50 pF, V

CL = 50 pF, VDD = 2 V to 2.7 V 12

= 30 pF, V

CL = 50 pF, V

= 2 V to 3.6 V 10 MHz

(3)

= 2 V to 3.6 V

= 2.7 V to 3.6 V 50 MHz

= 2.7 V to 3.6 V 30 MHz

= 2 V to 2.7 V 20 MHz

= 2.7 V to 3.6 V 5

= 2.7 V to 3.6 V 8

= 2.7 V to 3.6 V 5

= 2.7 V to 3.6 V 8

= 2 V to 2.7 V 12

(3)

10 ns

(3)

84/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

ai14131

10%

90%

50%

r(IO)out

OUTPUT

EXTERNAL

ON 50pF

Maximum fr equency is achieved if (tr + tf) 2/3) T and if the duty cycle is (45-55%)

10 %

50%

90%

when loaded by 50pF

r(IO)out

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Figure 43. I/O AC characteristics definition

5.3.15 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

Unless otherwise specified, the parameters given in Ta bl e 4 9 are derived from tests performed under ambient temperature and V

Ta bl e 1 0 .

Table 49. NRST pin characteristics

(see Ta bl e 4 6 ).

supply voltage conditions summarized in

Symbol Parameter Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

NF(NRST)

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

(1)

NRST Input low level voltage –0.5 0.8

(1)

NRST Input high level voltage 2 VDD+0.5

hys(NRST)

F(NRST)

the series resistance must be minimum

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse 100 ns

(1)

NRST Input not filtered pulse 300 ns

(~10% order).

(2)

200 mV

V

30 40 50 k

Figure 44. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 49. Otherwise the reset will not be taken into account by the device.

Doc ID 17143 Rev 2 85/108

max level specified in

IL(NRST)

Electrical characteristics STM32F101xF, STM32F101xG

5.3.16 TIM timer characteristics

The parameters given in Tab l e 5 0 are guaranteed by design.

Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 50. TIMx

Symbol Parameter Conditions Min Max Unit

(1)

characteristics

res(TIM)

EXT

Res

Timer resolution time

Timer external clock frequency on CH1 to CH4

Timer resolution 16 bit

TIM

16-bit counter clock period

COUNTER

when internal clock is selected

MAX_COUNT

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

Maximum possible count

5.3.17 Communications interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Ta bl e 5 1 are derived from tests performed under ambient temperature, f summarized in Ta bl e 1 0 .

The STM32F101xC, STM32F101xD and STM32F101xESTM32F101xF and STM32F101xG access line I protocol with the following restrictions: t “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

The I

characteristics

and SCL)

C interface meets the requirements of the standard I2C communication

is disabled, but is still present.

C characteristics are described in Ta b le 5 1 . Refer also to

for more details on the input/output alternate function characteristics (SDA

TIMxCLK

= 36 MHz

27.8 ns

TIMxCLK

018MHz

1 65536

TIMxCLK

= 36 MHz

0.0278 1820 µs

65536 × 65536

= 36 MHz

TIMxCLK

frequency and VDD supply voltage conditions

PCLK1

119.2 s

TIMxCLK

MHz

TIMxCLK

he I/O pins SDA and SCL are mapped to are not

Section 5.3.14: I/O port

86/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

Table 51. I2C characteristics

Symbol Parameter

Standard mode I

2C(1)

Fast mode I2C

Min Max Min Max

(1)(2)

Unit

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA)

r(SCL)

f(SDA)

f(SCL)

h(STA)

su(STA)

su(STO)

w(STO:STA)

Guaranteed by design, not tested in production.

2. f

PCLK1

to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz.

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

period of SCL signal.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100

SDA data hold time 0

(3)

SDA and SCL rise time 1000 20+0.1C

(4)

900

300

SDA and SCL fall time 300 300

Start condition hold time 4.0 0.6

Repeated Start condition setup time

4.7 0.6

Stop condition setup time 4.0 0.6 µs

Stop to Start condition time (bus free)

Capacitive load for each bus line 400 400 pF

must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz

4.7 1.3 µs

µs

(3)

µs

Doc ID 17143 Rev 2 87/108

Electrical characteristics STM32F101xF, STM32F101xG

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Figure 45. I2C bus AC waveforms and measurement circuit

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7V

Table 52. SCL frequency (f

SCL

= 36 MHz, VDD = 3.3 V)

PCLK1

(kHz)

400 0x801E

(1)(2)

I2C_CCR value

(1)

= 4.7 k

300 0x8028

200 0x803C

100 0x00B4

50 0x0168

20 0x0384

= External pull-up resistance, f

1. R

2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the

tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.

88/108 Doc ID 17143 Rev 2

SCL

= I2C speed,

STM32F101xF, STM32F101xG Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 53Table 54 are derived from tests performed under ambient temperature, f summarized in Ta bl e 1 0 . Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 53. STM32F10xxx SPI characteristics

Symbol Parameter Conditions Min Max Unit

frequency and VDD supply voltage conditions

PCLKx

SCK

1/t

c(SCK)

r(SCK)

f(SCK)

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

SPI clock frequency

SPI clock rise and fall time

(1)

NSS setup time Slave mode 4t

(1)

NSS hold time Slave mode 73

(1)

SCK high and low

(1)

time

(1)

Data input setup

(1)

time

Master mode 10

Slave mode 10

Capacitive load: C = 30 pF 8

PCLK

Master mode, f presc = 4

= 36 MHz,

PCLK

50 60

Master mode - SPI1 3

Master mode - SPI2 5

MHz

Slave mode 4

(1)

h(MI)

h(SI)

a(SO)

dis(SO)

v(SO)

v(MO)

h(SO)

h(MO)

Data input hold time

(1)

Data output access

(1)(2)

time

Data output disable

(1)(3)

time

Data output valid

(1)

time

Data output valid

(1)

time

(1)

Data output hold

(1)

time

1. Based on characterization, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

Master mode - SPI1 4

Master mode - SPI2 6

Slave mode 5

Slave mode, f presc = 4

Slave mode, f

= 36 MHz,

PCLK

= 20 MHz 4t

PCLK

055

PCLK

Slave mode 10

Slave mode (after enable edge) 25

Master mode (after enable edge) 6

Slave mode (after enable edge) 25

Master mode (after enable edge) 6

Doc ID 17143 Rev 2 89/108

Electrical characteristics STM32F101xF, STM32F101xG

Table 54. SPI characteristics

(1)

Symbol Parameter Conditions Min Max Unit

SCK

1/t

c(SCK)

r(SCK)

f(SCK)

DuCy(SCK)

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

h(MI)

h(SI)

(2)(3)

a(SO)

dis(SO)

v(SO)

v(MO)

h(SO)

h(MO)

SPI clock frequency

SPI clock rise and fall time

SPI slave input clock duty cycle

(2)

NSS setup time Slave mode 4t

(2)

NSS hold time Slave mode 2t

(2)

SCK high and low time

(2)

Data input setup time

(2)

Data input hold time

(2)

Data output access time Slave mode, f

(2)(4)

Data output disable time Slave mode 2 10

(2)(1)

Data output valid time Slave mode (after enable edge) 25

(2)(1)

Data output valid time Master mode (after enable edge) 5

(2)

Data output hold time

(2)

1. Remapped SPI1 characteristics to be determined.

2. Based on characterization, not tested in production.

3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

Master mode 18

Slave mode 18

Capacitive load: C = 30 pF 8 ns

Slave mode 30 70 %

PCLK

Master mode, f presc = 4

= 36 MHz,

PCLK

50 60

Master mode 5

Slave mode 5

Master mode 5

Slave mode 4

= 20 MHz 0 3t

PCLK

Slave mode (after enable edge) 15

Master mode (after enable edge) 2

MHz

90/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

ai14134c

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

NSS input

Figure 46. SPI timing diagram - slave mode and CPHA=0

Figure 47. SPI timing diagram - slave mode and CPHA=1

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

(1)

Doc ID 17143 Rev 2 91/108

Electrical characteristics STM32F101xF, STM32F101xG

ai14136

SCK Input

CPHA=0

MOSI

OUTUT

MISO

INP U T

CPHA=0

MSBIN

M SB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

c(SCK)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

h(MI)

High

SCK Input

CPHA=1

CPOL=0

CPOL=1

su(MI)

v(MO)

h(MO)

Figure 48. SPI timing diagram - master mode

(1)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

5.3.18 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Ta bl e 5 5 are preliminary values derived from tests performed under ambient temperature, f conditions summarized in Ta bl e 1 0.

Note: It is recommended to perform a calibration after each power-up.

PCLK2

frequency and V

supply voltage

DDA

92/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

AIN

ADCCADC

N2+

ln

------------------------------------------------------------- - R

ADC

–

Table 55. ADC characteristics

Symbol Parameter Conditions Min Typ

Max Unit

VREF

TRIG

AIN

Power supply 2.4 3.6 V

DDA

Positive reference voltage 2.4 V

REF+

Current on the V

REF

input

ADC clock frequency 0.6 14 MHz

ADC

(2)

Sampling rate 0.05 1 MHz

= 14 MHz 823 kHz

(2)

External trigger frequency

Conversion voltage range

AIN

(2)

External input impedance

ADC

(3)

See Equation

1 and Ta bl e 5 6

0 (V

SSA

tied to ground)

for details

(2)

ADC

CAL

STAB

CONV

lat

latr

Sampling switch resistance 1 k

Internal sample and hold

(2)

capacitor

= 14 MHz 5.9 µs

(2)

Calibration time

Injection trigger conversion

(2)

ADC

= 14 MHz 0.214 µs

ADC

latency

= 14 MHz 0.143 µs

Regular trigger conversion

(2)

ADC

latency

= 14 MHz 0.107 17.1 µs

(2)

Sampling time

(2)

Power-up time 0 0 1 µs

Total conversion time

(2)

(including sampling time)

ADC

1.5 239.5 1/f

= 14 MHz 1 18 µs

ADC

14 to 252 (t successive approximation)

1. Preliminary values.

2. Guaranteed by design, not tested in production.

3. V

4. For external triggers, a delay of 1/f

can be internally connected to V

REF+

the package. Refer to Section 3: Pinouts and pin descriptions for further details.

and V

DDA

must be added to the latency specified in Table 55.

PCLK2

can be internally connected to V

REF-

(1)

160

or V

REF-

83 1/f

for sampling +12.5 for

SSA

DDA

(1)

220

µA

17 1/f

REF+

50 k

8pF

(4)

1/f

, depending on

ADC

Equation 1: R

max formula:

AIN

Doc ID 17143 Rev 2 93/108

Electrical characteristics STM32F101xF, STM32F101xG

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 56. R

max for f

AIN

= 14 MHz

ADC

Ts (cycles) tS (µs) R

1.5 0.11 0.4

7.5 0.54 5.9

13.5 0.96 11.4

28.5 2.04 25.2

41.5 2.96 37.2

55.5 3.96 50

71.5 5.11 NA

239.5 17.1 NA

1. Guaranteed by design, not tested in production.

(1)

max (k)

AIN

Table 57. ADC accuracy - limited test conditions

Symbol Parameter Test conditions Typ Max

ET Total unadjusted error

EO Offset error ±1 ±1.5

EG Gain error ±0.5 ±1.5

ED Differential linearity error ±0.7 ±1

EL Integral linearity error ±0.8 ±1.5

= 28 MHz,

PCLK2

= 14 MHz, R

ADC

= 3 V to 3.6 V, TA = 25 °C

DDA

Measurements made after ADC calibration

= V

REF+

DDA

(1)(2)

< 10 k,

AIN

(3)

±1.3 ±2

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and I

in Section 5.3.14 does not

INJ(PIN)

3. Preliminary values.

Unit

LSB

94/108 Doc ID 17143 Rev 2

STM32F101xF, STM32F101xG Electrical characteristics

1LSB

IDEAL

(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line

=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

=Offset Error: deviation between the first actual

transition and the first ideal one.

=Gain Error: deviation between the last ideal

transition and the last actual one.

=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

4095

4094

4093

1234567

4093 4094 4095 4096

(1)

(2)

(3)

DDA

SSA

ai14395b

REF+

4096

(or depending on package)]

DDA

4096

[1LSB

IDEAL =

Table 58. ADC accuracy

Symbol Parameter Test conditions Typ Max

ET Total unadjusted error

EO Offset error ±1.5 ±2.5

EG Gain error ±1.5 ±3

ED Differential linearity error ±1 ±2

(1) (2)(3)

= 28 MHz,

PCLK2

= 14 MHz, R

ADC

= 2.4 V to 3.6 V

DDA

< 10 k,

AIN

Measurements made after ADC calibration

±2 ±5

(4)

Unit

LSB

EL Integral linearity error ±1.5 ±3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

3. ADC accuracy vs. negative injection current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I affect the ADC accuracy.

, frequency, V

INJ(PIN)

and temperature ranges.

REF

and I

in Section 5.3.14 does not

INJ(PIN)

4. Preliminary values.

Figure 49. ADC accuracy characteristics

Doc ID 17143 Rev 2 95/108

Electrical characteristics STM32F101xF, STM32F101xG

ai14139d

STM32F10xxx

AINx

IL±1 µA

0.6 V

AIN

(1)

parasitic

AIN

0.6 V

ADC

(1)

ADC

(1)

12-bit

converter

Sample and hold ADC converter

Figure 50. Typical connection diagram using the ADC

1. Refer to Table 55 for the values of R

2. C

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

pad capacitance (roughly 7 pF). A high C this, f

should be reduced.

ADC

AIN

, R

parasitic

ADC

and C

ADC

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 51. Power supply and reference decoupling (V

1 µF // 10 nF

is connected to V

REF+

1 µF // 10 nF

or not. The 10 nF capacitors should be

DDA

not connected to V

REF+

STM32F10xxx

REF+

DDA

SSA/VREF-

DDA

)

1. V

96/108 Doc ID 17143 Rev 2

REF+

and V

inputs are available only on 100-pin packages.

REF-

ai14380b

STM32F101xF, STM32F101xG Electrical characteristics

Figure 52. Power supply and reference decoupling (V

1 µF // 10 nF

1. V

REF+

and V

inputs are available only on 100-pin packages.

REF-

5.3.19 DAC electrical specifications

Table 59. DAC characteristics

Symbol Parameter Min Typ Max

(1)

connected to V

REF+

STM32F10xxx

REF+/VDDA

REF–/VSSA

ai14381b

Unit Comments

DDA

)

DDA

REF+

SSA

(2)

LOAD

(2)

LOAD

DAC_OUT

(2)

min

DAC_OUT

(2)

max

DAC_OUT

(2)

min

DAC_OUT

(2)

max

Analog supply voltage 2.4 3.6 V

Reference supply voltage 2.4 3.6 V

Ground 0 0 V

Resistive load with buffer ON 5 k

Impedance output with buffer OFF

15 k

Capacitive load 50 pF

Lower DAC_OUT voltage with buffer ON

Higher DAC_OUT voltage with buffer ON

Lower DAC_OUT voltage with buffer OFF

Higher DAC_OUT voltage with buffer OFF

0.2 V

– 0.2 V

DDA

0.5 mV

– 1LSB V

REF+

must always be below

REF+

DDA

When the buffer is OFF, the minimum resistive load between DAC_OUT and V

have a 1% accuracy is 1.5 M

Maximum capacitive load at DAC_OUT pin (when the buffer is ON).

It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at

= 3.6 V and (0x155) and

REF+

(0xEAB) at V

REF+

= 2.4 V.

It gives the maximum output excursion of the DAC.

Doc ID 17143 Rev 2 97/108

Electrical characteristics STM32F101xF, STM32F101xG

Table 59. DAC characteristics (continued)

Symbol Parameter Min Typ Max

(1)

Unit Comments

DDVREF+

DDA

(3)

DNL

(3)

INL

(3)

Offset

Gain error

SETTLING

(3)

Update rate

WAKEUP

(3)

DAC DC current consumption in quiescent mode (Standby

220 µA

mode)

380 µA

DAC DC current consumption in quiescent mode (Standby mode)

Differential non linearity

480 µA

±0.5 LSB

Difference between two consecutive code-1LSB)

Integral non linearity (difference between measured value at

±2 LSB

±1 LSB

Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)

±4 LSB

±10 mV

Offset error (difference between measured

value at Code (0x800) and the ideal value = V

REF+

/2)

±3 LSB

±12 LSB

(3)

Gain error ±0.5 %

Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when

34 µsC

DAC_OUT reaches final value ±1LSB

Max frequency for a correct DAC_OUT change when small

(3)

variation in the input code (from

1MS/sC

code i to i+1LSB)

Wakeup time from off state (Setting the ENx bit in the DAC

6.5 10 µs

Control register)

With no load, worst code (0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs.

With no load, middle code (0x800) on the inputs.

With no load, worst code (0xF1C) at V

REF+

= 3.6 V in terms of DC consumption on the inputs.

Given for the DAC in 10-bit configuration.

Given for the DAC in 12-bit configuration.

Given for the DAC in 10-bit configuration.

Given for the DAC in 12-bit configuration.

Given for the DAC in 10-bit at

= 3.6 V.

REF+

Given for the DAC in 12-bit at V

= 3.6 V.

REF+

Given for the DAC in 12bit configuration.

LOAD

 50 pF, R

LOAD

 5k

input code between lowest and highest possible ones.

Power supply rejection ratio (to

PSRR+

1. Preliminary values.

2. Guaranteed by design, not tested in production.

3. Preliminary values.

(2)

) (static DC measurement

DDA

98/108 Doc ID 17143 Rev 2

–67 –40 dB No R

LOAD

, C

LOAD

= 50 pF

STM32F101xF, STM32F101xG Electrical characteristics

LOAD

Buffered/Non-buffered DAC

DACx_OUT

Buffer(1)

12-bit digital to analog converter

ai17157

Figure 53. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

5.3.20 Temperature sensor characteristics

Table 60. TS characteristics

Symbol Parameter Min Typ Max Unit

(1)

Avg_Slope

(1)

(2)

START

S_temp

1. Preliminary values.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

linearity with temperature

SENSE

(1)

Average slope 4.0 4.3 4.6 mV/°C

1 2

Voltage at 25°C 1.34 1.43 1.52 V

Startup time 4 10 µs

ADC sampling time when reading the

(3)(2)

temperature

17.1 µs

°C

Doc ID 17143 Rev 2 99/108

Package characteristics STM32F101xF, STM32F101xG

6 Package characteristics

6.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

100/108 Doc ID 17143 Rev 2

ST STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

2.1 Device overview

Table 2. STM32F101xF and STM32F101xG features and peripheral counts

Figure 1. STM32F101xF and STM32F101xG access line block diagram

Figure 2. Clock tree

2.2 Full compatibility throughout the family

Table 3. STM32F101xx family

2.3 Overview

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

2.3.2 Memory protection unit

2.3.3 Embedded Flash memory

2.3.4 CRC (cyclic redundancy check) calculation unit

2.3.5 Embedded SRAM

2.3.6 FSMC (flexible static memory controller)

2.3.7 LCD parallel interface

2.3.8 Nested vectored interrupt controller (NVIC)

2.3.9 External interrupt/event controller (EXTI)

2.3.10 Clocks and startup

2.3.11 Boot modes

2.3.12 Power supply schemes

2.3.13 Power supply supervisor

2.3.14 Voltage regulator

2.3.15 Low-power modes

2.3.16 DMA

2.3.17 RTC (real-time clock) and backup registers

2.3.18 Timers and watchdogs

Table 4. STM32F101xF and STM32F101xG timer feature comparison

2.3.19 I²C bus

2.3.20 Universal synchronous/asynchronous receiver transmitters (USARTs)

2.3.21 Serial peripheral interface (SPI)

2.3.22 GPIOs (general-purpose inputs/outputs)

2.3.23 ADC (analog to digital converter)

2.3.24 DAC (digital-to-analog converter)

2.3.25 Temperature sensor

2.3.26 Serial wire JTAG debug port (SWJ-DP)

2.3.27 Embedded Trace Macrocell™

3 Pinouts and pin descriptions

Figure 3. STM32F101xF and STM32F101xG access line LQFP144 pinout

Figure 4. STM32F101xF and STM32F101xG LQFP100 pinout

Figure 5. STM32F101xF and STM32F101xG LQFP64 pinout

Table 5. STM32F101xF and STM32F101xG pin definitions

Table 6. FSMC pin definition

4 Memory mapping

Figure 6. Memory map

5 Electrical characteristics

5.1 Parameter conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

5.1.5 Pin input voltage

5.1.6 Power supply scheme

Figure 9. Power supply scheme

5.1.7 Current consumption measurement

Figure 10. Current consumption measurement scheme

5.2 Absolute maximum ratings

Table 7. Voltage characteristics

Table 8. Current characteristics

Table 9. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Table 10. General operating conditions

5.3.2 Operating conditions at power-up / power-down

Table 11. Operating conditions at power-up / power-down

5.3.3 Embedded reset and power control block characteristics

Table 12. Embedded reset and power control block characteristics

5.3.4 Embedded reference voltage

Table 13. Embedded internal reference voltage

5.3.5 Supply current characteristics

Table 17. Typical and maximum current consumptions in Stop and Standby modes

Table 20. Peripheral current consumption

5.3.6 External clock source characteristics

Table 21. High-speed external user clock characteristics

Table 22. Low-speed user external clock characteristics