ST STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD User Manual

High-density access line, ARM-based 32-bit MCU with 256 to

LQFP144

20 × 2

0 mm

LQFP64

10

× 10 mm

LQFP100

14

× 14 mm

512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 36 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)
performance

– Single-cycle multiplication and hardware

division

■ Memories

– 256 to 512 Kbytes of Flash memory
– up to 48 Kbytes of SRAM
– Flexible static memory controller with 4

Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND
memories

– LCD parallel interface, 8080/6800 modes

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage

detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration

capability
– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes
–V

■ 1 x 12-bit, 1 µs A/D converters (up to 16

channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor

■ 2 × 12-bit D/A converters

■ DMA

– 12-channel DMA controller
– Peripherals supported: timers, ADC, DAC,

■ Up to 112 fast I/O ports

supply for RTC and backup registers

BAT

2

SPIs, I

Cs and USARTs

STM32F101xC STM32F101xD

STM32F101xE

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors and almost all
5 V-tolerant

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™

■ Up to 9 timers

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counters

– 2 × watchdog timers (Independent and

Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC

■ Up to 10 communication interfaces

– Up to 2 x I
– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s)

■ CRC calculation unit, 96-bit unique ID

■ ECOPACK

Table 1. Device summary

Reference Part number

STM32F101xC

STM32F101xD

STM32F101xE

2

C interfaces (SMBus/PMBus)

®

packages

STM32F101RC STM32F101VC
STM32F101ZC

STM32F101RD STM32F101VD
STM32F101ZD

STM32F101RE STM32F101ZE
STM32F101VE

April 2011 Doc ID 14610 Rev 8 1/112

www.st.com

1

Contents STM32F101xC, STM32F101xD, STM32F101xE

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 14

2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15

2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16

2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 20

2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.22 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.23 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.26 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 39

5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 78

5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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Contents STM32F101xC, STM32F101xD, STM32F101xE

6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.2.2 Evaluating the maximum junction temperature for an application . . . . 105

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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STM32F101xC, STM32F101xD, STM32F101xE List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts . . . . 11

Table 3. STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. High-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 12. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 13. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 14. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 15. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 43

Table 17. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 43

Table 18. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 47

Table 20. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 21. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 22. Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 23. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 24. LSE oscillator characteristics (f

Table 25. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 26. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 28. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 58

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 59

Table 33. Asynchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 34. Asynchronous multiplexed NOR/PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 35. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 36. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 37. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 38. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 39. Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 73

Table 40. Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 76

Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

LSE

Doc ID 14610 Rev 8 5/112

List of tables STM32F101xC, STM32F101xD, STM32F101xE

Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 50. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 51. I
Table 52. SCL frequency (f

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

PCLK1

Table 53. STM32F10xxx SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 54. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 55. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 56. R

max for f

AIN

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

ADC

Table 57. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 58. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 59. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 60. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 61. LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . 101

Table 62. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . 102

Table 63. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . 103

Table 64. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 65. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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STM32F101xC, STM32F101xD, STM32F101xE List of figures

List of figures

Figure 1. STM32F101xC, STM32F101xD and STM32F101xE access line block diagram . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout . . . . . . 23

Figure 4. STM32F101xC, STM32F101xD and STM32F101xE LQFP100 pinout . . . . . . . . . . . . . . . 24

Figure 5. STM32F101xC, STM32F101xD and STM32F101xE LQFP64 pinout . . . . . . . . . . . . . . . . 25

Figure 6. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 7. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42

Figure 13. Typical current consumption on V

different V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

BAT

Figure 14. Typical current consumption in Stop mode with regulator in run mode

versus temperature at different V
Figure 15. Typical current consumption in Stop mode with regulator in low-power

mode versus temperature at different V
Figure 16. Typical current consumption in Standby mode versus temperature at

different V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DD

Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 18. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 58

Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 59

Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 25. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 26. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 28. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 29. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 69

Figure 30. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 70

Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 33. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 72

Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 73

Figure 35. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 36. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 37. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 75

Figure 38. NAND controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . 76

Figure 39. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 40. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

with RTC on vs. temperature at

BAT

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DD

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DD

Doc ID 14610 Rev 8 7/112

List of figures STM32F101xC, STM32F101xD, STM32F101xE

Figure 41. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 42. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 43. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 44. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 45. I

Figure 46. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 47. SPI timing diagram - slave mode and CPHA=1
Figure 48. SPI timing diagram - master mode

2

C bus AC waveforms and measurement circuit

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 49. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 50. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 51. Power supply and reference decoupling (V

not connected to V

REF+

). . . . . . . . . . . . . . 96

DDA

Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 97

Figure 53. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 54. LQFP144, 20 x 20 mm, 144-pin thin quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 55. Recommended footprint

Figure 56. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 102

Figure 57. Recommended footprint

Figure 58. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 103

Figure 59. Recommended footprint
Figure 60. LQFP64 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

D

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F101xC, STM32F101xD and STM32F101xE high-density access line

microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family,

please refer to Section 2.2: Full compatibility throughout the family.

The high-density STM32F101xx datasheet should be read in conjunction with the

STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Doc ID 14610 Rev 8 9/112

Description STM32F101xC, STM32F101xD, STM32F101xE

2 Description

The STM32F101xC, STM32F101xD and STM32F101xE access line family incorporates the

high-performance ARM

®

Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency,
high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 48
Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB
buses. All devices offer one 12-bit ADC, four general-purpose 16-bit timers, as well as
standard and advanced communication interfaces: up to two I

2

Cs, three SPIs and five

USARTs.

The STM32F101xx high-density access line family operates in the –40 to +85 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.

These features make the STM32F101xx high-density access line microcontroller family
suitable for a wide range of applications such as medical and handheld equipment, PC
peripherals and gaming, GPS platforms, industrial applications, PLC, printers, scanners
alarm systems and video intercom.

10/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Description

2.1 Device overview

The STM32F101xx high-density access line family offers devices in 3 different package
types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.

●

Figure 1 shows the general block diagram of the device family.

Table 2. STM32F101xC, STM32F101xD and STM32F101xE features and peripheral

counts

Peripherals STM32F101Rx STM32F101Vx STM32F101Zx

Flash memory in Kbytes 256 384 512 256 384 512 256 384 512

SRAM in Kbytes 32 48 32 48 32 48

FSMC No Yes

(1)

Ye s

Timers

General­purpose

4

Basic 2

SPI 3

Comm

I2C2

USART 5

GPIOs 51 80 112

12-bit ADC
Number of channels

12-bit DAC
Number of channels

16

1

16

1

1

16

1
2

CPU frequency 36 MHz

Operating voltage 2.0 to 3.6 V

Operating temperatures

Ambient temperature: –40 to +85 °C (see Ta b le 1 0)

Junction temperature: –40 to +105 °C (see Ta bl e 1 0 )

Package LQFP64 LQFP100 LQFP144

1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a

multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit
NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not
available in this package.

Doc ID 14610 Rev 8 11/112

Description STM32F101xC, STM32F101xD, STM32F101xE

PA[15:0]

EXT.IT

112AF

AHB2

WKUP

F

max

: 36 MHz

V

SS

I2C2

GP DMA1

TIM2

TIM3

XTAL 32kHz

Flash 512 Kbytes

V

DD

Backup interface

TIM4

Bus Matrix

64 bit

RTC

RC 8 MHz

Cortex-M3 CPU

Dbus

obl

Flash

interface

USART 2

SPI2

Backup

reg

I2C1

RX, TX, CTS, RT S,

USART 3

RC 40 kHz

Standby

IWDG

@

V

BAT

POR / PDR

@V

DDA

V

BAT

=1.8 V to 3.6 V

CK, as AF

RX, TX, CTS, RTS,
CK, as AF

NVIC

SPI1

interface

@VDDA

PVD

Int

AHB2

APB2

AWU

SPI3

UART4

RX,TX as AF

UART5

RX,TX as AF

TIM5

PLL

@V

DDA

FSMC

DAC_OUT1 as AF

DAC_OUT2 as AF

SRAM

48 KB

GP DMA2

TIM6

TIM7

NJTRST

JTDI
JTCK/SWCLK
JTMS/SWDIO

JTDO
as AF

A[25:0]
D[15:0]

CLK
NOE
NWE

NE[4:1]

NBL[1:0]

NWAIT

NL

as AF

7 channels

5 channels

GPIO port A

GPIO port B

GPIO port C

GPIO port D

GPIO port E

GPIO port F

GPIO port G

USART1

Temp. sensor

12-bit ADC

IF

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

ADC_IN[0:15]

@ V

DDA

APB2: Fmax = 24/36 MHz

APB1

Trace
controller

Pbus

Ibus

System

Reset &
Clock
control

PCLK1
PCLK2
HCLK
FCLK

Power

Volt. reg.

3.3 V to 1.8 V

Supply
supervision

@V

DD

POR

Reset

NRST
V

DDA

V

SSA

OSC_IN
OSC_OUT

@V

DD
XTAL OSC
4-16 MHz

OSC32_IN
OSC32_OUT

TAMPER-RTC/
ALARM/SECOND OUT

4 channels as AF

4 channels as AF

4 channels as AF

4 channels as AF

MOSI, MISO
SCK, NSS as AF

MOSI, MISO

SCK, NSS as AF

SCL, SDA, SMBA as AF

SCL, SDA, SMBA as AF

WWDG

ai14693d

APB1: F

max

= 24/36 MHz

TRACECLK
TRACED[0:3]

as AS

SW/JTAG

TPIU

Trace/trig

V

REF+

V

REF–

MOSI, MISO, SCK,
NSS as AF

RX, TX, CTS, RTS
as AF

12bit DAC1

IFIF

IF

12bit DAC 2

Figure 1. STM32F101xC, STM32F101xD and STM32F101xE access line block

diagram

1. TA = –40 °C to +85 °C (junction temperature up to 105 °C).

2. AF = alternate function on I/O port pin.

12/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Description

HSE OSC

4-16 MHz

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

LSE OSC

32.768 kHz

HSI RC

8 MHz

LSI RC
40 kHz

to Independent Watchdog (IWDG)

PLL

x2, x3, x4

PLLMUL

HSE = High Speed External clock signal

LSE = Low Speed External clock signal

LSI = Low Speed Internal clock signal

HSI = High Speed Internal clock signal

Legend:

MCO

Clock Output

Main

PLLXTPRE

/2

..., x16

AHB
Prescaler
/1, 2..512

/2

PLLCLK

HSI

HSE

APB1

Prescaler

/1, 2, 4, 8, 16

ADC
Prescaler
/2, 4, 6, 8

ADCCLK

PCLK1

HCLK

PLLCLK

to AHB bus, core,
memory and DMA

to ADC

LSE

LSI

HSI

/128

/2

HSI

HSE

peripherals

to APB1

Peripheral Clock
Enable (18 bits)

Enable (6 bits)

Peripheral Clock

APB2

Prescaler

/1, 2, 4, 8, 16

PCLK2

peripherals to APB2

Peripheral Clock

Enable (11 bits)

36 MHz max

36 MHz

36 MHz max

36 MHz max

to RTC

PLLSRC

SW

MCO

CSS

to Cortex System timer

/8

Clock

Enable (7 bits)

SYSCLK

max

RTCCLK

RTCSEL[1:0]

TIMXCLK

IWDGCLK

SYSCLK

FCLK Cortex
free running clock

TIM2,3,4,5,6,7

to TIM2,3,4,5,6 and 7

to FSMC

FSMCCLK

Peripheral clock
enable

ai15100

If (APB1 prescaler =1) x1

else x2

FLITFCLK
to Flash programming interface

Figure 2. Clock tree

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.

2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

Doc ID 14610 Rev 8 13/112

Description STM32F101xC, STM32F101xD, STM32F101xE

2.2 Full compatibility throughout the family

The STM32F101xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are
identified as low-density devices, the STM32F101x8 and STM32F101xB are referred to as
medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are
referred to as high-density devices.

Low- and high-density devices are an extension of the STM32F101x8/B medium-density
devices, they are specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets,
respectively.

Low-density devices feature lower Flash memory and RAM capacities, less timers and
peripherals. High-density devices have higher Flash memory and RAM densities, and
additional peripherals like FSMC and DACwhile remaining fully compatible with the other
members of the family.

The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE
are a drop-in replacement for the STM32F101x8/B devices, allowing the user to try different
memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F101xx access line family is fully compatible with all existing
STM32F103xx performance line and STM32F102xx USB access line devices.

Table 3. STM32F101xx family

Memory size

Low-density devices Medium-density devices High-density devices

Pinout

16 KB

Flash

4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM

144

100

64

2 × USARTs
2 × 16-bit timers

48

1 × SPI, 1 × I
1 × ADC

36

1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.

32 KB

Flash

2

C

(1)

64 KB

Flash

3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs,
1 × ADC

128 KB

Flash

256 KB

Flash

32 KB

RAM

5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I
FSMC (100 and 144 pins)

2.3 Overview

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.

384 KB

Flash

48 KB

RAM

2

Cs, 1 × ADC, 2 × DACs

512 KB

Flash

48 KB

RAM

14/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Description

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.

The STM32F101xC, STM32F101xD and STM32F101xE access line family having an
embedded ARM core, is therefore compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2 Embedded Flash memory

256 to 512 Kbytes of embedded Flash are available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link­time and stored at a given memory location.

2.3.4 Embedded SRAM

Up to 48 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.

2.3.5 FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F101xC, STM32F101xD and STM32F101xE access
line family. It has four Chip Select outputs supporting the following modes: PC
Card/Compact Flash, SRAM, PSRAM, NOR and NAND.

Functionality overview:

● The three FSMC interrupt lines are ORed in order to be connected to the NVIC

● Write FIFO

● Code execution from external memory except for NAND Flash and PC Card

● The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at

36 MHz

2.3.6 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost­effective graphic applications using LCD modules with embedded controllers or high­performance solutions using external controllers with dedicated acceleration.

Doc ID 14610 Rev 8 15/112

Description STM32F101xC, STM32F101xD, STM32F101xE

2.3.7 Nested vectored interrupt controller (NVIC)

The STM32F101xC, STM32F101xD and STM32F101xE access line embeds a nested
vectored interrupt controller able to handle up to 60 maskable interrupt channels (not
including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low-latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt
latency.

2.3.8 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.

2.3.9 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock is available when necessary (for example with failure
of an indirectly used external oscillator).

Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)
domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and
APB domains is 36 MHz. See Figure 2 for details on the clock tree.

2.3.10 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash
memory bank 2 by setting a bit in the option bytes.

● Boot from system memory

● Boot from embedded SRAM

The bootloader is located in system memory. It is used to reprogram the Flash memory by
using USART1.

16/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Description

2.3.11 Power supply schemes

● V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

DD

Provided externally through V

● V

SSA

, V

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

DDA

RCs and PLL (minimum voltage to be applied to V

● V

used). V

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

BAT

DDA

and V

must be connected to VDD and VSS, respectively.

SSA

registers (through power switch) when V

For more details on how to connect power pins, refer to Figure 9: Power supply scheme.

2.3.12 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

generated when V
than the V

power supply and compares it to the V

DD/VDDA

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

V

POR/PDR

and V

PVD

is below a specified threshold, V

DD

drops below the V

.

DD

pins.

is 2.4 V when the ADC or DAC is

DDA

is not present.

DD

POR/PDR

threshold. An interrupt can be

PVD

threshold and/or when VDD/V

PVD

, without the need for an

is higher

DDA

2.3.13 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop modes.

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.14 Low-power modes

The STM32F101xC, STM32F101xD and STM32F101xE access line supports three low­power modes to achieve the best compromise between low power consumption, short
startup time and available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.

Doc ID 14610 Rev 8 17/112

Description STM32F101xC, STM32F101xD, STM32F101xE

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.15 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to­peripheral transfers.

The two DMA controllers support circular buffer management, removing the need for user
code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.

DMA can be used with the main peripherals: SPI, I

2

C, USART, general-purpose and basic

timers TIMx, DAC and ADC.

2.3.16 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on
V

supply when present or through the V

DD

registers used to store 84 bytes of user application data when V
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.

pin. The backup registers are forty-two 16-bit

BAT

power is not present.

DD

2.3.17 Timers and watchdogs

18/112 Doc ID 14610 Rev 8

The high-density STM32F101xx access line devices include up to four general-purpose
timers, two basic timers, two watchdog timers and a SysTick timer.

Ta bl e 4 compares the features of the general-purpose and basic timers.

STM32F101xC, STM32F101xD, STM32F101xE Description

Table 4. Timer feature comparison

Timer

TIM2,
TIM3,
TIM4,

TIM5

TIM6,

TIM7

Counter

resolution

16-bit

16-bit Up

Counter

type

Up,

down,

up/down

Prescaler

factor

Any integer

between 1
and 65536

Any integer

between 1
and 65536

DMA request

generation

Capture/compare

channels

Ye s 4 N o

Ye s 0 N o

Complementary

outputs

General-purpose timers (TIMx)

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)
embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line devices.
These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and
feature 4 independent channels each for input capture/output compare, PWM or one-pulse
mode output. This gives up to 16 input captures / output compares / PWMs on the largest
packages.
The general-purpose timers can work together with the advanced-control timer via the Timer
Link feature for synchronization or event chaining. Their counter can be frozen in debug
mode. Any of the general-purpose timers can be used to generate PWM outputs. They all
have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

Doc ID 14610 Rev 8 19/112

Description STM32F101xC, STM32F101xD, STM32F101xE

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

2.3.18 I²C bus

Up to two I²C bus interfaces can operate in multi-master and slave modes. They support
standard and fast modes.
They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.

2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F101xC, STM32F101xD and STM32F101xE access line embeds three
universal synchronous/asynchronous receiver transmitters (USART1, USART2 and
USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of
up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.

2.3.20 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2.3.21 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current­capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

20/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Description

2.3.22 ADC (analog to digital converter)

A 12-bit analog-to-digital converter is embedded into STM32F101xC, STM32F101xD and
STM32F101xE access line devices. It has up to 16 external channels, performing
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start trigger and injection trigger, respectively, to allow the application to
synchronize A/D conversion and timers.

2.3.23 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

● two DAC converters: one for each output channel

● 8-bit or 12-bit monotonic output

● left or right data alignment in 12-bit mode

● synchronized update capability

● noise-wave generation

● triangular-wave generation

● dual DAC channel independent or simultaneous conversions

● DMA capability for each channel

● external triggers for conversion

● input voltage reference V

Seven DAC trigger inputs are used in the STM32F101xC, STM32F101xD and
STM32F101xE access line family. The DAC channels are triggered through the timer update
outputs that are also connected to different DMA channels.

REF+

2.3.24 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.

2.3.25 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

Doc ID 14610 Rev 8 21/112

< 3.6 V. The temperature sensor is internally

DDA

Description STM32F101xC, STM32F101xD, STM32F101xE

2.3.26 Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F10xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using Ethernet, or any
other high-speed channel. Real-time instruction and data flow activity can be recorded and
then formatted for display on the host computer running debugger software. TPA hardware
is commercially available from common development tool vendors. It operates with third
party debugger software tools.

22/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions

V

DD_3VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PG15

V

DD_11VSS_11

PG14

PG13

PG12

PG11

PG10

PG9

PD7

PD6

V

DD_10VSS_10

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

PE2

V

DD_2

PE3

V

SS_2

PE4

NC

PE5

PA13

PE6

PA12

VBAT

PA11

PC13-TAMPER-RTC

PA10

PC14-OSC32_IN

PA9

PC15-OSC32_OUT

PA8

PF0

PC9

PF1

PC8

PF2

PC7

PF3

PC6

PF4

V

DD_9

PF5

V

SS_9

V

SS_5

PG8

V

DD_5

PG7

PF6

PG6

PF7

PG5

PF8

PG4

PF9

PG3

PF10

PG2

OSC_IN

PD15

OSC_OUT

PD14

NRST

V

DD_8

PC0

V

SS_8

PC1

PD13

PC2

PD12

PC3

PD11

V

SSA

PD10

V

REF-

PD9

V

REF+

PD8

V

DDA

PB15

PA0-WKUP

PB14

PA1

PB13

PA2

PB12

PA3

V

SS_4

V

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PF11

PF12

VSS_6

V

DD_6

PF13

PF14

PF15

PG0

PG1

PE7

PE8

PE9

V

SS_7

V

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

V

SS_1

V

DD_1

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

109

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

3738394041424344454647484950515253545556575859

60

72

LQFP144

120

119

118

117

116

115

114

113

112

111

110

6162636465666768697071

26
27
28
29
30
31
32
33
34
35
36

83
82
81
80
79
78
77
76
75
74
73

ai14667

3 Pinouts and pin descriptions

Figure 3. STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout

Doc ID 14610 Rev 8 23/112

Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE

100

9998979695949392919089888786858483828180797877

76

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

VDD_2
VSS_2
NC
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS_1

VDD_1

VDD_3

VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

26272829303132333435363738394041424344454647484950

PE2
PE3
PE4
PE5
PE6

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

OSC_IN

OSC_OUT

NRST

PC0
PC1
PC2
PC3

VSSA

VREF-

VREF+

VDDA

PA 0- W K UP

PA 1
PA 2

ai14391

LQFP100

Figure 4. STM32F101xC, STM32F101xD and STM32F101xE LQFP100 pinout

24/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47
46

45
44
43

42

41

40

39

38

37

36

35

34

33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1

2
3

4

5
6

7

8

9

10
11
12

13

14
15

16

V

BAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

PC0
PC1
PC2
PC3

V

SSA

V

DDA

PA 0- W K UP

PA 1
PA 2

V

DD_3

V

SS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA 1 5

PA 14

V

DD_2

V

SS_2

PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12

PA 3

V

SS_4

V

DD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

V

SS_1

V

DD_1

LQFP64

ai14392

Figure 5. STM32F101xC, STM32F101xD and STM32F101xE LQFP64 pinout

Table 5. High-density STM32F101xx pin definitions

Pins

Pin name

LQFP64

LQFP144

LQFP100

1 - 1 PE2 I/O

2 - 2 PE3 I/O

3 - 3 PE4 I/O

4 - 4 PE5 I/O

5 - 5 PE6 I/O

616 V

BAT

7 2 7 PC13-TAMPER-RTC

8 3 8 PC14-OSC32_IN

949PC15-OSC32_OUT

SV

(5)

I/O PC13

(5)

I/O PC14

(5)

I/O PC15

(1)

(2)

Typ e

Main

function

(3)

(after reset)

I / O Level

FT

FT

FT

FT

FT

PE2 TRACECLK/ FSMC_A23

PE3 TRACED0/FSMC_A19

PE4 TRACED1/FSMC_A20

PE5 TRACED2/FSMC_A21

PE6 TRACED3/FSMC_A22

BAT

(6)

(6)

(6)

Alternate functions

Default Remap

TAMPER-RTC

OSC32_IN

OSC32_OUT

10 - - PF0 I/O FT PF0 FSMC_A0

11 - - PF1 I/O FT PF1 FSMC_A1

12 - - PF2 I/O FT PF2 FSMC_A2

13 - - PF3 I/O FT PF3 FSMC_A3

14 - - PF4 I/O FT PF4 FSMC_A4

15 - - PF5 I/O FT PF5 FSMC_A5

16 - 10 V

17 - 11 V

SS_5

DD_5

SV

SV

SS_5

DD_5

Doc ID 14610 Rev 8 25/112

(4)

Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE

Table 5. High-density STM32F101xx pin definitions (continued)

(4)

/

(7)

LQFP144

Pins

LQFP64

Pin name

LQFP100

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

18 - - PF6 I/O PF6 FSMC_NIORD

19 - - PF7 I/O PF7 FSMC_NREG

20 - - PF8 I/O PF8 FSMC_NIOWR

21 - - PF9 I/O PF9 FSMC_CD

22 - - PF10 I/O PF10 FSMC_INTR

23 5 12 OSC_IN I OSC_IN

24 6 13 OSC_OUT O OSC_OUT

25714 NRST I/O NRST

26 8 15 PC0 I/O PC0 ADC_IN10

27 9 16 PC1 I/O PC1 ADC_IN11

28 10 17 PC2 I/O PC2 ADC_IN12

29 11 18 PC3 I/O PC3 ADC_IN13

30 12 19 V

31 - 20 V

32 - 21 V

33 13 22 V

SSA

REF-

REF+

DDA

SV

SV

SV

SV

SSA

REF-

REF+

DDA

WKUP/ USART2_CTS

34 14 23 PA0-WKUP I/O PA0

ADC_IN0/TIM5_CH1/

TIM2_CH1_ETR

35 15 24 PA1 I/O PA1

36 16 25 PA2 I/O PA2

37 17 26 PA3 I/O PA3

38 18 27 V

39 19 28 V

SS_4

DD_4

SV

SV

40 20 29 PA4 I/O PA4

41 21 30 PA5 I/O PA5

42 22 31 PA6 I/O PA6

SS_4

DD_4

ADC_IN1/TIM5_CH2

TIM5_CH3/ADC_IN2/

TIM5_CH4 / ADC_IN3/

SPI1_NSS/ DAC_OUT1

ADC_IN4 / USART2_CK

DAC_OUT2/ADC_IN5

SPI1_MISO / ADC_IN6 /

Alternate functions

Default Remap

(7)

(7)

(7)

(7)

(7)

(7)

(7)

(7)

/

/

/

USART2_RTS

TIM2_CH2

USART2_TX

TIM2_CH3

USART2_RX

TIM2_CH4

SPI1_SCK/

TIM3_CH1

(7)

26/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions

Table 5. High-density STM32F101xx pin definitions (continued)

(7)

(7)

(4)

TIM2_CH3

TIM2_CH4

Pins

Pin name

LQFP64

LQFP144

LQFP100

43 23 32 PA7 I/O PA7

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

SPI1_MOSI / ADC_IN7/

TIM3_CH2

44 24 33 PC4 I/O PC4 ADC_IN14

45 25 34 PC5 I/O PC5 ADC_IN15

46 26 35 PB0 I/O PB0 ADC_IN8 / TIM3_CH3

47 27 36 PB1 I/O PB1 ADC_IN9/TIM3_CH4

48 28 37

PB2 I/O FT PB2/BOOT1

49 - - PF11 I/O FT PF11 FSMC_NIOS16

50 - - PF12 I/O FT PF12 FSMC_A6

51 - - V

52 - - V

SS_6

DD_6

53 - - PF13 I/O

SV

SV

FT

SS_6

DD_6

PF13 FSMC_A7

54 - - PF14 I/O FT PF14 FSMC_A8

55 - - PF15 I/O

FT

PF15 FSMC_A9

56 - - PG0 I/O FT PG0 FSMC_A10

57 - - PG1 I/O

FT

PG1 FSMC_A11

58 - 38 PE7 I/O FT PE7 FSMC_D4

59 - 39 PE8 I/O FT PE8 FSMC_D5

60 - 40 PE9 I/O FT PE9 FSMC_D6

61 - - V

62 - - V

SS_7

DD_7

SV

SV

SS_7

DD_7

63 - 41 PE10 I/O FT PE10 FSMC_D7

64 - 42 PE11 I/O FT PE11 FSMC_D8

65 - 43 PE12 I/O FT PE12 FSMC_D9

66 - 44 PE13 I/O FT PE13 FSMC_D10

67 - 45 PE14 I/O FT PE14 FSMC_D11

68 - 46 PE15 I/O FT PE15 FSMC_D12

69 29 47 PB10 I/O FT PB10 I2C2_SCL/ USART3_TX

70 30 48 PB11 I/O FT PB11 I2C2_SDA/ USART3_RX

71 31 49 V

72 32 50 V

SS_1

DD_1

73 33 51 PB12 I/O FT PB12

SV

SV

SS_1

DD_1

SPI2_NSS

USART3_CK

Alternate functions

Default Remap

(7)

(7)

(7)

(7)

/ I2C2_SMBA

(7)

Doc ID 14610 Rev 8 27/112

Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE

Table 5. High-density STM32F101xx pin definitions (continued)

(4)

TIM4_CH1 /

USART3_RTS

LQFP144

Pins

LQFP64

Pin name

LQFP100

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

74 34 52 PB13 I/O FT PB13

75 35 53 PB14 I/O FT PB14

76 36 54 PB15 I/O FT PB15 SPI2_MOSI

Alternate functions

Default Remap

(7)

(7)

(7)

/

(7)

(7)

/

SPI2_SCK

USART3_CTS

SPI2_MISO

USART3_RTS

77 - 55 PD8 I/O FT PD8 FSMC_D13 USART3_TX

78 - 56 PD9 I/O FT PD9 FSMC_D14 USART3_RX

79 - 57 PD10 I/O FT PD10 FSMC_D15 USART3_CK

80 - 58 PD11 I/O FT PD11 FSMC_A16 USART3_CTS

81 - 59 PD12 I/O FT PD12 FSMC_A17

82 - 60 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2

83 - - V

84 - - V

SS_8

DD_8

SV

SV

SS_8

DD_8

85 - 61 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3

86 - 62 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4

87 - - PG2 I/O FT PG2 FSMC_A12

88 - - PG3 I/O FT PG3 FSMC_A13

89 - - PG4 I/O FT PG4 FSMC_A14

90 - - PG5 I/O FT PG5 FSMC_A15

91 - - PG6 I/O FT PG6 FSMC_INT2

92 - - PG7 I/O FT PG7 FSMC_INT3

93 - - PG8 I/O FT PG8

94 - - V

95 - - V

SS_9

DD_9

SV

SV

SS_9

DD_9

96 37 63 PC6 I/O FT PC6 TIM3_CH1

97 38 64 PC7 I/O FT PC7 TIM3_CH2

98 39 65 PC8 I/O FT PC8 TIM3_CH3

99 40 66 PC9 I/O FT PC9 TIM3_CH4

100 41 67 PA8 I/O FT PA8 USART1_CK/ MCO

101 42 68 PA9 I/O FT PA9 USART1_TX

102 43 69 PA10 I/O FT PA10 USART1_RX

(7)

(7)

103 44 70 PA11 I/O FT PA11 USART1_CTS

28/112 Doc ID 14610 Rev 8

STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions

Table 5. High-density STM32F101xx pin definitions (continued)

(4)

TIM2_CH1_ETR/
PA15 /

USART3_TX

USART3_RX

USART3_CK

USART2_CTS

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

LQFP144

Pins

LQFP64

Pin name

LQFP100

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

104 45 71 PA12 I/O FT PA12 USART1_RTS

105 46 72 PA13 I/O FT JTMS-SWDIO

106 - 73 Not connected

107 47 74

108 48 75

109 49 76

110 50 77

111 51 78

112 52 79

113 53 80

114 5 81

115 6 82

116 54 83

117 - 84

118 - 85

119 - 86

120 - -

121 - -

122 - 87

123 - 88

124 - -

125 - -

126 - -

127 - -

128 - -

129 - -

130 - -

131 - -

132 - -

V

V

SS_2

DD_2

SV

SV

SS_2

DD_2

PA14 I/O FT JTCK-SWCLK PA14

PA15 I/O FT JTDI SPI3_NSS

PC10 I/O FT PC10 UART4_TX

PC11 I/O FT PC11 UART4_RX

PC12 I/O FT PC12 UART5_TX

PD0 I/O FT OSC_IN

PD1 I/O FT OSC_OUT

(8)

(8)

PD2 I/O FT PD2 TIM3_ETR/UART5_RX

PD3 I/O FT PD3 FSMC_CLK

PD4 I/O FT PD4 FSMC_NOE

PD5 I/O FT PD5 FSMC_NWE

V

SS_10

V

DD_10

SV

SV

SS_10

DD_10

PD6 I/O FT PD6 FSMC_NWAIT

PD7 I/O FT PD7

PG9 I/O FT PG9

PG10 I/O FT PG10

PG11 I/O FT PG11

PG12 I/O FT PG12 FSMC_NE4

PG13 I/O FT PG13 FSMC_A24

PG14 I/O FT PG14 FSMC_A25

V

SS_11

V

DD_11

SV

SV

SS_11

DD_11

PG15 I/O FT PG15

Alternate functions

Default Remap

FSMC_D2

FSMC_D3

(9)

(9)

FSMC_NE1/

FSMC_NCE2

FSMC_NE2/

FSMC_NCE3

FSMC_NE3/

FSMC_NCE4_1

FSMC_NCE4_2

PA 1 3

SPI1_NSS

Doc ID 14610 Rev 8 29/112

Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE

Table 5. High-density STM32F101xx pin definitions (continued)

Pins

LQFP64

LQFP144

133 55 89

134 56 90

(2)

Pin name

(1)

Typ e

LQFP100

I / O Level

Main

function

(3)

(after reset)

PB3 I/O FT JTDO SPI3_SCK

PB4 I/O FT NJTRST SPI3_MISO

Alternate functions

Default Remap

135 57 91 PB5 I/O PB5 I2C1_SMBA/ SPI3_MOSI

136 58 92 PB6 I/O FT PB6 I2C1_SCL/ TIM4_CH1

137 59 93 PB7 I/O FT PB7

I2C1_SDA/FSMC_NADV

TIM4_CH2

(7)

(7)

138 60 94 BOOT0 I BOOT0

(7)

(7)

(7)

/

139 61 95 PB8 I/O FT PB8 TIM4_CH3

140 62 96 PB9 I/O FT PB9 TIM4_CH4

141 - 97 PE0 I/O FT PE0

TIM4_ETR
FSMC_NBL0

142 - 98 PE1 I/O FT PE1 FSMC_NBL1

143 63 99 V

144 64 100 V

SS_3

DD_3

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.

7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.

8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F10xxx reference manual

9. For devices delivered in LQFP64 packages, the FSMC function is not available.

SV

SV

SS_3

DD_3

(4)

TIM2_CH2 /

TRACESWO

SPI1_SCK

TIM3_CH1

PB4 /

SPI1_MISO

TIM3_CH2 /
SPI1_MOSI

USART1_TX

USART1_RX

I2C1_SCL

I2C1_SDA

PB3

30/112 Doc ID 14610 Rev 8