ST M48T251Y, M48T251V User Manual
查询M48T251V供应商
5.0 or 3.3V, 4096K TIMEKEEPER® SRAM with PHANTOM
FEAT URES SUMMARY
M48T251Y
M48T251V
■ 5.0V OR 3.3V OPERATING VOLTAGE
■ REAL TIME CLOCK KEEPS TRACK OF
TENTHS/HUNDREDTHS OF SECONDS,
SECONDS, MINUTES, HOURS, DAYS,
DATE OF THE MONTH, MONTHS, AND
YEARS
■ AUTOMATIC LEAP YEAR CORREC TION
VALID UP TO THE YEAR 2100
■ AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY
■ CHOICE OF POWER-FAIL DESEL ECT
VOLTAGES:
(V
= Power-fail Deselect Voltage):
PFD
– M48T251Y: 4.25V
– M48T251V: 2.80V
■ FULL 10% V
■ OVER 10 YEARS’ DATA RETENTION IN
THE ABSENCE OF POWER
■ WATCH FUNCTION IS TRANSPARENT TO
RAM OPERATION
■ 512K x 8 NV SRAM DIRECTLY REPLACES
VOLATILE STATIC RAM OR EEPROM
OPERATING RANGE
CC
≤ V
≤ V
PFD
PFD
≤ 4.50V
≤ 2.97V
Figure 1. 32-pin, DIP Package
32
1
PMDIP32 (PM)
1/24February 2005
M48T251Y, M48T251V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 32-pin, DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Memory READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Memory WRITE Cycle 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 7. Memory WRITE Cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Memory AC Characteristics, M48T251Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. Memory AC Characteristics, M48T251V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8. Comparison Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Zero Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. P hant om Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11.Phantom Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. P hantom Clock AC Characteristics (M48T251Y ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. P hantom Clock AC Characteristics (M48T251V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. DC and A C Measurem ent Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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M48T251Y, M48T251V
Table 12.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14.Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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M48T251Y, M48T251V
SUMMARY DESCRIPTION
The M48T251Y/V TIMEKEEPER® RAM is a
512Kbit x 8 non-volatile static RAM and real time
clock organized as 524 ,288 words by 8 bits. The
special DIP package provides a fully integrated
battery back-up memory and real time clock solution. In the event of power instability or absence, a
self-contained battery maintains the timekeeping
operation and provides po wer for a CMOS static
RAM. Control circuitry monitors V
and invokes
CC
write protection to prevent data c orruption in the
memory and RTC.
The clock keeps track of tenths/hundredths of sec-
automatically adjusted for months with less than
31 days, including leap year correction.
The clock operates in one of two formats:
– a 12-hour mode with an AM/PM indicator;
or
– a 24-hour mode
The M48T251Y/V is a 32-pin (PM) DIP module
that integrates the RTC, the battery, and SRAM in
one package.
The modules are shipped in plastic, anti-static
tubes (see Table 14., page 22).
onds, seconds, minutes , hou rs, day, date, month,
and year information. The last day of the month is
Figure 2. Logic Diagram Table 1. Signal Names
A0–A18 Address Input
RST
CE
OE
WE
DQ0–DQ7 Data Inputs/Outputs
Reset Input
Chip Enable
Output Enable Input
WRITE Enable Input
A0-A18
WE
CE
V
CC
M48T251Y
M48T251V
DQ0-D7
OE
RST
V
CC
V
SS
V
SS
AI04237
Supply Voltage Input
Ground
4/24
Figure 3. DIP C on ne ctions
A18/RST
A16
A14
A12
DQ0
DQ1
DQ2
V
SS
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
M48T251Y
M48T251V
30
29
28
27
26
25
24
23
22
20
19
18
17
32
31
21
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
AI04239
M48T251Y, M48T251V
Figure 4. Block Diagram
CE
OE
WE
RST
DQ0
CONTROL
LOGIC
ACCESS
ENABLE
SEQUENCE
DETECTOR
I/O
BUFFERS
V
CC
32.768 Hz
CRYSTAL
READ
WRITE
POWER
FAIL
DATA
POWER-FAIL
DETECT
LOGIC
XO
XI
CLOCK/CALENDAR
LOGIC
UPDATE
TIMEKEEPER
REGISTER
SRAM
COMPARISON
REGISTER
INTERNAL V
CC
A0–A16
DQ0–DQ7
V
BAT
AI04238
5/24
M48T251Y, M48T251V
OPERATION MODES
Table 2. Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
V
Deselect
Note: X = VIH or VIL; VSO = Battery B ack-up Switchover Voltage
1. See Table 12., page 20 for details.
READ
A READ cycle executes whenever WRITE Enable
) is high and Chip Enable (CE) is low (see Fig-
(WE
ure 5.). The distinct address defined by the 19 ad-
dress inputs (A0-A18) specifies which of the 512K
bytes of dat a is to be acces sed . Vali d data w ill be
accessed by the eight data output drivers within
the specified Access Time (t
V
4.5V to 5.5V
or
3.0V to 3.6V
to V
SO
PFD
≤ V
CC
(1)
(min)
(1)
SO
) after the last ad-
ACC
CE OE WE DQ7-DQ0 Power
V
IH
V
IL
V
IL
V
IL
X X X High-Z CMOS Standby
X X X High-Z Battery Back-Up
X X High-Z Standby
X
V
IL
V
IH
V
IL
V
IH
V
IH
dress input signal is stable, the CE
D
IN
D
OUT
Active
Active
High-Z Active
and OE access
times, and their respective parameters are satisfied. When CE
ACC
and OE t
are not satisfied,
ACC
t
then data access times mus t be measured from
the more recent CE
ing parameter being t
and OE signals, with the limit-
(for CE) or tOE (for OE) in-
CO
stead of address access.
Figure 5. Memory READ Cycle
ADDRESSES
CE
OE
DQ0 - DQ7
Note: WE is high for a READ cycle.
tCOE
tCOE
tACC
tCO
tRC
tOH
tOD
tOE
tODO
DATA OUTPUT
VALID
AI04230
6/24
WRITE
M48T251Y, M48T251V
WRITE Mode (see Figure 6.) occurs whenever CE
and WE signals are low (after address inputs are
stable). The most recent falling edge of CE
will det ermine when the WRITE cycle begins
WE
(the earlier, rising edge of CE
or WE determines
and
cycle termination). All address inputs must be kept
stable throughout the WRITE cycle. WE
must be
Figure 6. Memory WRITE Cycle 1
ADDRESSES
tAW
CE
WE
high (inactive) for a minimum recovery time (t
before a subsequent cycle is initiated. The OE
control signal should be kept high (inactive) during
the WRITE cycles to avoid bus contention. If CE
and OE are low (active), WE will disable t he outputs for Output Data WRITE Time (t
ODW
falling edge.
tWC
tWR
tWP
tOEW
tODW
HIGH IMPEDANCE
WR
) from its
)
DQ0–DQ7
Note: 1. OE = VIH or VIL. If OE = VIH during a WRI TE cycle, the output buffers rem ain in a high imp edance state .
2. If the CE
3. If t h e C E
low transit i on occurs simult aneously with or later than the WE low transi t i on i n WRITE Cycle 1, the output buffers remain
in a high impedance state du ri ng this period .
high t rans ition o ccur s s imult ane ously wi th t he W E h igh t ransit ion , t he ou tp ut b uffe rs r ema in in a hi gh i mpe dance st ate
during this peri od.
tDS
DATA IN
STABLE
tDH
AI04231
7/24
M48T251Y, M48T251V
Figure 7. Memory WRITE Cycle 2
WE = V
IH
ADDRESSES
CE
V
V
tAW
tWC
V
V
IH
tWR
IH
V
V
IL
IL
IH
IL
tWP
V
IH
V
IL
V
IH
V
IL
tOEW
WE
V
IL
V
IL
tODW
tCOE
DQ0–DQ7
tDS
V
IH
V
IL
DATA IN
STABLE
tDH
V
IH
V
IL
Note: 1. OE = VIH or VIL. If OE = VIH during a WRI TE cycle, the output buffers rem ain in a high imp edance state .
2. If WE
is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high
impedance state during this period.
AI04232
8/24
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