查询M48T251V供应商
5.0 or 3.3V, 4096K TIMEKEEPER® SRAM with PHANTOM
FEAT URES SUMMARY
M48T251Y
M48T251V
■ 5.0V OR 3.3V OPERATING VOLTAGE
■ REAL TIME CLOCK KEEPS TRACK OF
TENTHS/HUNDREDTHS OF SECONDS,
SECONDS, MINUTES, HOURS, DAYS,
DATE OF THE MONTH, MONTHS, AND
YEARS
■ AUTOMATIC LEAP YEAR CORREC TION
VALID UP TO THE YEAR 2100
■ AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY
■ CHOICE OF POWER-FAIL DESEL ECT
VOLTAGES:
(V
= Power-fail Deselect Voltage):
PFD
– M48T251Y: 4.25V
– M48T251V: 2.80V
■ FULL 10% V
■ OVER 10 YEARS’ DATA RETENTION IN
THE ABSENCE OF POWER
■ WATCH FUNCTION IS TRANSPARENT TO
RAM OPERATION
■ 512K x 8 NV SRAM DIRECTLY REPLACES
VOLATILE STATIC RAM OR EEPROM
OPERATING RANGE
CC
≤ V
≤ V
PFD
PFD
≤ 4.50V
≤ 2.97V
Figure 1. 32-pin, DIP Package
32
1
PMDIP32 (PM)
1/24February 2005
M48T251Y, M48T251V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 32-pin, DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Memory READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Memory WRITE Cycle 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 7. Memory WRITE Cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Memory AC Characteristics, M48T251Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. Memory AC Characteristics, M48T251V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8. Comparison Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Zero Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. P hant om Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11.Phantom Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. P hantom Clock AC Characteristics (M48T251Y ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. P hantom Clock AC Characteristics (M48T251V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. DC and A C Measurem ent Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/24
M48T251Y, M48T251V
Table 12.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14.Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3/24
M48T251Y, M48T251V
SUMMARY DESCRIPTION
The M48T251Y/V TIMEKEEPER® RAM is a
512Kbit x 8 non-volatile static RAM and real time
clock organized as 524 ,288 words by 8 bits. The
special DIP package provides a fully integrated
battery back-up memory and real time clock solution. In the event of power instability or absence, a
self-contained battery maintains the timekeeping
operation and provides po wer for a CMOS static
RAM. Control circuitry monitors V
and invokes
CC
write protection to prevent data c orruption in the
memory and RTC.
The clock keeps track of tenths/hundredths of sec-
automatically adjusted for months with less than
31 days, including leap year correction.
The clock operates in one of two formats:
– a 12-hour mode with an AM/PM indicator;
or
– a 24-hour mode
The M48T251Y/V is a 32-pin (PM) DIP module
that integrates the RTC, the battery, and SRAM in
one package.
The modules are shipped in plastic, anti-static
tubes (see Table 14., page 22).
onds, seconds, minutes , hou rs, day, date, month,
and year information. The last day of the month is
Figure 2. Logic Diagram Table 1. Signal Names
A0–A18 Address Input
RST
CE
OE
WE
DQ0–DQ7 Data Inputs/Outputs
Reset Input
Chip Enable
Output Enable Input
WRITE Enable Input
A0-A18
WE
CE
V
CC
M48T251Y
M48T251V
DQ0-D7
OE
RST
V
CC
V
SS
V
SS
AI04237
Supply Voltage Input
Ground
4/24
Figure 3. DIP C on ne ctions
A18/RST
A16
A14
A12
DQ0
DQ1
DQ2
V
SS
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
M48T251Y
M48T251V
30
29
28
27
26
25
24
23
22
20
19
18
17
32
31
21
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
AI04239
M48T251Y, M48T251V
Figure 4. Block Diagram
CE
OE
WE
RST
DQ0
CONTROL
LOGIC
ACCESS
ENABLE
SEQUENCE
DETECTOR
I/O
BUFFERS
V
CC
32.768 Hz
CRYSTAL
READ
WRITE
POWER
FAIL
DATA
POWER-FAIL
DETECT
LOGIC
XO
XI
CLOCK/CALENDAR
LOGIC
UPDATE
TIMEKEEPER
REGISTER
SRAM
COMPARISON
REGISTER
INTERNAL V
CC
A0–A16
DQ0–DQ7
V
BAT
AI04238
5/24
M48T251Y, M48T251V
OPERATION MODES
Table 2. Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
V
Deselect
Note: X = VIH or VIL; VSO = Battery B ack-up Switchover Voltage
1. See Table 12., page 20 for details.
READ
A READ cycle executes whenever WRITE Enable
) is high and Chip Enable (CE) is low (see Fig-
(WE
ure 5.). The distinct address defined by the 19 ad-
dress inputs (A0-A18) specifies which of the 512K
bytes of dat a is to be acces sed . Vali d data w ill be
accessed by the eight data output drivers within
the specified Access Time (t
V
4.5V to 5.5V
or
3.0V to 3.6V
to V
SO
PFD
≤ V
CC
(1)
(min)
(1)
SO
) after the last ad-
ACC
CE OE WE DQ7-DQ0 Power
V
IH
V
IL
V
IL
V
IL
X X X High-Z CMOS Standby
X X X High-Z Battery Back-Up
X X High-Z Standby
X
V
IL
V
IH
V
IL
V
IH
V
IH
dress input signal is stable, the CE
D
IN
D
OUT
Active
Active
High-Z Active
and OE access
times, and their respective parameters are satisfied. When CE
ACC
and OE t
are not satisfied,
ACC
t
then data access times mus t be measured from
the more recent CE
ing parameter being t
and OE signals, with the limit-
(for CE) or tOE (for OE) in-
CO
stead of address access.
Figure 5. Memory READ Cycle
ADDRESSES
CE
OE
DQ0 - DQ7
Note: WE is high for a READ cycle.
tCOE
tCOE
tACC
tCO
tRC
tOH
tOD
tOE
tODO
DATA OUTPUT
VALID
AI04230
6/24
WRITE
M48T251Y, M48T251V
WRITE Mode (see Figure 6.) occurs whenever CE
and WE signals are low (after address inputs are
stable). The most recent falling edge of CE
will det ermine when the WRITE cycle begins
WE
(the earlier, rising edge of CE
or WE determines
and
cycle termination). All address inputs must be kept
stable throughout the WRITE cycle. WE
must be
Figure 6. Memory WRITE Cycle 1
ADDRESSES
tAW
CE
WE
high (inactive) for a minimum recovery time (t
before a subsequent cycle is initiated. The OE
control signal should be kept high (inactive) during
the WRITE cycles to avoid bus contention. If CE
and OE are low (active), WE will disable t he outputs for Output Data WRITE Time (t
ODW
falling edge.
tWC
tWR
tWP
tOEW
tODW
HIGH IMPEDANCE
WR
) from its
)
DQ0–DQ7
Note: 1. OE = VIH or VIL. If OE = VIH during a WRI TE cycle, the output buffers rem ain in a high imp edance state .
2. If the CE
3. If t h e C E
low transit i on occurs simult aneously with or later than the WE low transi t i on i n WRITE Cycle 1, the output buffers remain
in a high impedance state du ri ng this period .
high t rans ition o ccur s s imult ane ously wi th t he W E h igh t ransit ion , t he ou tp ut b uffe rs r ema in in a hi gh i mpe dance st ate
during this peri od.
tDS
DATA IN
STABLE
tDH
AI04231
7/24
M48T251Y, M48T251V
Figure 7. Memory WRITE Cycle 2
WE = V
IH
ADDRESSES
CE
V
V
tAW
tWC
V
V
IH
tWR
IH
V
V
IL
IL
IH
IL
tWP
V
IH
V
IL
V
IH
V
IL
tOEW
WE
V
IL
V
IL
tODW
tCOE
DQ0–DQ7
tDS
V
IH
V
IL
DATA IN
STABLE
tDH
V
IH
V
IL
Note: 1. OE = VIH or VIL. If OE = VIH during a WRI TE cycle, the output buffers rem ain in a high imp edance state .
2. If WE
is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high
impedance state during this period.
AI04232
8/24
M48T251Y, M48T251V
Table 3. Memory AC Characteristics, M48T251Y
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AXQX
t
EHQZ
t
GHQZ
t
WLQZ t
t
AVAV
t
WLWH
t
ELEH
t
AVEL
t
AVWL
t
EHAX
t
WHAX
t
WHQX
t
DVEH
t
DVWH
t
WHDX
t
EHDX
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (except where noted).
2. These paramet ers are sampled with a 5 pF load are not 100% tested.
3. t
4. t
t
t
ACC
t
t
t
COE
tOH
t
OD
ODW
t
WC
t
WP
t
t
WR1
t
WR2
t
OEW
t
DS
t
DH1
t
DH2
is specified as the logical AND of CE and WE. tWP is measured from the la tt er of CE or WE going l ow to the ea rli er of CE or
WP
going high.
WE
and tDS are measur ed from the earlier of CE or WE going high.
DH
READ Cycle Time 70 ns
RC
Access Time 70 ns
Chip Enable Low to Output Valid 70 ns
CO
Output Enable Low to Output Valid 35 ns
OE
Chip Enable or Output Enable Low to Output Transition 5 ns
Output Hold from Address Change 5 ns
(2)
Chip Enable or Output Enable High to Output Hi-Z 25 ns
(2)
Output Hi-Z from WE 25 ns
WRITE Cycle Time 70 ns
(3)
WE, CE Pulse Width 50 ns
Address Setup Time 0 ns
AW
WRITE Recovery Time 15 ns
Address Hold Time from WE 0ns
Output Active from WE 5ns
(4)
Data Setup Time 30 ns
(4)
Data Hold Time from WE 0ns
(4)
Data Hold Time from CE 10 ns
Parameter
(1)
M48T251Y–70
Min Max
Unit
9/24
M48T251Y, M48T251V
Table 4. Memory AC Characteristics, M48T251V
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AXQX
t
EHQZ
t
GHQZ
t
WLQZ t
t
AVAV
t
WLWH
t
ELEH
t
AVEL
t
AVWL
t
EHAX t
t
WHAX
t
WHQX
t
DVEH
t
DVWH
t
WHDX
t
EHDX
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (except where noted).
2. These paramet ers are sampled with a 5 pF load are not 100% tested.
3. t
4. t
5. t
t
t
ACC
t
t
t
COE
t
t
OD
ODW
t
WC
t
WP1
t
WP2
t
WR1
t
WR2
t
OEW
t
DS
t
DH1
t
DH2
is specified as the logical AND of CE and WE. tWP is measured from the la tt er of CE or WE going l ow to the ea rli er of CE or
WP
going high.
WE
is a function of the latter occu rring edge of WE or CE.
WR
and tDS are measur ed from the earlier of CE or WE going high.
DH
READ Cycle Time 85 ns
RC
Access Time 85 ns
Chip Enable Low to Output Valid 85 ns
CO
Output Enable Low to Output Valid 45 ns
OE
Chip Enable or Output Enable Low to Output Transition 5 ns
Output Hold from Address Change 5 ns
OH
(2)
Chip Enable or Output Enable High to Output Hi-Z 35 ns
(2)
Output Hi-Z from WE 30 ns
WRITE Cycle Time 85 ns
(3)
WRITE Enable Pulse Width 65 ns
Chip Enable Pulse Width 75 ns
Address Setup Time 0 ns
AW
(4)
WRITE Recovery Time 15 ns
Address Hold Time from WE 5ns
Output Active from WE 5ns
(5)
Data Setup Time 35 ns
(5)
Data Hold Time from WE 0ns
Data Hold Time from CE 15 ns
Parameter
(1)
M48T251V–85
Min Max
Unit
10/24
Data Retention Mode
M48T251Y, M48T251V
Data can be read or written only when V
greater than V
. When VCC is below V
PFD
PFD
CC
(the
is
point at which write protection occurs), the clock
registers and the SRAM are blocke d from any access. When V
Over threshold (V
to battery backup (V
V
CC
falls below the Battery Switch
CC
), the device is switched from
SO
). RTC operation and
BAT
SRAM data are maintained via battery backup until power is stable. All control, data, and address
signals must be powered down when V
is pow-
CC
ered down.
The lithium power source is designed to provide
power for RTC activity as well as RTC and RAM
PHANTO M CLOCK OPERATION
Communication with the Phantom Clock is established by pattern recogn ition of a s erial bit -stream
of 64 bits which must be matched by executing 64
consecutive WRITE cycles containing the proper
data on DQ0.
All accesses which occur prior to recognition of the
64-bit pattern are directed to memory.
After recognition is established, the next 64 READ
or WRITE cycles either extract or update data in
the clock while disabling the memory.
Data transfer to and from the timekeeping function
is accomplished with a serial bit-stream under control of Chip Enable (CE
WRITE Enable ( WE
the C E
and OE control of the clock starts the pa ttern recognition sequence by moving the pointer to
the first bit of the 64-bit comparison register (see
Figure 8., page 12).
Next, 64 consecutive WRITE cy cles are ex ecut ed
using the CE
and WE control of the device. These
64 WRITE cycles are used only to gain access to
the clock. Therefore, any addres s to the me mory
is acceptable. However, the WRITE cycles generated to gain access to the Phantom Clock are also
writing data to a location in the mated RAM. The
preferred way to manage this requirement is to set
), Output Enable (OE), and
). Initially , a READ cycle using
data retention when V
is absent or unstable.
CC
The capa bility of this sour ce is suffic ien t to po wer
the device continuously for th e life of the equipment into which it has been installed. For specification purposes, life expectanc y is ten (10) years
at 25°C with the internal oscillator running without
. Each unit is shipped with its energy source
V
CC
disconnected, guaranteeing full energy capacity.
When V
V
PFD
is first applied at a level greater than
CC
, the energy source is enabled for battery
backup operation. The actual life expectancy will
be much longer if no battery en ergy is used (e.g.,
when V
is present).
CC
aside just one address location in RAM as a Phantom Clock scratch pad.
When the first WRITE cycle is executed, it is compared to Bit 1 of the 64-bit comparison register. If
a match is found, the pointer increments to the
next location of the comparison register and
awaits the next WRITE cycle.
If a match is not found, the pointer does not advance and all subsequent WRITE cycles are ignored. If a READ cycle occurs at any t ime during
pattern recognition, the present sequence is aborted and the comparison register pointer is reset.
Pattern recognition continues for a total of 64
WRITE cycles as described above until all of the
bits in the comparison register have been
matched. With a correct match for 64-bits, the
Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The
next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depend ing
on the level of the OE
pin or the WE pin. Cycles to
other locations outside the memo ry block can be
interleaved with CE
cycles without interrupting the
pattern recognition sequence or data t ransfer sequence to the Phantom Clock.
11/24
M48T251Y, M48T251V
Figure 8. Comparison Register Definition
65 432
1
0
BYTE 0
7
1
Hex
1
0
1
0
0
10
Value
C5
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
01
10
01
10
01
10
01
3A
A3
5C
C5
3A
A3
5C
AI04262
Note: Th e odd s of this pat ter n being acc ide ntall y dupli cat ed and se ndin g abe rrant entrie s to the RTC is less tha n 1 in 1019. This pattern is
sent to the clock LSB to MSB.
12/24
M48T251Y, M48T251V
Clock Register Information
Clock information is contained in eight registers of
8 bits, each of which is sequentially accessed one
(1) bit at a time after the 64-bit pattern recognition
sequence has been completed. When updating
the clock registers, each must be handled in
groups of 8 bits. Writing and reading individual bits
within a register could produce erroneous results.
These READ/WRITE registers are defined in the
clock register map (see Table 5.).
Data contained in the clock regis ters is in Binary
Coded Decimal format (BCD). Reading and writing
the registers is always accomplished by stepping
through all eight registers, starting with Bit 0 of
Register 0 and ending with Bit 7 of Register 7.
Clock Accuracy
The RTC is guaranteed to keep time accuracy to
with ±1 minute per month at 25°C. The clock is factory-tuned with special calibration elements, and
does not require addition al calibration. Moderate
temperature deviation will have a negligible effect
in most app lic at io ns.
AM-PM/12/2 4 Mo de
Bit 7 of the hours register is defined as the 12-hour
or 24-hour mode select bit. When it is high, the 12hour mode is selected. In the 12-hour mo de, Bit 5
is the AM/PM bit with the logic high being “PM.” In
the 24-hour mode, Bit 5 is the second 10-hour bit
(20-23 hours).
Oscillator and Reset Bits
Bits 4 and 5 of the day register are used to control
the reset and oscillator functions. Bit 4 controls the
reset pin input. When the reset bit is set to logic '1,'
the Reset Input pin is ignored. When the re set bit
logic is set to '0,' a low input on the reset pi n will
cause the device to abort data transfer without
changing data in the timekeeping registers. Reset
operates independently of all other inputs. Bit 5
controls the oscillator. When set to logic '0,' t he oscillator turns on and the RT C/calendar begins to
increment.
Zero Bits
Registers 1, 2, 3, 4, 5, and 6 contain one (1) or
more bits that will always read logic '0.' When writing to these locations, either a logic '1' or '0' is acceptable.
Table 5. Phantom Clock Register Map
Function/Range
Register D7 D6 D5 D4 D3 D2 D1 D0
0 0.1 Seconds 0.01 Seconds Seconds 00-99
1 0 10 Seconds Seconds Seconds 00-59
2 0 10 Minutes Minutes Minutes 00-59
312/240
400OSC
5 0 0 10 date Date: Day of the Month Date 01-31
6 0 0 0 10M Month Month 01-12
7 10 Years Year Year 00-99
Keys: A/P = AM/PM Bit
12/24 = 12 or 24-hour mode B i t
OSC
= Oscillator Bit
10 /
A/P
Hrs Hours (24 Hour Format) Hours
RST 0 Day of the Week Day 01-7
= Rese t B i t
RST
0 = Must be set to '0'
BCD Format
01-12/
00-23
13/24
M48T251Y, M48T251V
Figure 9. Phantom Clock READ Cycle
WE
tCW
tCO
CE
tOW
OE
tOEE
tCOE
Q
Figure 10. Phantom Clock WRITE Cycle
OE
tWP
tOE
tRC
tRR
tOD
tODO
DATA OUTPUT VALID
AI04259
tWC
tWR
WE
CE
D
Figure 11. Phantom Clock Reset
RST
tCW
tDS
DATA INPUT STABLE
tRST
tWR
tDH
t
DH
AI04261
AI04235
14/24
M48T251Y, M48T251V
Table 6. Phantom Clock AC Characteristics (M48T251Y)
Symbol
t
AVAV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AVAV
t
WLWH t
t
EHAX
t
DVEH
t
WHDX
t
EHDX
t
ELEH
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (except where noted).
2. These paramet ers are sampled with a 5 pF load and are not 100% te st ed.
3. t
4. t
5. t
t
t
t
t
COE
t
OEE
t
OD
t
ODO
t
t
WP
t
WR
t
DS
t
DH1
t
DH2
t
t
RST
is specified as the logical AND of CE and WE. tWP is measured from the la tt er of CE or WE going l ow to the ea rli er of CE or
WP
going high.
WE
is a function of the latter occu rring edge of WE or CE.
WR
and tDS are measur ed from the earlier of CE or WE going high.
DH
READ Cycle Time 65 ns
RC
CE Access Time 55 n s
CO
OE Access Time 55 ns
OE
CE to Output Low Z 5 ns
OE to Output Low Z 5 ns
(2)
CE to Output High Z 25 ns
(2)
OE to Output High Z 25 ns
READ Recovery 10 ns
RR
WRITE Cycle Time 65 ns
WC
(3)
WRITE Pulse Width 55 ns
(4)
WRITE Recovery 10 ns
(5)
Data Setup Time 30 ns
(5)
Data Hold Time from WE 0ns
(5)
Data Hold Time from CE 0ns
CE Pulse Width 55 ns
CW
RST Pulse Width 65 ns
Parameter
(1)
Min Typ Max Unit
15/24
M48T251Y, M48T251V
Table 7. Phantom Clock AC Characteristics (M48T251V)
Symbol
t
AVAV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AVAV
t
WLWH t
t
EHAX
t
DVEH
t
WHDX
t
EHDX
t
ELEH
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (except where noted).
2. These paramet ers are sampled with a 5 pF load and are not 100% te st ed.
3. t
4. t
5. t
t
t
t
t
COE
t
OEE
t
OD
t
ODO
t
t
WP
t
WR
t
DS
t
DH1
t
DH2
t
t
RST
is specified as the logical AND of CE and WE. tWP is measured from the la tt er of CE or WE going l ow to the ea rli er of CE or
WP
going high.
WE
is a function of the latter occu rring edge of WE or CE.
WR
and tDS are measur ed from the earlier of CE or WE going high.
DH
READ Cycle Time 85 ns
RC
CE Access Time 85 n s
CO
OE Access Time 85 ns
OE
CE to Output Low Z 5 ns
OE to Output Low Z 5 ns
(2)
CE to Output High Z 30 ns
(2)
OE to Output High Z 30 ns
READ Recovery 20 ns
RR
WRITE Cycle Time 85 ns
WC
(3)
WRITE Pulse Width 60 ns
(4)
WRITE Recovery 20 ns
(5)
Data Setup Time 35 ns
(5)
Data Hold Time from WE 0ns
(5)
Data Hold Time from CE 0ns
CE Pulse Width 65 ns
CW
RST Pulse Width 85 ns
Parameter
(1)
Min Typ Max Unit
16/24
MAXIMUM RA T ING
M48T251Y, M48T251V
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
not implied. Exposure to Absol ute Max imum Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
ed in the Operating sections of this specification is
Table 8. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
STG
(1)
T
SLD
V
CC
V
IO
I
O
P
D
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
No preheat above 150°C, or direct expos u re to IR reflow (or I R preheat) allowed, to avoid damaging the Li thium batter y.
CAUTION! Negative undershoots below -0.3V are not allowed on any pin while i n the Battery Ba ck-up Mode.
Operating Temperature 0 to 70 °C
Storage Temperature (VCC, Oscillator Off)
Lead Solder Temperature for 10 seconds 260 °C
Supply Voltage (on any
pin relative to Ground)
Input or Output Voltages
Output Current 20 mA
Power Dissipation 1 W
M48T251Y –0.3 to +7.0 V
M48T251V –0.3 to +4.6 V
–40 to 85 °C
–0.3 to V
CC
+ 0.3
V
17/24
M48T251Y, M48T251V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
ment Conditions listed in t he relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
derived from tests performed under the Meas ure-
Table 9. DC and AC Measurement Conditions
Parameter M48T251Y M48T251V
V
Supply Voltage
CC
Ambient Operating Temperature 0 to 70°C 0 to 70°C
Load Capacitance (C
Input Rise and Fall Times ≤ 5ns ≤ 5ns
Input Pulse Voltages 0 to 3V 0 to 3V
Input and Output Timing Ref. Voltages 1.5V 1.5V
Note: Output High Z is defined as the poi nt where data i s no longer driven (see Table 9., page 18).
)
L
4.5 to 5.5V 3.0 to 3.6V
100pF 50pF
Figure 12. AC Te sting Load Cir c uit
V
CCI
1.1 KΩ
DEVICE
UNDER
TEST
680 Ω
Note: 5 0pF for M48T251V.
CL = 50 pF
AI04240
Table 10. Capacitance
Symbol
C
IN
(3)
C
IO
Note: 1. Effec tive capacitance measure d wi t h power supp l y at 5V. Sampled on l y; not 100% tested.
2. At 25°C, f = 1MHz.
3. Out puts were deselected.
Input Capacitance 10 pF
Input / Output Capacitance 10 pF
Parameter
(1,2)
Min Max Unit
18/24
M48T251Y, M48T251V
Table 11. DC Characteristics
M48T251Y M48T251V
Sym
(2)
I
LI
I
LO
I
CC1
I
CC2
I
CC3
(3)
V
IL
(3)
V
IH
V
OL
V
OH
(3)
V
PFD
(3)
V
SO
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (except where noted).
2. RST
3. All voltages are referenced to Ground.
Parameter
Input Leakage Current
Output Leakage Current
Supply Current 85 50 mA
Supply Current (TTL
Standby)
VCC Power Supply
Current
Input Low Voltage –0.3 0.8 –0.3 0.6 V
Input High Voltage 2.2
Output Low Voltage
Output High Voltage
Power Fail Deselect 4.25 4.37 4.50 2.80 2.97 V
Battery Back-up
Switchover
(Pin 1) has an i nternal pull- up resistor.
(1)
Test Condition
0V ≤ V
0V ≤ V
CE
I
IN
OUT
= V
CE
= V
CCI
I
= 2.0 mA
OL
= –1.0 mA
OH
≤ V
≤ V
IH
– 0.2
Min Typ Max Min Typ Max
CC
CC
±1 ±1 µA
±1 ±1 µA
510 5 7mA
35 23mA
V
CC
+ 0.3
2.2
0.4 0.4 V
2.4 2.4 V
V
BA T
2.5 V
VCC + 0.3
Unit–70 –85
V
19/24
M48T251Y, M48T251V
Figure 13. Power Down/Up Mode AC Waveforms
V
CC
V
V
PFD
PFD
(max)
(min)
V
SO
tF
tFB
tR
tPD
CE
tDR
tREC
Table 12. Power Down/Up Trip Points DC Characteristics
Symbol
t
REC
t
F
t
FB
t
R
t
PD
(2)
t
DR
Note: 1. Valid for Ambient Op erating Temp erature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3. 0 to 3.6V (except where noted).
2. At 25°C, V
V
(max) to CE low
PFD
V
(max) to V
PFD
V
(min) to VSO VCC Fall Time
PFD
V
(min) to V
PFD
CE High to Power-Fail 0 µs
Expected Data Retention Time 10 Years
= 0V; the expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running.
CC
Parameter
(min) VCC Fall Time
PFD
(max) VCC Rise Time
PFD
(1)
Min Max Unit
1.5 2.5 ms
300
10
0
AI04236
µs
µs
µs
20/24
PACKAG E MECHANICAL INFORMAT ION
Figure 14. PMDIP32 – 32-pin Plastic Module DIP, Package Outline
M48T251Y, M48T251V
A1AL
S
B
e1
eA
e3
D
N
E
1
Note: D rawing is not to scale.
Table 13. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 9.27 9.52 0.365 0.375
A1 0.38 – 0.015 –
B 0.43 0.59 0.017 0.023
C 0.20 0.33 0.008 0.013
mm inches
C
PMDIP
D 42.42 43.18 1.670 1.700
E 18.03 18.80 0.710 0.740
e1 2.29 2.79 0.090 0.110
e3 34.29 41.91 1.350 1.650
eA 14.99 16.00 0.590 0.630
L 3.05 3.81 0.120 0.150
S 1.91 2.79 0.075 0.110
N3232
21/24
M48T251Y, M48T251V
PART NUMBERING
Table 14. Ordering Information Example
Example: M48T 251Y –70 PM 1 TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
251Y = V
251V = V
Speed
–70 = 70ns (M48T251Y)
–85 = 85ns (M48T251V)
= 4.5 to 5.5V; V
CC
= 3.0 to 3.6V; V
CC
= 4.25 to 4.50V
PFD
= 2.80 to 2.97V
PFD
Package
PM = PMDIP32
Temperature Range
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
22/24
REVISION HISTORY
Table 15. Document Revision History
Date Version Revision Details
June 2001 1.0 First Issue
20-May-02 1.1 Add countries to disclaimer
28-Mar-03 2.0 v2.2 template applied; test condition updated (Table 12)
22-Feb-05 3.0 Reformatted; IR reflow update (Table 8)
M48T251Y, M48T251V
23/24
M48T251Y, M48T251V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics a ssumes no responsibility fo r the c onsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authori zed for use as criti cal component s in life support devices or sys tems without express written approval of STMicroele ct ronics.
The ST logo is a registered trademark of STMi croelectronics.
All other nam es are the property of their r espective owners
© 2005 STMi croelectroni cs - All rights reserved
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24/24
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