ST M41T11 User Manual
M41T11
Serial real-time clock (RTC) with 56 bytes of NVRAM
Datasheet − production data
Features
■ Counters for seconds, minutes, hours, day,
date, month, years and century
■ 32 KHz crystal oscillator integrating load
capacitance (12.5 pF) providing exceptional
oscillator stability and high crystal series
resistance operation
■ Serial interface supports I
protocol)
■ Ultra-low battery supply current of 0.8 µA (typ.
at 3 V)
■ 2.0 to 5.5 V clock operating voltage
■ Automatic switchover and deselect circuitry
■ 56 bytes of general purpose RAM
■ Software clock calibration to compensate
crystal deviation due to temperature
■ Automatic leap year compensation
■ Operating temperature of –40 to 85°C
■ Packaging includes a 28-lead SOIC and
SNAPHAT
®
top (to be ordered separately;
3.3 V to 5.0 V supply voltage only)
■ RoHS compliant
– Lead-free second level interconnect
2
C bus (100 kHz
8
1
SO8
®
SNAPHAT
battery & crystal
28
1
SOH28
June 2012 Doc ID 6103 Rev 10 1/30
This is information on a product in full production.
www.st.com
1
Contents M41T11
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Preferred initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/30 Doc ID 6103 Rev 10
M41T11 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. SO8 – 8-lead plastic small outline (150 mils body width) package mechanical data . . . . . 23
Table 12. SOH28 – 28-lead plastic small outline, battery SNAPHAT
Table 13. SH – 4-pin SNAPHAT
Table 14. SH – 4-pin SNAPHAT
Table 15. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. SNAPHAT
®
battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
®
housing for 48 mAh battery & crystal, package mechanical data . 25
®
housing for 120 mAh battery & crystal, package mech. data . . . . 26
Table 17. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
®
package mechanical data. . . 24
Doc ID 6103 Rev 10 3/30
List of figures M41T11
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. 8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Alternate read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. AC testing input/output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. SO8 – 8-lead plastic small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT
Figure 18. SH – 4-pin SNAPHAT
Figure 19. SH – 4-pin SNAPHAT
Figure 20. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
®
housing for 48 mAh battery & crystal package outline . . . . . . . . . 25
®
housing for 120 mAh battery & crystal, package outline. . . . . . . . 26
®
package outline. . . . . . . . . . . 24
4/30 Doc ID 6103 Rev 10
M41T11 Description
1 Description
The M41T11 is a low-power serial real-time clock (RTC) with 56 bytes of NVRAM. A built-in
32.768 kHz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used
for the clock/calendar function and are configured in binary-coded decimal (BCD) format.
Addresses and data are transferred serially via a two-line bidirectional bus. The built-in
address register is incremented automatically after each write or read data byte.
The M41T11 clock has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply during power failures. The energy needed to
sustain the RAM and clock operations can be supplied from a small lithium coin cell.
Typical data retention time is in excess of 5 years with a 50 mA/h, 3 V lithium cell. The
M41T11 is supplied in an 8-lead plastic small outline package or 28-lead SNAPHAT
®
package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing containing the battery and crystal. The unique
design allows the SNAPHAT battery package to be mounted on top of the SOIC package
after the completion of the surface mount process. Insertion of the SNAPHAT housing after
reflow prevents potential battery and crystal damage due to the high temperatures required
for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately. For the 28-lead SOIC, the
battery/crystal package (i.e. SNAPHAT) part number is “M4Txx-BR12SH” (see Table 16 on
page 27).
Caution: Do not place the SNAPHAT battery/crystal package “M4Txx-BR12SH” in conductive foam
since this will drain the lithium button-cell battery.
Figure 1. Logic diagram
V
V
CC
BAT
OSCI
OSCO
SCL
Doc ID 6103 Rev 10 5/30
M41T11
V
SS
SDA
FT/OUT
AI01000
Description M41T11
Table 1. Signal names
OSCI Oscillator input
OCSO Oscillator output
FT/OUT Frequency test/output driver (open drain)
SDA Serial data address input/output
SCL Serial clock
V
BAT
V
CC
V
SS
Battery supply voltage
Supply voltage
Ground
Figure 2. 8-pin SOIC connections
M41T11
OSCI V
V
BAT
SS
Figure 3. 28-pin SOIC connections
NC V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
AI01001
M41T11
8
7
6
5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI03606
CC
FT/OUTOSCO
SCL
SDAV
CC
NC
FT/OUT
NC
NC
NC
NC
NC
SCL
NC
NC
NC
SDA
NC
6/30 Doc ID 6103 Rev 10
M41T11 Description
Figure 4. Block diagram
OSCI
OSCO
FT/OUT
V
CC
V
SS
V
BAT
SCL
SDA
OSCILLATOR
32.768 kHz
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
SERIAL
BUS
INTERFACE
DIVIDER
CONTROL
LOGIC
ADDRESS
REGISTER
1 Hz
SECONDS
MINUTES
CENTURY/HOURS
DAY
DATE
MONTH
YEAR
CONTROL
RAM
(56 x 8)
AI02566
Doc ID 6103 Rev 10 7/30
Operation M41T11
2 Operation
The M41T11 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:
st
● 1
● 2
● 3
● 4
● 5
● 6
● 7
● 8
● 9
byte: seconds register
nd
byte: minutes register
rd
byte: century/hours register
th
byte: day register
th
byte: date register
th
byte: month register
th
byte: years register
th
byte: control register
th
- 64th bytes: RAM
The M41T11 clock continually monitors V
fall below V
, the device terminates an access in progress and resets the device address
SO
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out of tolerance system. When V
the device automatically switches over to the battery and powers down into an ultra low
current mode of operation to conserve battery life. Upon power-up, the device switches from
battery to V
at VSO and recognizes inputs.
CC
2.1 2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
for an out of tolerance condition. Should VCC
CC
falls below VSO,
CC
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
8/30 Doc ID 6103 Rev 10
M41T11 Operation
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.1.4 Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
2.1.5 Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 5. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
Doc ID 6103 Rev 10 9/30
STOP
CONDITION
AI00587
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