M41T11
Serial real-time clock (RTC) with 56 bytes of NVRAM
Datasheet − production data
Features
■ Counters for seconds, minutes, hours, day,
date, month, years and century
■ 32 KHz crystal oscillator integrating load
capacitance (12.5 pF) providing exceptional
oscillator stability and high crystal series
resistance operation
■ Serial interface supports I
protocol)
■ Ultra-low battery supply current of 0.8 µA (typ.
at 3 V)
■ 2.0 to 5.5 V clock operating voltage
■ Automatic switchover and deselect circuitry
■ 56 bytes of general purpose RAM
■ Software clock calibration to compensate
crystal deviation due to temperature
■ Automatic leap year compensation
■ Operating temperature of –40 to 85°C
■ Packaging includes a 28-lead SOIC and
SNAPHAT
®
top (to be ordered separately;
3.3 V to 5.0 V supply voltage only)
■ RoHS compliant
– Lead-free second level interconnect
2
C bus (100 kHz
8
1
SO8
®
SNAPHAT
battery & crystal
28
1
SOH28
June 2012 Doc ID 6103 Rev 10 1/30
This is information on a product in full production.
www.st.com
1
Contents M41T11
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Preferred initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/30 Doc ID 6103 Rev 10
M41T11 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. SO8 – 8-lead plastic small outline (150 mils body width) package mechanical data . . . . . 23
Table 12. SOH28 – 28-lead plastic small outline, battery SNAPHAT
Table 13. SH – 4-pin SNAPHAT
Table 14. SH – 4-pin SNAPHAT
Table 15. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. SNAPHAT
®
battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
®
housing for 48 mAh battery & crystal, package mechanical data . 25
®
housing for 120 mAh battery & crystal, package mech. data . . . . 26
Table 17. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
®
package mechanical data. . . 24
Doc ID 6103 Rev 10 3/30
List of figures M41T11
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. 8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Alternate read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. AC testing input/output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. SO8 – 8-lead plastic small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT
Figure 18. SH – 4-pin SNAPHAT
Figure 19. SH – 4-pin SNAPHAT
Figure 20. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
®
housing for 48 mAh battery & crystal package outline . . . . . . . . . 25
®
housing for 120 mAh battery & crystal, package outline. . . . . . . . 26
®
package outline. . . . . . . . . . . 24
4/30 Doc ID 6103 Rev 10
M41T11 Description
1 Description
The M41T11 is a low-power serial real-time clock (RTC) with 56 bytes of NVRAM. A built-in
32.768 kHz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used
for the clock/calendar function and are configured in binary-coded decimal (BCD) format.
Addresses and data are transferred serially via a two-line bidirectional bus. The built-in
address register is incremented automatically after each write or read data byte.
The M41T11 clock has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply during power failures. The energy needed to
sustain the RAM and clock operations can be supplied from a small lithium coin cell.
Typical data retention time is in excess of 5 years with a 50 mA/h, 3 V lithium cell. The
M41T11 is supplied in an 8-lead plastic small outline package or 28-lead SNAPHAT
®
package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing containing the battery and crystal. The unique
design allows the SNAPHAT battery package to be mounted on top of the SOIC package
after the completion of the surface mount process. Insertion of the SNAPHAT housing after
reflow prevents potential battery and crystal damage due to the high temperatures required
for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately. For the 28-lead SOIC, the
battery/crystal package (i.e. SNAPHAT) part number is “M4Txx-BR12SH” (see Table 16 on
page 27).
Caution: Do not place the SNAPHAT battery/crystal package “M4Txx-BR12SH” in conductive foam
since this will drain the lithium button-cell battery.
Figure 1. Logic diagram
V
V
CC
BAT
OSCI
OSCO
SCL
Doc ID 6103 Rev 10 5/30
M41T11
V
SS
SDA
FT/OUT
AI01000
Description M41T11
Table 1. Signal names
OSCI Oscillator input
OCSO Oscillator output
FT/OUT Frequency test/output driver (open drain)
SDA Serial data address input/output
SCL Serial clock
V
BAT
V
CC
V
SS
Battery supply voltage
Supply voltage
Ground
Figure 2. 8-pin SOIC connections
M41T11
OSCI V
V
BAT
SS
Figure 3. 28-pin SOIC connections
NC V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
AI01001
M41T11
8
7
6
5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI03606
CC
FT/OUTOSCO
SCL
SDAV
CC
NC
FT/OUT
NC
NC
NC
NC
NC
SCL
NC
NC
NC
SDA
NC
6/30 Doc ID 6103 Rev 10
M41T11 Description
Figure 4. Block diagram
OSCI
OSCO
FT/OUT
V
CC
V
SS
V
BAT
SCL
SDA
OSCILLATOR
32.768 kHz
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
SERIAL
BUS
INTERFACE
DIVIDER
CONTROL
LOGIC
ADDRESS
REGISTER
1 Hz
SECONDS
MINUTES
CENTURY/HOURS
DAY
DATE
MONTH
YEAR
CONTROL
RAM
(56 x 8)
AI02566
Doc ID 6103 Rev 10 7/30
Operation M41T11
2 Operation
The M41T11 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:
st
● 1
● 2
● 3
● 4
● 5
● 6
● 7
● 8
● 9
byte: seconds register
nd
byte: minutes register
rd
byte: century/hours register
th
byte: day register
th
byte: date register
th
byte: month register
th
byte: years register
th
byte: control register
th
- 64th bytes: RAM
The M41T11 clock continually monitors V
fall below V
, the device terminates an access in progress and resets the device address
SO
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out of tolerance system. When V
the device automatically switches over to the battery and powers down into an ultra low
current mode of operation to conserve battery life. Upon power-up, the device switches from
battery to V
at VSO and recognizes inputs.
CC
2.1 2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
for an out of tolerance condition. Should VCC
CC
falls below VSO,
CC
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
8/30 Doc ID 6103 Rev 10
M41T11 Operation
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.1.4 Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
2.1.5 Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 5. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
Doc ID 6103 Rev 10 9/30
STOP
CONDITION
AI00587
Operation M41T11
Figure 6. Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
SCLK FROM
MASTER
START
12 89
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
MSB LSB
Figure 7. Bus timing requirements sequence
SDA
tHD:STAtBUF
tR
SCL
SP
1. P = STOP and S = START
tF
tHIGH
tLOW
tSU:DAT
tHD:DAT
SR
AI00601
tHD:STA
tSU:STOtSU:STA
P
AI00589
10/30 Doc ID 6103 Rev 10
M41T11 Operation
Table 2. AC characteristics
Symbol Parameter
(1)
Min Max Unit
f
SCL
t
LOW
t
HIGH
t
t
t
HD:STA
t
SU:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling
edge of SCL.
SCL clock frequency 0 100 kHz
Clock low period 4.7 µs
Clock high period 4 µs
SDA and SCL rise time 1 µs
R
SDA and SCL fall time 300 ns
F
START condition hold time
(after this period the first clock pulse is generated)
START condition setup time
(only relevant for a repeated start condition)
Data setup time 250 ns
(2)
Data hold time 0 µs
STOP condition setup time 4.7 µs
Time the bus must be free before a new transmission can start 4.7 µs
2.2 Read mode
In this mode, the master reads the M41T11 slave after setting the slave address (see
Figure 8). Following the write mode control bit (R/W
address A
address are repeated, followed by the READ mode control bit (R/W
master transmitter becomes the master receiver. The data byte which was addressed will be
transmitted and the master receiver will send an acknowledge bit to the slave transmitter
(see Figure 9). The address pointer is only incremented on reception of an acknowledge bit.
The M41T11 slave transmitter will now place the data byte at address A
master receiver reads and acknowledges the new byte and the address pointer is
incremented to A
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
is written to the on-chip address pointer. Next the START condition and slave
n
n
+ 2.
4µs
4.7 µs
= 0) and the acknowledge bit, the word
= 1). At this point, the
+ 1 on the bus. The
n
An alternate READ mode may also be implemented, whereby the master reads the M41T11
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 10 on page 12).
Doc ID 6103 Rev 10 11/30
Operation M41T11
Figure 8. Slave address location
R/W
START A
Figure 9. Read mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
START
S
SLAVE
ADDRESS
R/W
ADDRESS (An)
ACK
WORD
SLAVE ADDRESS
MSB
0100011
START
S
ACK
ADDRESS
STOP
SLAVE
LSB
AI00602
R/W
DATA n DATA n+1
ACK
ACK
ACK
DATA n+X
P
NO ACK
Figure 10. Alternate read mode sequence
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
12/30 Doc ID 6103 Rev 10
START
S
SLAVE
ADDRESS
R/W
DATA n DATA n+1 DATA n+X
ACK
ACK
ACK
AI00899
STOP
PSDA LINE
ACK
NO ACK
AI00895
M41T11 Operation
2.3 Write mode
In this mode the master transmitter transmits to the M41T11 slave receiver. Bus protocol is
shown in Figure 11. Following the START condition and slave address, a logic '0' (R/W
= 0)
is placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T11
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte.
2.4 Data retention mode
With valid VCC applied, the M41T11 can be accessed as described above with read or write
cycles. Should the supply voltage decay, the M41T11 will automatically deselect, write
protecting itself when V
Figure 11. Write mode sequence
falls (see Figure 15).
CC
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
START
S
ADDRESS
SLAVE
R/W
WORD
ADDRESS (An)
ACK
DATA n DATA n+1 DATA n+X
ACK
ACK
ACK
STOP
PSDA LINE
ACK
AI00591
Doc ID 6103 Rev 10 13/30
Clock operation M41T11
3 Clock operation
The eight byte clock register (see Ta bl e 3 ) is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are
contained within the first three registers. Bits D6 and D7 of clock register 2 (hours register)
contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1'
will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century
(depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2
of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of
month), month and years. The final register is the control register (this is described in the
clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a
'1' will cause the oscillator to stop. If the device is expected to spend a significant amount of
time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'
the oscillator restarts within one second.
Note: In order to guarantee oscillator startup after the initial power-up, set the ST bit to a '1,' then
reset this bit to a '0.' This sequence enables a “kick start” circuit which aids the oscillator
startup during worst case conditions of voltage and temperature.
The seven clock registers may be read one byte at a time, or in a sequential block. The
control register (address location 7) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the seven clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
delayed by 250 ms to allow the read to be completed before the update occurs. This will
prevent a transition of data during the read.
Note: This 250 ms delay affects only the clock register update and does not alter the actual clock
time.
14/30 Doc ID 6103 Rev 10
M41T11 Clock operation
Table 3. Register map
Address
D7 D6 D5 D4 D3 D2 D1 D0
0 ST 10 seconds Seconds Seconds 00-59
1 X 10 minutes Minutes Minutes 00-59
(2)
2CEB
3 X X X X X Day Day 01-07
4 X X 10 date Date Date 01-31
5 X X X 10 M. Month Month 01-12
6 10 years Years Year 00-99
7 OUT FT S Calibration Control
1. Keys:
S = SIGN bit
FT = FREQUENCY TEST bit
ST = STOP bit
OUT = Output level
X = Don’t care
CEB = Century enable bit
CB = Century bit
2. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the
initial value set). When CEB is set to '0', CB will not toggle.When CEB is set to '1', CB will toggle from '0' to
'1' or from '1' to '0' every 100 years (dependent upon the initial value set). When CEB is set to '0', CB will
not toggle.
CB 10 hours Hours Century/hours 0-1/00-23
(1)
Data
Function/range
BCD format
3.1 Clock calibration
The M41T11 is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M41T11 improves to better than ±2 ppm
at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 12 on page 17).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome trim capacitors. The M41T11 design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 13 on page 17. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five-bit calibration byte found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The calibration byte occupies the five lower order bits (D4-D0) in the control register (addr
7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
Doc ID 6103 Rev 10 15/30
Clock operation M41T11
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T11 may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure. All the
designer has to do is provide a simple utility that accessed the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of some test equipment. When the frequency test (FT) bit, the seventh-most significant bit in
the control register, is set to a '1', and the oscillator is running at 32,768 Hz, the FT/OUT pin
of the device will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and
direction of oscillator frequency shift at the test temperature.
For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency
error, requiring a –10(XX001010) to be loaded into the calibration byte for correction. Note
that setting or changing the calibration byte does not affect the frequency test output
frequency.
3.2 Output driver pin
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the
contents of D7 of the control register. In other words, when D6 of location 7 is a zero and D7
of location 7 is a zero and then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is open drain which requires an external pull-up resistor.
3.3 Preferred initial power-on defaults
Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit
will be set to a '1'. All other register bits will initially power on in a random state.
16/30 Doc ID 6103 Rev 10
M41T11 Clock operation
Figure 12. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
ΔF
= K x (T –T
F
K = –0.036 ppm/°C2 ± 0.006 ppm/°C
TO = 25°C ± 5°C
0 10203040506070
Temperature °C
2
)
O
2
80–10–20–30–40
AI00999b
Figure 13. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Doc ID 6103 Rev 10 17/30
Maximum ratings M41T11
4 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
T
T
STG
T
SLD
V
IO
V
CC
I
O
P
1. Lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (the time above 255°C must not
exceed 30 seconds).
Ambient operating temperature –40 to 85 °C
A
SNAPHAT
®
–40 to 85
Storage temperature (VCC off, oscillator off)
SOIC –55 to 125
(1)
Lead solder temperature for 10 seconds 260 °C
Input or output voltages –0.3 to 7 V
Supply voltage –0.3 to 7 V
Output current 20 mA
Power dissipation 0.25 W
D
°C
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT
®
sockets.
18/30 Doc ID 6103 Rev 10
M41T11 DC and AC parameters
5 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in Tab l e 5 :
Operating and AC measurement conditions. Designers should check that the operating
conditions in their projects match the measurement conditions when using the quoted
parameters.
Table 5. Operating and AC measurement conditions
Parameter M41T11 Unit
Supply voltage (V
Ambient operating temperature (T
Load capacitance (C
) 2.0 to 5.5
CC
) –40 to 85 °C
A
) 100 pF
L
Input rise and fall times ≤ 50 ns
(1)
(2)
V
Input pulse voltages 0.2VCC to 0.8V
Input and output timing ref. voltages 0.3V
1. Output Hi-Z is defined as the point where data is no longer driven.
2. Supply voltage for SOH28 is 3.3 V to 5.5 V.
to 0.7V
CC
Figure 14. AC testing input/output waveform
0.8V
0.2V
CC
CC
0.7V
0.3V
AI02568
CC
CC
CC
CC
V
V
Doc ID 6103 Rev 10 19/30
DC and AC parameters M41T11
Table 6. Capacitance
Symbol Parameter
(1)(2)
Min Max Unit
C
C
OUT
t
LP
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs deselected.
Table 7. DC characteristics
Symbol Parameter Test Condition
I
LI
I
LO
I
CC1
I
CC2
V
IL
V
IH
V
OL
V
BAT
I
BAT
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
3. After switchover (VSO), V
4. For rechargeable back-up, V
Input capacitance (SCL) 7 pF
IN
(3)
Output capacitance (SDA, FT/OUT) 10 pF
Low-pass filter input time constant (SDA and SCL) 250 1000 ns
Input leakage current 0V ≤ VIN ≤ V
Output leakage current 0V ≤ V
OUT
≤ V
(1)
CC
CC
Min Typ Max Unit
Supply current Switch frequency = 100 kHz 300 µA
Supply current (standby) SCL, SDA = VCC – 0.3 V 70 µA
Input low voltage –0.3 0.3V
Input high voltage 0.7V
CC
VCC + 0.5 V
Output low voltage IOL = 3 mA 0.4 V
Pull-up supply voltage
(open drain)
(2)
Battery supply voltage 2.5
Battery supply current
(min) can be 2.0 V for crystal with RS = 40 KΩ.
BAT
BAT
(max) may be considered VCC.
oscillator ON, V
FT/OUT 5.5 V
(3)
33.5
= 25°C, VCC = 0 V,
T
A
BAT
= 3 V
0.8 1 µA
±1 µA
±1 µA
CC
(4)
V
V
Table 8. Crystal electrical characteristics
Symbol Parameter
f
R
C
1. These values are externally supplied if using the SO8 package. STMicroelectronics recommends the KDS
DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD)
quartz crystal for industrial temperature operations. Please refer to the KDS website for further information
on this crystal type.
2. Load capacitors are integrated within the M41T11. Circuit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
3. All SNAPHAT
4. ESR (max) = 110 kΩ for VCC or V
Resonant frequency 32.768 kHz
O
Series resistance 60
S
Load capacitance 12.5 pF
L
®
battery:crystal tops meet these specifications.
(1)(2)(3)
BAT
> 2.5 V.
20/30 Doc ID 6103 Rev 10
Min Typ Max Unit
(4)
kΩ
M41T11 DC and AC parameters
Figure 15. Power down/up mode AC waveforms
V
CC
VSO
SDA
SCL
Table 9. Power down/up AC characteristics
Symbol Parameter
tPD
DON'T CARE
(1)(2)
Min Max Unit
tREC
AI00596
t
t
REC
PD
SCL and SDA at VIH before power down 0 ns
SCL and SDA at VIH after power up 10 µs
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
fall time should not exceed 5 mV/µs.
2. V
CC
Table 10. Power down/up trip points DC characteristics
Symbol Parameter
(4)
V
SO
Battery backup switchover voltage V
(1)(2)
Min Typ Max
– 0.80 V
BAT
– 0.50 V
BAT
(3)
– 0.30 V
BAT
Unit
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
2. All voltages referenced to V
3. In 3.3 V application, if initial battery voltage is ≥ 3.4 V, it may be necessary to reduce battery voltage (i.e.,
through wave soldering the battery) in order to avoid inadvertent switchover/deselection for VCC – 10%
operation.
SS
.
4. Switchover and deselect point.
Doc ID 6103 Rev 10 21/30
Package mechanical data M41T11
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
22/30 Doc ID 6103 Rev 10
M41T11 Package mechanical data
Figure 16. SO8 – 8-lead plastic small outline package outline
h x 45˚
A2
b
e
D
8
1
1. Drawing is not to scale.
Table 11. SO8 – 8-lead plastic small outline (150 mils body width) package
E1
A
ccc
E
A1
L
L1
c
0.25 mm
GAUGE PLANE
k
SO-A
mechanical data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27– –0.050– –
h 0.25 0.50 0.010 0.020
k 0°8° 0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
Doc ID 6103 Rev 10 23/30
Package mechanical data M41T11
Figure 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT® package
outline
A2
Be
D
N
1
SOH-A
1. Drawing is not to scale.
Table 12. SOH28 – 28-lead plastic small outline, battery SNAPHAT® package
CP
E
H
A
C
eB
LA1 α
mechanical data
mm inches
Symb
Typ Min Max Typ Min Max
A3.050.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e1.27– –0.050– –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N28 28
CP 0.10 0.004
24/30 Doc ID 6103 Rev 10
M41T11 Package mechanical data
Figure 18. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal package
outline
A1
A
eA
D
E
1. Drawing is not to scale.
Table 13. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package
B
eB
SHTK-A
A3
A2
L
mechanical data
mm inches
Symb
Typ Min Max Typ Min Max
A9.780.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
Doc ID 6103 Rev 10 25/30
Package mechanical data M41T11
Figure 19. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package
outline
A1
A
eA
D
E
1. Drawing is not to scale.
Table 14. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package
B
eB
SHTK-B
A3
A2
L
mech. data
mm inches
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
26/30 Doc ID 6103 Rev 10
M41T11 Part numbering
7 Part numbering
Table 15. Ordering information scheme
Example: M41T 11 M 6 F
Device type
M41T
Supply voltage
11 = V
= 2.0 to 5.5 V
CC
Package
M = SO8 (150 mil width)
(2)
MH
= SOH28
(1)
Temperature range
6 = –40 to 85°C
Shipping method
®
F = ECOPACK
1. SOH28 supply voltage is 3.3 V to 5.5 V.
2. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately (see
Table 16).
package, tape & reel
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Table 16. SNAPHAT® battery table
Part Number Description Package
M4T28-BR12SH Lithium battery (48 mAh) SNAPHAT SH
M4T32-BR12SH Lithium battery (120 mAh) SNAPHAT SH
Doc ID 6103 Rev 10 27/30
Environmental information M41T11
8 Environmental information
Figure 20. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
28/30 Doc ID 6103 Rev 10
M41T11 Revision history
9 Revision history
Table 17. Revision history
Date Revision Changes
03-Oct-2007 7
Added lead-free second level interconnect information to cover page and Section 6:
Package mechanical data; some text changes; updated Ta bl e 4 .
02-May-2008 8 Updated Figure 16, Tab l e 1 1 , 15.
08-Jan-2009 9
Updated Ta b le 4 , Section 6: Package mechanical data;
added Section 8: Environmental information.
Added ESR footnote to Table 8: Crystal electrical characteristics
11-Jun-2012 10
Removed shipping method in tubes from Table 15: Ordering information scheme
Updated Section 8: Environmental information
Minor textual updates
Doc ID 6103 Rev 10 29/30
M41T11
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30/30 Doc ID 6103 Rev 10
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