ST M41T00S User Manual
FEAT URES SUMMARY
■ 2.0 TO 5.5V CLOCK OPERATING VO LT AG E
■ COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY
■ SOFTWARE CLOCK CALIBRATION
■ AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY (FIXED
REFERENCE)
–V
■ SERIAL INTERFACE SUP PORT S I
(400kHz PROTOCOL)
■ LOW OPERATING CURRENT OF 300µA
■ OSCILLATOR STOP DETECTION
■ BATTERY OR SUPER-CAP BACK- U P
■ OPERATING TEMPE RATURE OF –40 TO
85°C
■ ULTRA-LOW BATTER Y SUPPLY CURRE NT
OF 1µA
= 2.7 to 5.5V
CC
2.5V ≤ V
PFD
≤ 2.7V
2
C BUS
M41T00S
Seria l Access R eal-Time Clock
Figure 1. Packages
8
1
SO8 (M)
8-pin SOIC
1/23December 2004
M41T00S
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 9. Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.Clock Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Oscillator Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Driver Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/23
M41T00S
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10.Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11.AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16.SO8 – 8-lead Plastic Small Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mech. Data . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M41T00S
SUMMARY DESCRIPTION
The M41T00S Serial Access TIMEKEEPER
SRAM is a low power Serial RTC with a built-in
32.768kHz oscillator (external crystal controlled).
Eight bytes of the SRA M (see Table 2., page 11)
are used for the c lock/calendar function and are
configured in binary coded decimal (BCD) form at.
Addresses and data are transferred serially via a
two line, bi-directional I
address register is incre mented automatically after each WRITE or READ data byte.
The M41T00S ha s a built-in power sense c ircuit
which detects power failures and automatically
Figure 2. Logic Diagram
(1)
XI
(1)
XO
SCL
SDA
V
V
CC
M41T00S
2
C interface. The built-in
BAT
FT/OUT
®
switches to the battery supply when a power f ailure occurs. The energy needed to sustain the
clock operations can be supplied by a small lithium
button supply when a power failure o ccurs. The
eight clock address locations contain the cent ury,
year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29
(leap year - valid until year 2100), 30 and 31 day
months are made automatically.
The M41T00S is supplied in an 8-pin SOIC.
Table 1. Signal Names
(1)
XI
(1)
XO
FT/OUT
SDA Serial Data Input/Output
SCL Serial Clock Input
Oscillator Input
Oscillator Output
Frequency Test / Output Driver
(Open Drain)
V
SS
Note: 1. For SO8 package on l y.
AI09165
V
BA T
V
CC
V
SS
Note: 1. For SO8 package on l y.
Battery Supply Voltage
Supply Voltage
Ground
Figure 3. 8-pin SOIC (M) Connections
V
1
XI
2
XO
V
BAT
V
SS
Note: 1. Open Drain Output
M41T00S
3
45
8
CC
7
FT/OUT
6
SCL
SDA
AI09166
(1)
4/23
Figure 4. Block Diagram
CRYSTAL
32KHz
OSCILLATOR
M41T00S
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL
CIRCUIT
RTC &
CALIBRATION
SDA
SCL
V
CC
V
Note: 1. Open Drain Output
BAT
FREQUENCY TEST
FT
FT/OUT
(1)
I2C
INTERFACE
OUTPUT DRIVER
WRITE
PROTECT
V
SO
V
COMPARE
PFD
OUT
INTERNAL
POWER
AI09168
5/23
M41T00S
OPERATION
The M41T00S clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave address (D0h). The 8 bytes contained in the dev ice
can then be accessed sequentially in the following
order:
1. Seconds Register
2. Minutes Register
3. Century/Hours Register
4. Day Register
5. Date Register
6. Month Register
7. Year Register
8. Calibration Register
The M41T00S clock continually monitors V
an out-of-tolerance condition. S hould V
low V
, the device terminates an access in
PFD
CC
progress and resets t he device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data f rom bei ng wri tten
to the device from a an out-of-tolerance system.
Once V
(V
SO
falls below the switchover voltage
CC
), the device autom atically switches over to
the battery and powers down into an ultra-low current mode of operation to preserve battery life. If
is less than V
V
BAT
switched from V
. If V
V
BAT
BAT
to V
CC
is greater than V
power is switched from V
drops below V
PFD
switches from battery to V
rises above V
, it will recogn i z e th e i n puts.
PFD
, the device power is
PFD
when VCC drops below
BAT
CC
to V
, the device
PFD
when V
BAT
. Upon power-up, the device
at VSO. When V
CC
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
for
CC
fall be-
CC
CC
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock li nes remain
High.
Start data transfer. A change in the s tate of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A c hange in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. T he state of the data line rep resents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives o ut a m essag e is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are cal led
“slaves.”
Acknowledge. E ach by te of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transm itter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
6/23
Figure 5. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
M41T00S
START
CONDITION
Figure 6. Acknowledgement Sequence
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
12 89
MSB LSB
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
CLOCK PULSE FOR
ACKNOWLEDGEMENT
AI00601
7/23
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