ST M41T00CAP User Manual
with integral backup battery and crystal
Features
■ Real-time clock (RTC) with backup battery
integrated into package
■ Uses M41T00S enhanced RTC with precision
switchover reference
■ 400 kHz I
■ Automatic switchover and deselect circuitry
with fixed reference voltage
–V
– 2.6 V (typ) power-fail deselect (switchover)
■ Counters for seconds, minutes, hours, day,
date, month, year and century
■ Software clock calibration
■ Low operating current of 300 µA
■ Oscillator stop detection
■ Battery backup
■ Operating temperature of 0 to 70 °C
■ Self-contained battery and crystal in
CAPHAT™ DIP package
■ RoHS compliant
– Lead-free second level interconnect
2
C serial interface
= 2.7 to 5.5 V operating voltage range
CC
threshold
M41T00CAP
Serial access real-time clock (RTC)
Datasheet − production data
24
1
PCDIP24 (PC)
Battery/crystal CAPHAT
TM
March 2012 Doc ID 14557 Rev 5 1/27
This is information on a product in full production.
www.st.com
1
Contents M41T00CAP
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/27 Doc ID 14557 Rev 5
M41T00CAP Contents
9 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 14557 Rev 5 3/27
List of tables M41T00CAP
List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. TIMEKEEPER
Table 3. Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data . . . . . . . . . 23
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
®
register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4/27 Doc ID 14557 Rev 5
M41T00CAP List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 23
Figure 16. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 14557 Rev 5 5/27
Description M41T00CAP
1 Description
The M41T00CAP is a low-power serial real-time clock (RTC) with integral battery and
crystal in ST’s 24-pin CAPHAT™ package. It includes a crystal controlled, 32.768 kHz
oscillator and has a built-in power sense circuit which detects power failures and
automatically switches to the backup battery when a power failure occurs.
Eight registers comprise the clock/calendar function and are configured in binary-coded
decimal (BCD) format. Addresses and data are transferred serially via an industry standard,
two line, 400 kHz, bidirectional I
automatically after each WRITE or READ data byte. The internal lithium coin cell contains
ample energy to sustain timekeeping operation for 10 years in the absence of system power.
The eight clock address locations contain the century, year, month, date, day, hour, minute,
and second in 24-hour BCD format. Corrections for the number of days in a month, including
leap year, are made automatically (leap year valid up to year 2100).
Figure 1. Logic diagram
2
C interface. The built-in address register is incremented
V
CC
SCL
SDA
M41T00CAP
V
SS
FT/OUT
AI09165
6/27 Doc ID 14557 Rev 5
M41T00CAP Pin settings
2 Pin settings
2.1 Pin connection
Figure 2. DIP connections
1. DU is “don’t use”. Do not connect. Must be allowed to float. Do not connect to VCC or VSS.
2.2 Pin description
Table 1. Pin description
Symbol Name and function
FT/OUT Frequency test / output driver (open drain)
SDA Serial data input/output
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SS
1
2
3
4
5
6
M41T00CAP
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
FT/OUT
NC
NC
NC
NC
NC
NC
NC
SCLNC
SDA
(1)
DUV
AI01028
SCL Serial clock input
V
CC
V
SS
(1)
DU
NC No connection
1. DU is “don’t use”. Do not connect. Must be allowed to float. Do not connect to VCC or VSS.
Supply voltage
Ground
Do not use. Do not connect. Reserved for factory use.
Doc ID 14557 Rev 5 7/27
Pin settings M41T00CAP
Figure 3. Block diagram
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL
CIRCUIT
RTC &
CALIBRATION
CRYSTAL
32KHz
OSCILLATOR
SDA
SCL
V
CC
1. Open drain output
2
I
C
INTERFACE
LOGIC OUTPUT
WRITE
PROTECT
V
BAT
V
SO
FREQUENCY TEST
V
COMPARE
PFD
FT
OUT
INTERNAL
POWER
FT/OUT
(1)
AI09168
8/27 Doc ID 14557 Rev 5
M41T00CAP Operation
3 Operation
The M41T00CAP clock operates as a slave device on the I2C serial bus. Access is obtained
by implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1. Seconds register
2. Minutes register
3. Century/hours register
4. Day register
5. Date register
6. Month register
7. Year register
8. Calibration register
The M41T00CAP clock continually monitors V
V
fall below V
CC
, the device terminates an access in progress and resets the device
PFD
address counter. Inputs to the device will not be recognized at this time to prevent erroneous
data from being written to the device from a an out-of-tolerance system. Once V
below the switchover voltage (V
), the device automatically switches over to the battery
SO
and powers down into an ultra-low current mode of operation to prolong battery life. If V
is less than V
V
. If V
BAT
BAT
drops below V
V
rises above V
CC
, the device power is switched from VCC to V
PFD
is greater than V
. Upon power-up, the device switches from battery to VCC at VSO. When
PFD
, the inputs will be recognized.
PFD
, the device power is switched from VCC to V
PFD
For more information on battery storage life refer to application note AN1012.
3.1 Wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line, while the clock line is high, will be interpreted as control
signals.
for an out-of-tolerance condition. Should
CC
falls
CC
when VCC drops below
BAT
when VCC
BAT
BAT
Accordingly, the following bus conditions have been defined:
3.2 Bus not busy
Both data and clock lines remain high.
Doc ID 14557 Rev 5 9/27
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