ST M41T00AUD User Manual

Serial real-time clock (RTC) with audio

Features

Combination real-time clock with audio

■ Serial real-time clock (RTC) based on M41T00

■ Audio section provides:

– 300 mW differential audio amplifier – 256 and 512 Hz tone generation – –33 to +12 dB gain, 3 dB steps (16 steps

plus MUTE)

■ 0 °C to 70 °C operation

■ Small DFN16 package (5 mm x 4 mm)

Real-time clock details

■ Superset of M41T00

■ 3.0 to 3.6 V operation

– Timekeeping down to 1.7 V

■ Automatic backup switchover circuit

– Ultra-low 400 nA backup current at 3.0 V

(typ) – Suitable for battery or capacitor backup – On-chip trickle charge circuit for backup

capacitor

■ 400 kHz I

■ M41T00 compatible register set with counters

for seconds, minutes, hours, day, date, month, years, and century

– Automatic leap year compensation – HT bit set when clock goes into backup

■ RTC operates using 32,768 Hz quartz crystal

– Calibration register provides for

– Oscillator supports crystals with up to 40

■ Oscillator fail detect circuit OF bit indicates

when oscillator has stopped for four or more cycles

C bus

mode

adjustments of –63 to +126 ppm

kΩ series resistance, 12.5 pF load

capacitance

M41T00AUD

DFN16 (5 mm x 4 mm)

Audio section

■ Power amplifier

– Differential output amplifier – Provides 300 mW into 8 Ω

(THD+N = 2% (max), f

■ Summing node at audio input

– Inverting configuration with summing

resistors into the minus (-) terminal

– 0 dB gain with 10 kΩ feedback resistor and

20 kΩ input summing resistors – Signal input centered at V – 1.6 V

■ 256 or 512 Hz signal multiplexing with analog

analog input range (max)

P-P

input to provide audio with beep tones

■ Volume control, 4-bit register

– Allows gain adjustment from –33 dB to

+12 dB – 3 dB steps –MUTE bit

■ Audio automatically shuts off in backup mode

= 1 kHz)

February 2012 Doc ID 13480 Rev 5 1/42

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Contents M41T00AUD

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 M41T00AUD clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1.1 Halt bit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1.2 Oscillator fail detect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1.3 Trickle charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 Reading and writing the clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 Priority for IRQ

5.4 Switchover thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.5 Trickle charge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

/FT/OUT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1 Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . . 24

7 Audio section operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.1 Gain tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2 Wake-up time: T

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M41T00AUD Contents

8 Initial conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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List of tables M41T00AUD

List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. List of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. M41T00AUD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Priority for IRQ

Table 6. Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7. MUTE and GAIN values (V

Table 8. Initial values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. Input/output characteristics (25 °C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 13. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 14. RTC power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 15. RTC power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 16. Audio section electrical characteristics, valid for V

= 25 °C (except where otherwise noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 17. DFN16 (5 mm x 4 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

AMB

/FT/OUT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

= 3.3 V and ambient temperature = 25 °C). . . . . . . . . . . . . 29

= 3.3 V and

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M41T00AUD List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Typical hookup example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10. Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12. Counter update diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13. Switchover thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 14. Trickle charge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 15. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 16. Audio section diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 17. AC testing input/output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 18. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19. DFN16 (5 mm x 4 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 20. DFN16 (5 mm x 4 mm) footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Description M41T00AUD

1 Description

The M41T00AUD is a low-power serial real-time clock (RTC) with an integral audio section with tone generator and 300 mW output amplifier. The RTC is a superset of the M41T00 with enhancements such as a precision reference for switchover, an oscillator fail detect circuit, and storing of the time at power-down. The audio section includes a summing amplifier (inverting) at the input. An 8 kHz low-pass filter follows that with a 16-step programmable gain stage next. A 256 or 512 Hz audio tone can be switched into the filter in place of the input signal. From the gain stage, the 300 mW amplifier drives the output pins.

The M41T00AUD has a built-in power sense circuit which detects power failures and automatically switches to the backup input when V supplied by a capacitor or by a battery such as a lithium coin cell. The device includes a trickle charge circuit for charging the capacitor.

The RTC includes a built-in 32.768 kHz oscillator controlled by an external crystal. Eight register bytes are used for the clock/calendar functions and are superset compatible with the M41T00. Two additional registers control the audio section and the trickle charger. The 10 registers (see Ta bl e 2 ) are accessed over a 400 kHz I increments automatically after each byte READ or WRITE operation thus streamlining transfers by eliminating the need to send a new address for each byte to be transferred.

is removed. Backup power can be

C bus. The address register

Typical data retention times will be in excess of 5 years with a 50 mAh 3 V lithium cell (see RTC DC characteristics, Ta bl e 1 2 for more information).

Figure 1. Logic diagram

OSCI

BIAS

OSCO

IRQ/FT/OUT

SDA

BACK

SCL

AIN

M41T00AUD

FBK AOUT+ AOUT –

ai13322

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M41T00AUD Pin settings

2 Pin settings

2.1 Pin connection

Figure 2. Pin connection

2.2 Pin description

Table 1. Pin description

Symbol Name and function

OSCI Oscillator input

OSCO Oscillator output

SCL I

SDA I

AIN Audio input

OSCI

OSCO

IRQ/FT/OUT

BACK

SCL

SDA

1 2 3 4 5 6 7 8

Supply voltage

C serial clock

C serial data

16 15 14 13 12 11 10

AOUT–

AOUT+ FBK V

BIAS

AIN

ai13323

BIAS

AOUT– Analog out, 180 phase

AOUT+ Analog out, 0 phase

IRQ/FT/OUT

BACK

FBK

NC No connection

No name; exposed pad on back of IC package

Doc ID 13480 Rev 5 7/42

Input for decoupling capacitor

Ground

Interrupt output for oscillator fail detect, frequency test output for calibration, or discrete logic output

Backup supply voltage

Feedback; connect feedback resistor between this pin and AIN

Must be connected to ground

Application M41T00AUD

3 Application

Figure 3. Application diagram

M41T00AUD

OSCI

OSCO

I2C (SDA, SCL)

FBK

AIN

AUTOM ATIC

BATTERY

SWITCHOVER

& DESELEC T

REFERENCE

=2.80V

PFD

WRITE

PROTECT

400kHz I2C

INTER FACE

32KHz

OSCILL ATOR

TRICKLE CHARGE

INT

SECS

MINS

HOURS

DATE

DAY

MONTH

YEAR CENTURY BIT CALIBRATION

OUT

OSCILLATOR FAIL DETECT

256/512Hz

AUDIO

ADJ

BPF

GAIN

I2C

Audio-in

BACK

IRQ/FT/OUT

AOUT+ AOUT–

BIAS

ai13324

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M41T00AUD Application

Figure 4. Typical hookup example

3.3 V

SCL

SDA

R2 should

be a minimum

Audio

Set R1’s to 2x

R2 for unity gain

3.3V

32.768 kHz

Place near

pin 4

0.1 µF

3.3V

*optional

SCL 7

SDA 8

OSCI

OSCO

FBK

0.1 µF AIN

SWITCHOVER

V 4

BATTERY

I2C

32 KHz

OSC

PMH

M41T00AUD

TRICKLE CHARGE

Place near pin 15

1.0 µF

INT

RT C

256/512 Hz

ONE GEN

AUDIO SECTION

BIAS

Either/or, but not both

BACK

0.22 µF

(typical)

3.3 V

IRQ/FT/OUT

Optional connection to micro

AOUT+ AOUT–

Lithium Cell Battery (alternative)

Optional: can sum additional audio inputs

Package Metal Heatsink: exposed pad on back of

IC package

ai13325

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Operation M41T00AUD

4 Operation

The M41T00AUD clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 10 bytes contained in the device can then be accessed sequentially in the following order:

Table 2. List of registers

Byte address Contents

00h Seconds register

01h Minutes register

02h Century/hours register

03h Day register

04h Date register

05h Month register

06h Years register

07h Calibration/control register

08h Audio register

09h Control2 register

The M41T00AUD continually monitors VCC for an out of tolerance condition. Should VCC fall below V

, the device terminates an access in progress and resets the device address

PFD

counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When V

falls below VSO,

the device automatically switches over to the backup battery or capacitor and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to V

at VSO and recognizes inputs.

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M41T00AUD Operation

4.1 2-wire bus characteristics

This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is high.

Changes in the data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

● Bus not busy. Both data and clock lines remain high.

● Start data transfer. A change in the state of the data line, from high to low, while the

clock is high, defines the START condition.

● Stop data transfer. A change in the state of the data line, from low to high, while the

clock is high, defines the STOP condition.

● Data valid. The state of the data line represents valid data when after a start condition,

the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the message is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves".

● Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This

acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line high to enable the master to generate the STOP condition.

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Operation M41T00AUD

Figure 5. Serial bus data transfer sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CONDITION

CHANGE OF

DATA ALLOWED

Figure 6. Acknowledgement sequence

START

SCLK FROM MASTER

DATA OUTPUT BY TRANSMITTER

DATA OUTPUT BY RECEIVER

12 89

MSB LSB

Figure 7. Bus timing requirements sequence

STOP

CONDITION

AI00587

CLOCK PULSE FOR

ACKNOWLEDGEMENT

AI00601

SDA

HD:STA

LOW

HIGH

HD:DAT

SCL

BUF

Note: P = STOP and S = START

12/42 Doc ID 13480 Rev 5

SU:DAT

SU:STA

HD:STA

AI00589

SU:STO

M41T00AUD Operation

4.2 Characteristics

Table 3. AC characteristics

Symbol Parameter

(1)

Min Typ Max Units

SCL

LOW

HIGH

HD:STA

SU:STA

SU:DAT

HD:DAT

SU:STO

BUF

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).

2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.

SCL clock frequency 0 400 kHz

Clock low period 1.3 µs

Clock high period 600 ns

SDA and SCL rise time 300 ns

SDA and SCL fall time 300 ns

START condition hold time (after this period the first clock pulse is generated)

START condition setup time (only relevant for a repeated start condition)

(2)

Data setup time 100 ns

Data hold time 0 µs

STOP condition setup time 600 ns

Time the bus must be free before a new transmission can start

4.3 READ mode

600 ns

1.3 µs

In this mode, the master reads the M41T00AUD slave after setting the slave address (see

Figure 8). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the

word (register) address An is written to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge bit. The device slave transmitter will now place the data byte at address An+1 on the bus. The master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2.

This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter.

An alternate READ mode may also be implemented, whereby the master reads the M41T00AUD slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 10).

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