The M41T0 real-time clock is a low power serial real-time clock with a built-in 32.768 kHz
oscillator (external crystal controlled). Eight registers are used for the clock/calendar
function and are configured in binary coded decimal (BCD) format. Addresses and data are
transferred serially via a two-line bidirectional bus. The built-in address register is
incremented automatically after each WRITE or READ data byte.
The M41T0 is supplied in 8-lead plastic small outline package.
Figure 1.Logic diagram
V
CC
OSCI
SCL
Figure 2.SOIC connections
OSCIV
(1)
NF
SS
1. NF pin must be tied to VSS.
Table 1.Signal names
OSCIOscillator input
OCSOOscillator output
M41T0
V
SS
1
2
3
4
M41T0
8
7
6
5
AI07029
OSCO
SDA
OUT
AI07028
CC
OUTOSCO
SCL
SDAV
OUTOutput driver (open drain)
SDASerial data address input / output
SCLSerial clock
(1)
NF
V
CC
V
SS
1. NF pin must be tied to VSS.
No function
Supply voltage
Ground
Doc ID 9105 Rev 75/23
DescriptionM41T0
Figure 3.Block diagram
OSCI
OSCO
OSCILLATOR
32.768 kHz
DIVIDER
1 Hz
SECONDS
MINUTES
OUT
V
CC
V
SS
SCL
SDA
SERIAL
BUS
INTERFACE
CONTROL
LOGIC
ADDRESS
REGISTER
CENTURY/HOURS
DAY
DATE
MONTH
YEAR
CONTROL
AI07030
6/23 Doc ID 9105 Rev 7
M41T0Operation
2 Operation
The M41T0 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1.Seconds register
2. Minutes register
3. Century/hours register
4. Day register
5. Date register
6. Month register
7. Years register
8. Control register
2.1 2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●Data transfer may be initiated only when the bus is not busy.
●During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
Doc ID 9105 Rev 77/23
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