Datasheet M41ST87Y, M41ST87W Datasheet (ST)

M41ST87Y

M41ST87W

5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor
with tamper detection and 128 bytes of clearable NVRAM

Features

■ 5.0, 3.3, or 3.0 V operation

■ 400 kHz I

■ NVRAM supervisor to non-volatize external

LPSRAM

■ 2.5 to 5.5 V oscillator operating voltage

■ Automatic switchover and deselect circuitry

■ Choice of power-fail deselect voltages

– M41ST87Y:

– M41ST87W:

■ Two independent power-fail comparators

(1.25 V reference)

■ Counters for tenths/hundredths of seconds,

seconds, minutes, hours, day, date, month,
year, and century

■ 128 bytes of clearable, general purpose

NVRAM

■ Programmable alarm and interrupt function

(valid even during battery backup mode)

■ Programmable watchdog timer

■ Unique electronic serial number (8-byte)

■ 32 kHz frequency output available upon power-

on

■ Microprocessor power-on reset output

■ Battery low flag

■ Ultra-low battery supply current of 500 nA (typ)

2

C bus

(not recommended for new design, contact
ST sales office for availability)
THS = 1: V
THS = 0: V

THS = 1: V
THS = 0: V

≈ 4.63 V; VCC = 4.75 to 5.5 V

PFD

≈ 4.37 V; VCC = 4.5 to 5.5 V

PFD

≈ 2.9 V; VCC = 3.0 to 3.6 V

PFD

≈ 2.63 V; VCC = 2.7 to 3.6 V

PFD

Embedded crystal

28-pin, (300 mil)

SOX28

SSOP20

Security features

■ Tamper indication circuits with timestamp and

RAM clear

■ LPSRAM clear function (TP

■ Packaging includes a 28-lead, embedded

crystal SOIC and a 20-lead SSOP

■ Oscillator stop detection

CLR

)

October 2011 Doc ID 9497 Rev 10 1/54

www.st.com

1

Contents M41ST87Y, M41ST87W

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5 Tamper detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6 Tamper register bits (tamper 1 and tamper 2) . . . . . . . . . . . . . . . . . . . . . 18

2.6.1 Tamper enable bits (TEB1 and TEB2) . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.2 Tamper bits (TB1 and TB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6.3 Tamper interrupt enable bits (TIE1 and TIE2) . . . . . . . . . . . . . . . . . . . . 19

2.6.4 Tamper connect mode bit (TCM1 and TCM2) . . . . . . . . . . . . . . . . . . . . 19

2.6.5 Tamper polarity mode bits (TPM1 and TPM2) . . . . . . . . . . . . . . . . . . . . 19

2.6.6 Tamper detect sampling (TDS1 and TDS2) . . . . . . . . . . . . . . . . . . . . . . 22

2.6.7 Tamper current high/tamper current low (TCHI/TCLO1 and

TCHI/TCLO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.6.8 RAM clear (CLR1 and CLR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.6.9 RAM clear external (CLR1

package only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

and CLR2

EXT

) - available in SOX28

EXT

2.7 Tamper detection operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.8 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.9 Internal tamper pull-up/down current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.10 Avoiding inadvertent tampers (normally closed configuration) . . . . . . . . . 27

2.11 Tamper event time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.0.1 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Contents

3.1 TIMEKEEPER® registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.5 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.6 Full-time 32 kHz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.8 Reset inputs (RSTIN1

3.9 Power-fail comparators (1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.10 Power-fail outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.11 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.12 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.13 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.14 t

3.15 Electronic serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.16 Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.17 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

rec

& RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Doc ID 9497 Rev 10 3/54

List of tables M41ST87Y, M41ST87W

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Tamper detection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4. Tamper detection current (normally closed - TCM

Table 5. Tamper detect timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. Calculated cut-off frequency for typical capacitance and resistance values. . . . . . . . . . . . 27

Table 7. TIMEKEEPER

Table 8. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 9. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 10. Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 11. Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 12. t

Table 13. Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 14. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 15. DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 16. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 17. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 18. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 19. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 20. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal mechanical data . . . . 47

Table 21. SSOP20 – 20-lead, shrink, small outline package mechanical data. . . . . . . . . . . . . . . . . . 48

Table 22. Carrier tape dimensions for SOX28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 23. Reel dimensions for 24 mm carrier tape (SOX28 package) and 16 mm carrier tape

Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

rec

(SSOP20 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

®

register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

= '0') . . . . . . . . . . . . . . . . . . . . . . . . . . 23

X

4/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. 28-pin, 300 mil SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. 20-pin, SSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13. WRITE cycle timing: RTC & external SRAM control signals. . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14. Tamper detect connection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15. Basic tamper detect options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16. Tamper detect output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 17. Tamper detect sampling options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 18. Tamper current options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 19. Tamper output timing (with CLR1

package only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 20. RAM clear hardware hookup (SOX28 package only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 21. Low-pass filter implementation for noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 22. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 23. Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 24. Alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 25. Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 26. RSTIN1

Figure 27. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 28. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 29. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal outline. . . . . . . . . . . . 47

Figure 30. SSOP20 – 20-lead, shrink, small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 31. Carrier tape for SOX28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 32. Carrier tape for SSOP20 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 33. Reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

& RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

or CLR2

EXT

= '1') - available in SOX28

EXT

Doc ID 9497 Rev 10 5/54

Description M41ST87Y, M41ST87W

1 Description

The M41ST87Y/W secure serial RTC and NVRAM supervisor is a low power 1280-bit, static

CMOS SRAM organized as 160 bytes by 8 bits. A built-in 32.768 kHz oscillator (internal

crystal-controlled) and 8 bytes of the SRAM are used for the clock/calendar function and are

configured in binary coded decimal (BCD) format.

An additional 11 bytes of RAM provide calibration, status/control of alarm, watchdog,

tamper, and square wave functions. 8 bytes of ROM and finally 128 bytes of user RAM are

also provided. Addresses and data are transferred serially via a two line, bidirectional I

interface. The built-in address register is incremented automatically after each WRITE or

READ data byte. The M41ST87Y/W has a built-in power sense circuit which detects power

failures and automatically switches to the battery supply when a power failure occurs. The

energy needed to sustain the SRAM and clock operations can be supplied by a small lithium

button-cell supply when a power failure occurs.

Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm

interrupts, tamper detection, watchdog timer, and programmable square wave output. Other

features include a power-on reset as well as two additional debounced inputs (RSTIN1

RSTIN2

contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a

second in 24-hour BCD format. Corrections for 28, 29 (leap year), 30 and 31 day months are

made automatically.

) which can also generate an output reset (RST). The eight clock address locations

2

C

and

1.1 Security features

Two fully independent tamper detection Inputs allow monitoring of multiple locations within

the system. User programmable bits provide both normally open and normally closed switch

monitoring. Time stamping of the tamper event is automatically provided. There is also an

option allowing data stored in either internal memory (128 bytes), and/or external memory to

be cleared, protecting sensitive information in the event tampering occurs. By embedding

the 32 kHz crystal in the SOX28 package, the clock is completely isolated from external

tampering. An oscillator fail bit (OF) is also provided to ensure correct operation of the

oscillator.

The M41ST87Y/W is supplied in a 28-pin, 300 mil SOIC package which includes an

embedded 32 kHz crystal and a 20-pin SSOP package for use with an external crystal.

The SOIC and SSOP packages are shipped in plastic anti-static tubes or in tape & reel form.

The 300 mil, embedded crystal SOIC requires only a user-supplied battery to provide non-

volatile operation.

6/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Description

Figure 1. Logic diagram

XI

XO

SCL

SDA

EX

RSTIN1

RSTIN2

WDI

PFI

PFI

TP1

TP2

(4)

(4)

(3)

IN

IN

(3)

(3)

1

2

CC

V

BAT

V

M41ST87Y

M41ST87W

V

OUT

IRQ/OUT

SQW/FT

(3)

E

CON

(1)

RST

(1)

F

32k

(2)

PFO

1

(2)

PFO

2

(3)

TP

CLR

(1)

(2)

V

SS

1. Open drain output.

2. Programmable output (open drain or full-CMOS). Defaults to open drain on first power-up.

3. Available in SOX28 package only.

4. Available in SSOP package only.

AI07023

Doc ID 9497 Rev 10 7/54

Description M41ST87Y, M41ST87W

Figure 2. 28-pin, 300 mil SOIC connections

V

NF
NF
NF

NF
NC
NC

PFO

SQW/FT

WDI
RSTIN1
RSTIN2

PFO

PFI

V

SS

1
2
3
4
5
6
7

2

M41ST87Y

8

M41ST87W

9
10
11
12

1

13

2

14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CC
EX
IRQ/OUT
V

OUT

TP2

IN

PFI

1
SCL
F

32k

TP1

IN
RST
TP

CLR
SDA
E

CON

V

BAT

AI07025b

Note: No function (NF) and no connect (NC) pins should be tied to V

internally shorted together.

Figure 3. 20-pin, SSOP connections

V

CC
X1
X2

NC

PFO

SQW/FT

RSTIN1

PFO

PFI

V

SS

Note: No connect (NC) pin should be tied to V

1
2
3
4
5

2

M41ST87Y

M41ST87W

6
7
8

1

9

2

10

.

SS

20
19
18
17
16
15
14
13
12
11

IRQ/OUT
V

OUT

TP2

PFI
SCL

F

32k

TP1
RST

SDA
V

BAT

AI07025c

. Pins 1, 2, 3, and 4 are

SS

IN

1

IN

8/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Description

Table 1. Signal names

(1)

XI

(1)

XO

(2)

E

CON

(2)

EX

IRQ/OUT

(3)

Oscillator input

Oscillator output

Conditioned chip enable output

External chip enable

Interrupt/out output (open drain)

PFI

PFI

PFO

PFO

RST

1

2

(4)

1

(4)

2

(3)

Power fail input 1

Power fail input 2

Power fail output 1

Power fail output 2

Reset output (open drain)

RSTIN1 Reset 1 input

RSTIN2

(2)

Reset 2 input

SCL Serial clock input

SDA Serial data input/output

CC

OUT

SS

32k

CLR

BAT

(5)

(5)

(4)

(2)

Square wave output/frequency test

Watchdog input

Supply voltage

Voltage output

Ground

(3)

IN

IN

(2)

32 kHz square wave output (open drain)

Tamper pin 1 input

Tamper pin 2 input

Tamper pin RAM clear

Positive battery pin input

No function

No connect

SQW/FT

WDI

V

V

V

F

TP1

TP2

TP

V

NF

NC

1. Available in SSOP package only.

2. Available in SOX28 package only.

3. Open drain output.

4. Programmable output (open drain or full-CMOS).

5. Should be connected to VSS.

Doc ID 9497 Rev 10 9/54

Description M41ST87Y, M41ST87W

Figure 4. Block diagram

REAL TIME CLOCK

CALENDAR

128 BYTES

SDA

I2C

INTERFACE

SCL

(4)

Crystal

V

OUT

WDI

2

TPX

V

IN

CC

V

BAT

V

SS

XI

32KHz

OSCILLATOR

XO

(3)

V

BL

CLR

COMPARE

USER RAM

8 BYTES ROM

RTC w/ALARM

& CALIBRATION

WATCHDOG

SQUARE WAVE

X

TAMPER

BL

OFIE

AFE

WDS

CLRX

EXT

TIE

OUT

32k

CLR

(1)

(2)

(3)

(1)

IRQ/OUT

X

SQW/FT

TP

V

F

SO

PFD

COMPARE

COMPARE

COMPARE

POR

RST

E

CON

PFO

RSTIN1

RSTIN2

EX

PFI

V

V

(3)

(3)

1

1.25V
(Internal)

PFI

2

COMPARE

PFO

1.25V
(Internal)

AI07026

1. Open drain output.

2. Programmable output (open drain or full-CMOS); if open drain option is selected and if pulled-up to supply other than V
this supply must be equal to, or less than V

when VCC = 0 V (during battery backup mode).

BAT

3. Available in SOX28 package only.

4. Crystal is external on SSOP package and internal for the SOX28 package.

(1)

(3)

(2)

1

(2)

2

,

CC

10/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Description

Figure 5. Hardware hookup

Unregulated

Voltage

V

IN

Regulator

V

IN

3.3V

Regulator

For monitoring

of additional

voltage sources

Pushbutton

R1

R3

R2

R4

1. Available in SOX28 package only.

5V

Reset

M41ST87Y/W

V

CC

V

CC

V

CC

TP1

TP2

EX

SCL

WDI

IN

IN

(1)

(1)

RSTIN1

(1)

RSTIN2

PFI

1

PFI

2

V

SS

V

BAT

TP

CLR

V

OUT

E

CON

SDA

RST

SQW/FT

PFO

PFO

IRQ/OUT

F

32k

(1)

V

(1)

CC

E

Low-Power

SRAM

To Microprocessor

To LED Display

1

2

To NMI

To INT

To 32kHz

AI07027

Doc ID 9497 Rev 10 11/54

Operating modes M41ST87Y, M41ST87W

2 Operating modes

The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 160 bytes
contained in the device can then be accessed sequentially in the following order:

00h. Tenths/hundredths of a second register

01h. Seconds register

02h. Minutes register

03h. Century/hours register

04h. Day register

05h. Date register

06h. Month register

07h. Year register

08h. Control register

09h. Watchdog register

0Ah-0Eh. Alarm registers

0Fh. Flag register

10h-12h. Reserved

13h. Square wave

14h. Tamper register 1

15h. Tamper register 2

16h-1Dh. Serial number (8 bytes)

1Eh-1Fh. Reserved (2 bytes)

20h-9Fh. User RAM (128 bytes)

The M41ST87Y/W clock continually monitors V
V

fall below V

CC

, the device terminates an access in progress and resets the device

PFD

for an out-of-tolerance condition. Should

CC

address counter. Inputs to the device will not be recognized at this time to prevent erroneous
data from being written to the device from a an out-of-tolerance system. When V
below V

, the device automatically switches over to the battery and powers down into an

SO

CC

falls

ultra low current mode of operation to conserve battery life. As system power returns and
V

rises above VSO, the battery is disconnected, and the device is switched to external

CC

V

.

CC

Write protection continues until t

(min) elapses after VCC reaches V

rec

PFD

(min).

For more information on battery storage life refer to application note AN1012.

12/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Operating modes

2.1 2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a clock
signal (SCL) and a bidirectional data signal (SDA). The SDA line must be connected to a
positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is high.

● Changes in the data line, while the clock line is high, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1 Bus not busy

Both data and clock lines remain high.

2.1.2 Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.

2.1.3 Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.

2.1.4 Data valid

The state of the data line represents valid data when, after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”

2.1.5 Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this

Doc ID 9497 Rev 10 13/54

Operating modes M41ST87Y, M41ST87W

case the transmitter must leave the data line high to enable the master to generate the
STOP condition.

Figure 6. Serial bus data transfer sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CONDITION

DATA ALLOWED

Figure 7. Acknowledgement sequence

START

SCL FROM
MASTER

DATA OUTPUT
BY TRANSMITTER

DATA OUTPUT
BY RECEIVER

12 89

MSB LSB

Figure 8. Bus timing requirements sequence

SDA

CHANGE OF

STOP

CONDITION

AI00587

CLOCK PULSE FOR

ACKNOWLEDGEMENT

AI00601

t

HD:STA

t

t

LOW

t

F

HIGH

t

t

HD:DAT

t

R

SP

SCL

t

BUF

14/54 Doc ID 9497 Rev 10

SU:DAT

SR

t

t

SU:STA

HD:STA

P

AI00589

t

SU:STO

M41ST87Y, M41ST87W Operating modes

Table 2. AC characteristics

Symbol Parameter

f

SCL

t

BUF

t

EXPD

t

F

t

HD:DAT

t

HD:STA

t

HIGH

t

LOW

t

R

t

SU:DAT

t

SU:STA

t

SU:STO

1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).

2. Available in SOX28 package only.

3. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.

SCL clock frequency 0 400 kHz

Time the bus must be free before a new transmission can start 1.3 µs

(2)

EX to E

propagation delay

CON

SDA and SCL fall time 300 ns

(3)

Data hold time 0 µs

START condition hold time
(after this period the first clock pulse is generated)

Clock high period 600 ns

Clock low period 1.3 µs

SDA and SCL rise time 300 ns

Data setup time 100 ns

START condition setup time
(only relevant for a repeated start condition)

STOP condition setup time 600 ns

(1)

Min Max Unit

M41ST87Y 10 ns

M41ST87W 15 ns

600 ns

600 ns

2.2 READ mode

In this mode the master reads the M41ST87Y/W slave after setting the slave address (see

Figure 9 on page 16). Following the WRITE mode control bit (R/W

bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W
point the master transmitter becomes the master receiver.

The data byte which was addressed will be transmitted and the master receiver will send an
acknowledge bit to the slave transmitter. The address pointer is only incremented on
reception of an acknowledge clock. The M41ST87Y/W slave transmitter will now place the
data byte at address An+1 on the bus, the master receiver reads and acknowledges the new
byte and the address pointer is incremented to An+2.

This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter (see Figure 10 on page 16).

The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a stop condition or when
the pointer increments to a non-clock or RAM address.

Note: This is true both in READ mode and WRITE mode.

An alternate READ mode may also be implemented whereby the master reads the
M41ST87Y/W slave without first writing to the (volatile) address pointer. The first address
that is read is the last one stored in the pointer (see Figure 11 on page 16).

=0) and the acknowledge

=1). At this

Doc ID 9497 Rev 10 15/54

Operating modes M41ST87Y, M41ST87W

Figure 9. Slave address location

R/W

START A

Figure 10. READ mode sequence

BUS ACTIVITY:
MASTER

SDA LINE

BUS ACTIVITY:

START

S

SLAVE

ADDRESS

R/W

ADDRESS (An)

ACK

WORD

SLAVE ADDRESS

MSB

0100 011

START

S

ACK

ADDRESS

STOP

SLAVE

LSB

AI00602

R/W

DATA n DATA n+1

ACK

ACK

ACK

DATA n+X

P

NO ACK

Figure 11. Alternate READ mode sequence

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

16/54 Doc ID 9497 Rev 10

START

S

SLAVE

ADDRESS

R/W

DATA n DATA n+1 DATA n+X

ACK

ACK

AI00899

STOP

PSDA LINE

ACK

ACK

NO ACK

AI00895

M41ST87Y, M41ST87W Operating modes

2.3 WRITE mode

In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus
protocol is shown in Figure 12. Following the START condition and slave address, a logic '0'
(R/W

= 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The
M41ST87Y/W slave receiver will send an acknowledge clock to the master transmitter after
it has received the slave address (see Figure 9 on page 16) and again after it has received
the word address and each data byte.

Figure 12. WRITE mode sequence

BUS ACTIVITY:
MASTER

BUS ACTIVITY:

START

S

SLAVE

ADDRESS

R/W

WORD

ADDRESS (An)

ACK

DATA n DATA n+1 DATA n+X

ACK

ACK

Figure 13. WRITE cycle timing: RTC & external SRAM control signals

(1)

EX

t

EXPD

t

(1)

E

CON

1. Available in SOX28 package only.

EXPD

STOP

PSDA LINE

ACK

AI00591

ACK

AI03663

2.4 Data retention mode

With valid VCC applied, the M41ST87Y/W can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the M41ST87Y/W will automatically
deselect, write protecting itself (and any external SRAM) when V
(max) and V
accomplished by internally inhibiting access to the clock registers. At this time, the reset pin
(RST

) is driven active and will remain active until VCC returns to nominal levels. External
RAM access is inhibited in a similar manner by forcing E
within 0.2 volts of the V
of-tolerance condition. When V

(min) (see Figure 28 on page 46, Table 19 on page 46). This is

PFD

. E

BAT

falls between V

CC

to a high level. This level is

will remain at this level as long as VCC remains at an out-

CON

falls below the battery backup switchover voltage (VSO),

CC

CON

PFD

Doc ID 9497 Rev 10 17/54

Operating modes M41ST87Y, M41ST87W

power input is switched from the VCC pin to the battery, and the clock registers and external
SRAM are maintained from the attached battery supply.

All signal outputs become high impedance. The V

pin is capable of supplying 100µA of

OUT

current to the attached memory with less than 0.3 volts drop under this condition. On power
up, when V
E

. The RST signal also remains active during this time (see Figure 28 on page 46).

CON

returns to a nominal value, write protection continues for t

CC

by inhibiting

rec

Note: Most low power SRAMs on the market today can be used with the M41ST87Y/W RTC

SUPERVISOR. There are, however some criteria which should be used in making the final
choice of an SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M41ST87Y/W and
SRAMs to be “Don’t Care” once V
guarantee data retention down to V

falls below V

CC

= 2.0 volts. The chip enable access time must be

CC

(min). The SRAM should also

PFD

sufficient to meet the system needs with the chip enable output propagation delays
included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to
V

.

OUT

If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 volts. Manufacturers generally specify a typical
condition for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
use. The data retention current value of the SRAMs can then be added to the I

value of

BAT

the M41ST87Y/W to determine the total current requirements for data retention. The
available battery capacity for the battery of your choice can then be divided by this current to
determine the amount of data retention available.

For a further more detailed review of lifetime calculations, please see application note
AN1012.

2.5 Tamper detection circuit

The M41ST87Y/W provides two independent input pins, the tamper pin 1 input (TP1IN) and
tamper pin 2 input (TP2

), which can be used to monitor two separate signals which can

IN

result in the associated setting of the tamper bits (TB1 and/or TB2, in flag register 0Fh) if the
tamper enable bits (TEB1 and/or TEB2) are enabled, for the respective tamper 1 or tamper
2 channels. The TP1
by either 1) closing a switch to ground or V
that was previously closed to ground or V
the TCM

bits and the TPMX bits in the tamper register (14h and/or 15h).

X

pin or TP2IN pin may be set to indicate a tamper event has occurred

IN

(normally open), or by 2) opening a switch

OUT

(normally closed), depending on the state of

OUT

2.6 Tamper register bits (tamper 1 and tamper 2)

2.6.1 Tamper enable bits (TEB1 and TEB2)

When set to a logic '1,' this bit will enable the tamper detection circuit. This bit must be set to
'0' in order to clear the associated tamper bits (TB

Note: 1 TEB

2 When servicing a tamper interrupt, the TEB

should be cleared then set again whenever the tamper detect condition is modified.

X

x

set to 1 to again enable the tamper detect circuits.

18/54 Doc ID 9497 Rev 10

, in 0Fh).

X

bits must be cleared to clear the TBx bits, then

M41ST87Y, M41ST87W Operating modes

2.6.2 Tamper bits (TB1 and TB2)

If the TEBX bit is set, and a tamper condition occurs, the TBX bit will be set to '1.' This bit is
“Read-only” and is reset only by setting the TEB

bit to '0.' These bits are located in the flags

X

register 0Fh.

2.6.3 Tamper interrupt enable bits (TIE1 and TIE2)

If this bit is set to a logic '1,' the IRQ/OUT pin will be activated when a tamper event occurs.
This function is also valid in battery backup if the ABE bit (alarm in battery backup) is also
set to '1' (see Figure 15 on page 21).

Note: In order to avoid an inadvertent activation of the IRQ

/OUT pin due to a prior tamper event,

the flag register (0Fh) should be read prior to clearing and again setting the TEB

2.6.4 Tamper connect mode bit (TCM1 and TCM2)

This bit indicates whether the position of the external switch selected by the user is in the
normally open (TCM

= '1') or normally closed (TCMX= '0') position (see Figure 14 on

X

page 20 and Figure 16 on page 21).

2.6.5 Tamper polarity mode bits (TPM1 and TPM2)

The state of this bit indicates whether the tamper pin input will be taken high (to V
TPM

= '1') or low (to VSS if TPMX = '0') to trigger a tamper event (see Figure 14 on page 20

X

and Figure 16 on page 21).

X

bit.

OUT

if

Doc ID 9497 Rev 10 19/54

Operating modes M41ST87Y, M41ST87W

Figure 14. Tamper detect connection options

NORMALLY

OPEN

(TCMX = 1)

NORMALLY

CLOSED

(TCMX = 0)

III.

TAMPER LO

(TPMX = 0)

I.

TP

IN

(2)

V

OUT

TP

IN

TCHI/TCLO = 1

TCHI/TCLO = 0

II.

IV.

V

CC

(3)

TAMPER HI

(TPMX = 1)

(1)

V

OUT

TP

IN

V

OUT

TCHI/TCLO = 0TCHI/TCLO = 1

(Int)

Note: These options are summarized in Ta bl e 3 .

1. If the CLRX

2. If the CLRX

3. Optional external resistor to V

bit is set, a second tamper to V

EXT

bit is set, a second tamper to V

EXT

allows the user to bypass sampling when power is “on.”

CC

(TPM2 = '1') during t

OUT

(TPM2 = '1') will trigger automatically.

OUT

will not be detected.

CLR

Table 3. Tamper detection truth table

Option Mode TCM

OUT

(1)

(1)

I Normally open/tamper to GND

II Normally open/tamper to V

III Normally closed/tamper to GND 0 0

IV Normally closed/tamper to V

1. No battery current drawn during battery backup.

OUT

X

10

11

01

AI07075

TPM

X

20/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Operating modes

Figure 15. Basic tamper detect options

Triggering Event Tamper Event Output

V

(V

CC

TCM

, TPM

, TPM

, TPM

, TPM

X

X

X

X

= 1,1

= 0,0

= 1,0

= 0,1

V

CC

TCM

TCM

TCM

X

X

X

X

1. Available in SOX28 package only.

)

OUT

NORMALLY OPEN

(V

)

OUT

NORMALLY CLOSED

NORMALLY OPEN

NORMALLY CLOSED

TAMPER HI,

TAMPER LO,

TAMPER LO,

TAMPER HI,

VCC (V

OUT

IRQ - Interrupt the

TIE

User

Configuration

CLRX

CLRX

)

TCM

, TPM

X

X

processor on tamper

X

TP

RAM on tamper

EXT

CLR - Clear internal
RAM on tamper

Time stamp tamper
event

- Clear external

CLR

AI07818

(1)

Figure 16. Tamper detect output options

User

Configuration

TIE

1

CLR1

EXT

TP1

TEB1

TP2

TEB2

1. Available in SOX28 package only.

CLR1

TIE

CLR2

CLR2

2

EXT

(other reset sources)

IRQ - Interrupt the
processor on tamper

- Clear external

TP

CLR

RAM on tamper

RESET OUT

CLR - Clear 128 bytes
internal RAM on tamper

Time stamp tamper
event (to RTC)

AI07821

(1)

Doc ID 9497 Rev 10 21/54

Operating modes M41ST87Y, M41ST87W

2.6.6 Tamper detect sampling (TDS1 and TDS2)

This bit selects between a 1Hz sampling rate or constant monitoring of the tamper input
pin(s) to detect a tamper event when the normally closed switch mode is selected. This
allows the user to reduce the current drain when the TEB

bit is enabled while the device is

X

in battery backup (see Table 4 on page 23 and Figure 17 on page 23). Sampling is disabled
if the TCM

bit is set to logic '1' (Normally Open). In this case the state of the TDSX bit is a

X

“Don’t care.”

Note: The crystal oscillator must be “on” for sampling to function. If the oscillator is stopped, the

tamper detect circuit will revert to continuous monitoring.

2.6.7 Tamper current high/tamper current low (TCHI/TCLO1 and TCHI/TCLO2)

This bit selects the strength of the internal pull-up or pull-down used during the sampling of
the normally closed condition. The state of the TCHI/TCLO
open (TCM

= '1') mode (see Figure 18 on page 24).

X

bit is a “Don’t care” for normally

X

2.6.8 RAM clear (CLR1 and CLR2)

When either CLR1 or CLR2 and the TEBX bit are set to a logic '1,' the internal 128 bytes of
user RAM (see Figure 15 on page 21) will be cleared to all zeros in the event of a tamper
condition. Furthermore, the 128 bytes of user RAM will be deselected (inaccessible) until
the corresponding TEB
the cleared RAM values cannot be accessed.)

bit is reset to '0.' Any data read during this time will be invalid. (ie.

X

2.6.9 RAM clear external (CLR1

and CLR2

EXT

) - available in SOX28

EXT

package only

When either CLR1
the TP

signal will be asserted for clearing external RAM, and the RST output asserted

CLR

upon detection of a tamper event (see Figure 15 on page 21 and Figure 20 on page 25).

Note: The reset output resulting from a tamper event will be the same as a reset resulting from a

power-down condition, a watchdog time-out, or a manual reset (RSTIN1
RST

output will be asserted for t

This is accomplished by forcing TP
regulator (see Figure 20 on page 25) will also switch off V
of power to the V
tamper occurs during battery back-up (see Figure 19 on page 24). By inhibiting the DC
regulator, the user will also prevent other inputs from sourcing current to the external SRAM,
which would allow it to retain data otherwise.

The user may optionally connect an inverting charge pump to the V
SRAM (see Figure 20 on page 25). Depending on the process technology used for the
manufacturing of the external SRAM, clearing the memory may require varying durations of
negative potential on the V
the time needed for their particular application. Control Bits CLRPW0 and CLRPW1
determine the duration TP

page 25).

Note: When using the inverting charge pump, the user must also provide isolation in the form of

two additional small-signal power MOSFETs. These will isolate the V

EXT

CC

or CLR2

pin. V

is set to a logic '1' and the TEBX bit is also set to logic '1,'

EXT

or RSTIN2); the

seconds.

rec

high, which if used to control the inhibit pin of the DC

CLR

will automatically be disconnected from the battery if the

OUT

pin. This device configuration will allow the user to program

CC

will be enabled (see Figure 19 on page 24 and Tabl e 5 o n

CLR

, depriving the external SRAM

OUT

pin of the external

CC

pin from both the

OUT

22/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Operating modes

negative voltage generated by the charge pump during a tamper condition, and from being
pulled to ground by the output of the charge pump when it is in shut-down mode (SHDN
logic low). The gates of both MOSFETs should be connected to TP

as shown in

CLR

=

Figure 20 on page 25. One n-channel enhancement MOSFET should be placed between

the output of the inverting charge pump and the V
should be an enhancement mode p-channel, and placed between V
and V

of the external SRAM. When TP

CC

goes high after a tamper condition occurs, the

CLR

of the M41ST87. The other MOSFET

OUT

of the M41ST87

OUT

n-channel MOSFET will turn on and the p-channel will turn off. During normal operating
conditions, TP

will be low and the p-channel will be on, while the n-channel will be off.

CLR

Table 4. Tamper detection current (normally closed - TCM

TDS

X

TCHI/TCLO

X

Tamper circuit mode Current at 3.0 V (typ)

= '0')

X

(1)(2)

0 0 Continuous monitoring / 10 MΩ pull-up/-down 0.3 µA

0 1 Continuous monitoring / 1 MΩ pull-up/-down 3.0 µA

1 0 Sampling (1 Hz) / 10 MΩ pull-up/-down 0.3 nA

1 1 Sampling (1 Hz) / 1 MΩ pull-up/-down 3.0 nA

1. When calculating battery lifetime, this current should be added to I

2. Per tamper detect input

current listed in Table 17 on page 44.

BAT

Figure 17. Tamper detect sampling options

V

(V

CC

V

CC

)

OUT

NORMALLY OPEN

(V

)

OUT

NORMALLY CLOSED

NORMALLY OPEN

NORMALLY CLOSED

TAMPER HI,

TAMPER LO,

TAMPER LO,

TAMPER HI,

VCC (V

OUT

CONTINUOUS
MONITORING

TDS

TDS

X

X

= 0

= 1

User

Configuration

TCMX, TPM

X

CONTINUOUS

MONITORING

SAMPLED

MONITORING

CONTINUOUS
MONITORING

)

TDS

TDS

= 0

X

= 1

X

AI07819

CONTINUOUS

MONITORING

SAMPLED

MONITORING

Unit

Doc ID 9497 Rev 10 23/54

Operating modes M41ST87Y, M41ST87W

Figure 18. Tamper current options

(V

V

CC

V

CC

)

OUT

NORMALLY OPEN

(V

)

OUT

NORMALLY CLOSED

NORMALLY OPEN

TAMPER HI,

TAMPER LO,

TAMPER LO,

TCHI/TCLO = 1

VCC (V

TCHI/TCLO = 0

)

OUT

CONTINUOUS

MONITORING

CONTINUOUS

MONITORING

SAMPLED

MONITORING

User Configuration

CONTINUOUS
MONITORING

User Configuration

TDS

TDS

X

X

= 0

= 1

User

Configuration

TCMX, TPM

TP

X

(TP1, TP2)

X

TAMPER HI,

NORMALLY CLOSED

TCHI/TCLO = 1

TCHI/TCLO = 0

Figure 19. Tamper output timing (with CLR1

only

TP

CLR

RST

V

OUT

IRQ/OUT

E

CON

(1)

(3)

Tamper

Event

(TB Bit set)

t

CLRD

t

CLR

High-Z

High-Z

(2)

or CLR2

EXT

TDS

TDS

= 0

X

= 1

X

AI07820

(4)

AI07083

CONTINUOUS

MONITORING

SAMPLED

MONITORING

= '1') - available in SOX28 package

EXT

t

rec

1. If connected to a negative charge pump device, this pin must be isolated from the charge pump by using both n-channel

and p-channel MOSFETs as illustrated in Figure 20 on page 25.

2. If the device is in battery back-up; NOT on V

in SOX28 package only on page 22). V

3. If TIE

= '1.'

X

OUT

(see Section 2.6.9: RAM clear external (CLR1

CC

is forced to GND during a tamper event when on VCC.

and CLR2

EXT

) - available

EXT

4. If ABE = '1' and device is in battery backup mode.

24/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Operating modes

Table 5. Tamper detect timing

Symbol Parameter

(1)

t

CLRD

t

CLR

1. With input capacitance = 70 pF and resistance = 50 Ω.

2. If the OF bit is set, t

Tamper RAM clear ext delay X X 1.0

Tamper clear timing

(min) = 0.5 ms.

CLRD

CLRPW1CLRPW

0

Min Typ Max Unit

(2)

1.5 2.0 ms

00 1 s

01 4 s

10 8 s

11 16 s

Figure 20. RAM clear hardware hookup (SOX28 package only)

Inverting

Charge

Inhibit

V

IN

5V

Regulator

Pump

OUTIN

SHDN

M41ST87Y/W

V

CC

V

CC

TP1

TP2

EX

SCL

WDI

TP

CLR

IN

IN

E

V

OUT

CON

SDA

CAP+ CAP–

(2)

Negative Output

(–1 x VIN)

(1)

V

CC

E

Low-Power

SRAM

To RST

To LED Display

To NMI

To INT

To 32kHz

AI07804

Pushbutton

Reset

RSTIN1

RSTIN2

PFI

1

PFI

2

V

SS

V

BAT

RST

SQW/FT

PFO

PFO

IRQ/OUT

F

32k

1

2

1. Most inverting charge pumps drive OUT to ground when device shut down is enabled (SHDN = logic low). Therefore, an n-

channel enhancement mode MOSFET should be used to isolate the OUT pin from the V

2. In order to avoid turning on an on-chip parasitic diode when driving V

MOSFET should be used to isolate the V

pin from the negative voltage generated by the inverting charge pump.

OUT

negative, a p-channel enhancement mode

OUT

of the M41ST87.

OUT

Doc ID 9497 Rev 10 25/54

Operating modes M41ST87Y, M41ST87W

2.7 Tamper detection operation

The tamper pins are triggered based on the state of an external switch. Two switch mode
options are available, normally open or normally closed, based on the setting of the tamper
connect mode bit (TCM
tamper pin will be triggered by being connected to V
(if the TPM

bit is set to '1'), through the closing of the external switch. When the external

X

switch is closed, the tamper bit (TB
if the device has been physically tampered with. If the selected switch mode is normally
closed (TCM

= '0'), the tamper pin will be triggered by being pulled to VSS or to V

X

(depending on the state of the TPM
result of opening the external switch.

When a tamper event occurs, the tamper bits (TB1 and/or TB2) will be immediately set if
TEB

= '1.'

X

If the tamper interrupt enable bit (TIE
The IRQ

/OUT output is cleared by a READ of the flags register (as seen in Figure 24 on

page 34), a reset of the TIE bit to '0,' or the RST

). If the selected switch mode is normally open (TCMX = '1'), the

X

) will be immediately set, allowing the user to determine

x

bit), through an internal pull-up/pull-down resistor as a

X

) is set to a '1,' the IRQ/OUT pin will also be activated.

X

(if the TPMX bit is set to '0') or to VCC

SS

OUT

output is asserted.

Note: In order to avoid an inadvertent activation of the IRQ

the flag register (0Fh) should be read prior to resetting the TEB

/OUT pin due to a prior tamper event,

bit.

X

The tamper bits are “read only” bits and are reset only by writing the tamper enable bit
(TEB

) to '0.' Thus, when servicing a tamper interrupt, the user should read the flags

X

register to clear the IRQ
TEB

to again enable the tamper circuit.

x

pin, then clear the TEBx bit to clear the TBx flag, followed by setting

The tamper detect function operates both under normal power, and in battery backup. Even
if the trigger event occurs during a power-down condition, the tamper flag bit(s) will be set
correctly.

2.8 Sampling

As the switch mode normally closed (TCMX= '0') requires a greater amount of current to
maintain constant monitoring, the M41ST87Y/W offers a programmable tamper detect
sampling bit (TDS

page 23). When enabled, the sampling frequency is once per second (1Hz), for a duration of

approximately 1 ms.

When TEB

is disabled, no current will be drawn by the tamper detection circuit. After a

X

tamper event has been detected, no additional current will be drawn.

Note: The oscillator must be running for tamper detection to operate in the sampling mode. If the

oscillator is stopped, the tamper detection circuit will revert to constant monitoring.

) to reduce the current drawn on VCC or V

X

(see Figure 17 on

BAT

Note: Sampling in the tamper high mode (TPM

connecting the TPx
monitoring when V

pin to VCC through an external resistor. This will allow constant

IN

is “on” and revert to sampling when in battery backup (see Figure 14

CC

= '1') may be bypassed while on VCC by

X

on page 20).

26/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Operating modes

2.9 Internal tamper pull-up/down current

Depending on the capacitive and resistive loading of the tamper pin input (TP
may require more or less current from the internal pull-up/down used when monitoring the
normally closed switch mode. The state of the tamper current hi/tamper current low bit
(TCHI/TCLO
1 MΩ pull-up/-down resistor, while TCHI/TCLO

) determines the sizing of the internal pull-up/-down. TCHI/TCLOX = '1' uses a

X

= '0' uses a 10 MΩ pull-up/-down resistor

X

(see Figure 18 on page 24).

2.10 Avoiding inadvertent tampers (normally closed configuration)

In some applications it may be necessary to use a low pass filter to reduce electrical noise
on the tamper input pin when the TCM
the tamper detect switch is located some distance (> 6”) from the tamper input pin. A low
pass filter can prevent unwanted, higher frequency noise from inadvertently being detected
as a tamper condition caused by the “antenna-effect” (produced by a longer signal wire or
mesh). This low pass filter can be constructed using a series resistor (R) in conjunction with
a capacitor (C) on the tamper input pin.

The cut-off frequency f

is determined according to the formula:

c

Figure 21. Low-pass filter implementation for noise immunity

bit = 0 (normally closed). This is especially true if

X

fc12PiRC⋅⋅⋅()⁄=

), the user

XIN

C

TP

AI11185

IN

To Tamper Detect Switch

Table 6. Calculated cut-off frequency for typical capacitance and resistance

R

values

R (Ω)C (F) fc1/fc (s)

1000 1.00E-09 15.9 MHz 6.28 µs

1000 1.00E-06 159.2 Hz 6.28 ms

5000 1.00E-09 31.8 kHz 31.4 µs

5000 1.00E-06 31.8 Hz 31.4 ms

10000 1.00E-09 15.9 kHz 62.8 µs

10000 1.00E-06 15.9 Hz 62.8 ms

Doc ID 9497 Rev 10 27/54

Operating modes M41ST87Y, M41ST87W

2.11 Tamper event time-stamp

Regardless of which tamper occurs first, not only will the appropriate tamper bit be set, but
the event will also be automatically time-stamped. This is accomplished by freezing the
normal update of the clock registers (00h through 07h) immediately following a tamper
event. Thus, when tampering occurs, the user may first read the time registers to determine
exactly when the tamper event occurred, then re-enable the clock update to the current time
(and reset the tamper bit, TB

The time update will then resume and the clock can be read to determine the current time.
Both tamper enable bits (TEB

In the event of multiple tampers, the time-stamp will reflect the initial tamper event.

) by resetting the tamper enable bit (TEBX).

X

) must always be set to '0' in order to read the current time.

X

Note: If the TEB

down time-stamp (see Section 3.0.1: Power-down time-stamp on page 29) and the HT bit
(halt update) will not be set during the power-down event. If both are needed, the power
down time-stamp may be accomplished by writing the time into the general purpose RAM
memory space when PFO

bit is set, the tamper event time-stamp will take precedence over the power

X

is asserted.

28/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Clock operation

3 Clock operation

The eight byte clock register (see Table 7 on page 30) is used to both set the clock and to
read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths
of seconds, seconds, minutes, and hours are contained within the first four registers.

Note: A WRITE to any clock register (addresses 0 to 7h) will result in the tenths/hundredths of

seconds being reset to “00.” Furthermore, the tenths/hundredths of seconds cannot be
written to any value other than “00.”

Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of
week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The
ninth clock register is the control register (this is described in the clock calibration section).
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. If the device is expected to spend a significant amount of time on the shelf,
the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator
restarts within one second (typical).

Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),

including the OFIE bit, CLRPW0 bit, CLRPW1 bit, THS bit, and so forth, will result in an
update of the system clock and a reset of the divider chain. This could result in a significant
corruption of the current time, especially if the HT bit (see Section 3.0.1: Power-down time-

stamp) has not been previously reset. These non-clock related bits should be written prior to

setting the clock, and remain unchanged until such time as a new clock time is also written.

The eight clock registers may be read one byte at a time, or in a sequential block. The
control register (address location 08h) may be accessed independently. The M41ST87 will
periodically copy the time/date counters to the user registers thus updating them. This
process is suspended when any of these 8 registers is being accessed. It is also suspended
during backup mode. Suspending the updates ensures that the clock data being read does
not change during the READ.

3.0.1 Power-down time-stamp

Upon power-down following a power failure, the halt update bit (HT) will automatically be set
to a '1.' This will prevent the clock from updating the user registers, and will allow the user to
read the time of the power-down event.

Note: When the HT bit is set or a tamper event occurs, the tenths/hundredths of a second register

(00h) will automatically be reset to a value of “00.” All other date and time registers (01h ­07h) will retain the value last updated prior to the power-down or tamper event. The internal
clock remains accurate and no time is lost as a result of the zeroing of the tenth/hundredths
of a second register. When updates are resumed (due to resetting the HT bit or TEB bit), the
correct time will be displayed.

Resetting the HT bit to a '0' will allow the clock to update the user registers with the current
time.

Note: If the TEB bit is set, the power down time-stamp will be disabled, and the tamper event time-

stamp will take precedence (see Section 2.7: Tamper detection operation on page 26).

Doc ID 9497 Rev 10 29/54

Clock operation M41ST87Y, M41ST87W

3.1 TIMEKEEPER® registers

The M41ST87Y/W offers 22 internal registers which contain clock, control, alarm, watchdog,
flag, square wave, and tamper data. The 8 clock registers are memory locations which
contain external (user accessible) and internal copies of the data (usually referred to as
BiPORT
except that they are updated periodically by the simultaneous transfer of the incremented
internal copy. The internal divider (or clock) chain will be reset upon the completion of a
WRITE to any clock address (00h to 07h).

The system-to-user transfer of clock data will be halted whenever the address being
accessed is a clock address (00h to 07h). The updates will resume either due to a stop
condition or when the pointer increments to a non-clock or RAM address.

TIMEKEEPER and alarm registers store data in BCD format. Control, watchdog and square
wave registers store data in binary format.

™

TIMEKEEPER cells). The external copies are independent of internal functions

Table 7. TIMEKEEPER

Addr

D7 D6 D5 D4 D3 D2 D1 D0

00h 0.1 seconds 0.01 seconds

01h ST 10 seconds Seconds Seconds 00-59
02h OFIE 10 minutes Minutes Minutes 00-59

03h CB1 CB0 10 hours Hours (24-hour format)

04h TR THS CLRPW1 CLRPW0 32kE Day of week Day 01-7
05h PFOD 0 10 date Date: day of month Date 01-31
06h 0 0 0 10M Month Month 01-12
07h 10 Years Year Year 00-99
08h OUT FT S Calibration Control
09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
0Ah AFE SQWE ABE Al 10M Alarm month Al month 01-12
0Bh RPT4 RPT5 AI 10 date Alarm date Al date 01-31
0Ch RPT3 HT AI 10 hour Alarm hour Al hour 00-23
0Dh RPT2 Alarm 10 minutes Alarm minutes Al min 00-59
0Eh RPT1 Alarm 10 seconds Alarm seconds Al sec 00-59
0Fh WDF AF 0 BL 0 OF TB1 TB2 Flags
10h 0 0 0 0 0 0 0 0 Reserved
11h 0 0 0 0 0 0 0 0 Reserved
12h 0 0 0 0 0 0 0 0 Reserved
13h RS3 RS2 RS1 RS0 SQWOD 0 0 0 SQW

14h TEB1 TIE1 TCM1 TPM1 TDS1

15h TEB2 TIE2 TCM2 TPM2 TDS2

16h-1Dh ROM

1Eh-1Fh Reserved 2-byte

20h-9Fh

®

register map

Data

TCHI/

TCLO

TCHI/

TCLO

Function/range

BCD format

10s/100s

seconds

Century/

Hours

CLR1

1

CLR2

2

CLR1 Tamper1

EXT

CLR2 Tamper2

EXT

Serial

number

128 user

bytes

00-99

0-1/

00-23

8-byte

30/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Clock operation

Keys:

0 = Must be set to zero RB0-RB1 = Watchdog resolution bits

32kE = 32 kHz output enable bit RPT1-RPT5 = Alarm repeat mode bits

ABE = Alarm in battery backup mode enable bit RS0-RS3 = SQW frequency

AF = Alarm flag (read only) S = Sign bit

AFE = Alarm flag enable bit SQWE = Square wave enable

BL = Battery low flag (read only) SQWOD = Square wave open drain bit

BMB0-BMB4 = Watchdog multiplier bits ST = Stop bit

CB0-CB1 = Century bits TB (1 and 2) = Tamper bits (read only)

CLR (1 and 2) = RAM clear bits TCHI/TCLO

CLR (1 and 2)

CLRPW0 = RAM clear pulse width 0 bit TDS (1 and 2) = Tamper detect sampling bits

CLRPW1 = RAM clear pulse width 1 bit TEB (1 and 2) = Tamper enable bits

FT = Frequency test bit THS = Threshold bit

HT = Halt update bit TIE (1 and 2) = Tamper interrupt enable bits

OF = Oscillator fail bit TPM (1 and 2) = Tamper polarity mode bits

= RAM clear external bits TCM (1 and 2) = Tamper connect mode bits

EXT

(1 and 2) = Tamper current hi/tamper current low bits

OFIE = Oscillator fail interrupt enable bit TR = t

OUT = Output level WDS = Watchdog steering bit

PFOD = Power-fail output open drain bit WDF = Watchdog flag (read only)

rec

bit

3.2 Calibrating the clock

The M41ST87Y/W is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested to not exceed ±35 ppm (parts per million) oscillator
frequency error at 25
month. Even better accuracy can be achieved with higher accuracy crystals. When the
calibration circuit is properly employed, accuracy can be improved to better than ±2 ppm at
25 °C.

The oscillation rate of crystals changes with temperature (see Figure 22 on page 33).
Therefore, the M41ST87Y/W design employs periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage,
as shown in Figure 23: Calibration waveform on page 33. The number of times pulses which
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.

The calibration bits occupy the five lower order bits (D4-D0) in the control register (08h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.

°

C, with ±20 ppm crystals, which translates to about ±1.53 minutes per

Doc ID 9497 Rev 10 31/54

Clock operation M41ST87Y, M41ST87W

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is
running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M41ST87Y/W may
require.

The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in application
note AN934, “TIMEKEEPER

®

calibration.” This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the calibration byte.

The second approach is better suited to a manufacturing environment, and involves the use
of the SQW/FT pin. The pin will toggle at 512 Hz, when the stop bit (ST) is '0,' the frequency
test bit (FT) is '1,' and SQWE is '0.'

Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.

If the SQWOD bit = '1,' the SQW/FT pin is an open drain output which requires a pull-up
resistor to V

for proper operation. A 500 to 10 kΩ resistor is recommended in order to

CC

control the rise time. The FT bit is cleared on power-down.

32/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Clock operation

Figure 22. Crystal accuracy across temperature

Frequency (ppm)

20

0

–20

–40

–60

2

= 25°C ± 5°C

T

O

2

80–10–20–30–40

AI07888

–80

–100

–120

–140

–160

= K x (T – TO)

F

= –0.036 ppm/°C2 ± 0.006 ppm/°C

K

0 10203040506070

Temperature °C

Figure 23. Calibration waveform

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

3.3 Setting alarm clock registers

Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go
off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every
year, month, day, hour, minute, or second. It can also be programmed to go off while the
M41ST87Y/W is in the battery back-up to serve as a system wake-up call.

Bits RPT5–RPT1 put the alarm in the repeat mode of operation. Table 8 on page 34 shows
the possible configurations. Codes not listed in the table default to the once per second
mode to quickly alert the user of an incorrect alarm setting.

AI00594B

When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5–RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the

Doc ID 9497 Rev 10 33/54

Clock operation M41ST87Y, M41ST87W

alarm condition activates the IRQ/OUT pin as shown in Figure 25 on page 35. To disable the
alarm, write '0' to the alarm date register and to RPT5–RPT1.

If the address pointer is allowed to increment to the flag register address, an alarm condition
will not cause the interrupt/flag to occur until the address pointer is moved to a different
address. It should also be noted that if the last address written is the “alarm seconds,” the
address pointer will increment to the flag address, causing this situation to occur. Thus the
user should not leave the address pointer at 0Fh if using the alarm interrupt function. This is
easily handled by simply reading past the flags registers before teminating a read sequence.

The IRQ

/OUT output is cleared by a READ to the flags register. A subsequent READ of the

flags register is necessary to see that the value of the alarm flag has been reset to '0.'

The IRQ

/OUT pin can also be activated in the battery backup mode. The IRQ/OUT will go
low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are
set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during
power-up will only set AF. The user can read the flag register at system boot-up to
determine if an alarm was generated while the M41ST87Y/W was in the deselect mode
during power-up. Figure 25 on page 35 illustrates the backup mode alarm timing.

Figure 24. Alarm interrupt reset waveform

ADDRESS POINTER

ACTIVE FLAG

IRQ/OUT

0Fh0Eh 10h

HIGH-Z

Table 8. Alarm repeat modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting

AI07086

11111Once per second

11110Once per minute

11100Once per hour

11000Once per day

10000Once per month

00000Once per year

34/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Clock operation

Figure 25. Backup mode alarm waveform

V

CC

V

PFD

V

SO

t

rec

ABE, AFE Bits in Interrupt Register

AF bit in Flags Register

IRQ/OUT

HIGH-Z

3.4 Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and
11=4 seconds. The amount of time-out is then determined to be the multiplication of the five­bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog
register = 3*1 or 3 seconds).

Note: The accuracy of the timer is within ± the selected resolution.

If the processor does not reset the timer within the specified period, the M41ST87Y/W sets
the WDF (watchdog flag) and generates either a watchdog interrupt or a microprocessor
reset.

The most significant bit of the watchdog register is the watchdog steering bit (WDS). When
set to a '0,' the watchdog will activate the IRQ
a '1,' the watchdog will output a negative pulse on the RST
register, FT, AFE, ABE and SQWE bits will reset to a '0' at the end of a watchdog time-out
when the WDS bit is set to a '1.'

/OUT pin when timed-out. When WDS is set to

pin for t

HIGH-Z

. The watchdog

rec

AI07087

The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high)
can be applied to the watchdog input pin (WDI) or 2) the microprocessor can perform a
WRITE of the watchdog register. The time-out period then starts over.

Note: The WDI pin should be tied to V

In order to perform a software reset of the watchdog timer, the original time-out period can
be written into the watchdog register, effectively restarting the count-down cycle.

if not used and is only available in the SOX28 package.

SS

Doc ID 9497 Rev 10 35/54

Clock operation M41ST87Y, M41ST87W

Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt,
either a transition of the WDI pin, or a value of 00h needs to be written to the watchdog
register in order to clear the IRQ

/OUT pin. This will also disable the watchdog function until
it is again programmed correctly. A READ of the flags register will reset the watchdog flag
(bit D7; register 0Fh) but does not clear the IRQ

/OUT pin.

The watchdog function is automatically disabled upon power-up and the watchdog register
is cleared.

3.5 Square wave output

The M41ST87Y/W offers the user a programmable square wave function which is output on
the SQW/FT pin. RS3-RS0 bits located in 13h establish the square wave output frequency.
These frequencies are listed in Tab le 9 . Once the selection of the SQW frequency has been
completed, the SQW/FT pin can be turned on and off under software control with the square
wave enable bit (SQWE) located in register 0Ah.

The SQW/FT output is programmable as an N-channel, open drain output driver, or a full­CMOS output driver. By setting the square wave open drain bit (SQWOD) to a '1,' the output
will be configured as an open drain (with I
SQWOD is set to '0,' the output will be configured as full-CMOS (sink and source current as
specified in Table 17 on page 44).

as specified in Table 17 on page 44). When

OL

Note: When configured as open drain (SQWOD = '1'), the SQW/FT pin requires an external pull-

up resistor.

Table 9. Square wave output frequency

Square wave bits Square wave

RS3 RS2 RS1 RS0 Frequency Units

0000None–

000132.768kHz

00108.192kHz

00114.096kHz

01002.048kHz

01011.024kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

36/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Clock operation

3.6 Full-time 32 kHz square wave output

The M41ST87Y/W offers the user a special 32 kHz square wave function which defaults to
output on the F
(ST bit = '0'). This function is available within one second (typ) of initial power-up and can
only be disabled by setting the 32 kE bit to '0' or the ST bit to '1.' If not used, the F
should be disconnected and allowed to float.

pin (pin 21) as long as VCC ≥ VSO, and the oscillator is running

32k

32k

pin

Note: The F

pin is an open drain which requires an external pull-up resistor.

32k

3.7 Power-on reset

The M41ST87Y/W continuously monitors VCC. When VCC falls to the power fail detect trip
point, the RST
V

(max). The RST pin is an open drain output and an appropriate pull-up resistor should

PFD

pulls low (open drain) and remains low on power-up for t

after VCC passes

rec

be chosen to control rise time.

Note: A power-on reset will result in resetting the following control bits to '0': OFIE, AFE, ABE,

SQWE, FT, WDS, BMB0-BMB4, RB0, RB1, TIE1, and TIE2 (see Table 13 on page 41).

3.8 Reset inputs (RSTIN1 & RSTIN2)

The M41ST87Y/W provides two independent inputs which can generate an output reset.
The function of these resets is identical to a reset generated by a power cycle. Tab l e 1 0 and

Figure 26 illustrate the AC reset characteristics of this function. Pulses shorter than t

t

will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to

R2

V

through a 100 kΩ resistor. Note that RSTIN1 triggers on the falling edge while RSTIN2

CC

triggers on the rising edge.

Note: RSTIN2

Figure 26. RSTIN1

is available only in the SOX28 package.

& RSTIN2 timing waveforms

R1

and

RSTIN1

RSTIN2

RST

t

R1

t

R2

Hi-Z

t

rec

Doc ID 9497 Rev 10 37/54

t

rec

Hi-Z

AI07072

Clock operation M41ST87Y, M41ST87W

Table 10. Reset AC characteristics

Symbol Parameter

(2)

t

R1

(2)

t

R2

(3)

t

rec

1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except

where noted).

2. Pulse widths of less than 100 ns will result in no RESET (for noise immunity).

3. Programmable (see Table 12 on page 40). Same function as power-on reset.

RSTIN1 low to RST low (min pulse width) 100 200 ns

RSTIN2 low to RSTIN2 high (min pulse width) 100 200 ns

RSTIN1 or RSTIN2 high to RST high 96 98

(1)

Min Max Unit

(3)

ms

3.9 Power-fail comparators (1 and 2)

Two power-fail inputs (PFI1 and PFI2) are compared to an internal reference voltage (1.25V).
If either PFI
output (PFO
detector to signal a failing power supply. Typically PFI
external voltage dividers (see Figure 5 on page 11) to either the unregulated DC input (if it is
available) or the regulated output of the V
such that the voltage at PFI
regulated V
operating voltage, thus providing an early warning of power failure.

or PFI2 is less than the power-fail threshold (V

1

or PFO2) will go low. This function is intended for use as an under-voltage

1

regulator. The voltage divider can be set up

or PFI2 falls below V

input to the M41ST87Y/W or the microprocessor drops below the minimum

CC

1

CC

and PFI2 are connected through

1

several milliseconds before the

PFI

), the associated power-fail

PFI

During battery back-up, the power-fail comparator turns off and PFO
remain) low. This occurs after V
PFO

are forced high, irrespective of V

2

from V

(max) until the inputs are recognized. At the end of this time, the power-fail

PFD

comparator is enabled and PFO
unused, PFI

or PFI2 should be connected to VSS and the associated PFO1 or PFO2 left

1

drops below V

CC

and PFO2 follow PFI1 and PFI2. If the comparator is

1

for the write protect time (t

PFI

unconnected.

3.10 Power-fail outputs

The PFO1 and PFO2 outputs are programmable as N-channel, open drain output drivers, or
full-CMOS output drivers. By setting the power-fail output open drain bit (PFOD) to a '1,' the
output will be configured as open drain (with I
PFOD is set to '0,' the outputs will be configured as full-CMOS (sink and source current as
specified in Table 17 on page 23).

Note: When configured as open drain (PFOD = '1'), PFO

up resistor.

as specified in Table 17 on page 44). When

OL

and PFO2 go (or

(min). When power returns, PFO1 and

PFD

and PFO2 will require an external pull-

1

1

), which is the time

rec

38/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Clock operation

3.11 Century bits

These two bits will increment in a binary fashion at the turn of the century, and handle leap
years correctly. Refer to Ta bl e 1 1 . These bits represent the next higher order bits of the
years register (07h), and should be set accordingly. For example, for the year 2100, they
would be set to 1 (D7 = 0 and D6 = 1), and for the year 2300, they would be set to 3 (D7 = 1
and D6 = 1). Once set, they will increment every 100 years. Provided they are set as
described above, the date register (05h) will properly manage leap day at the turn of any
century. Leap day does not occur in turn-of-century years except for those which are
multiples of 400. Thus, with CB1 and CB0 properly set, the device will omit leap day from
the appropriate turn-of-century years.

Table 11. Century bits examples

CB1 CB0 Leap year? Example

0 0 Yes 2000

0 1 No 2100

1 0 No 2200

1 1 No 2300

1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by

100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year
2100 is not).

(1)

3.12 Output driver pin

When the TIE bit, OFIE bit, AFE bit, and watchdog register are not set to generate an
interrupt, the IRQ

/OUT pin becomes an output driver that reflects the contents of D7 of the
control register. In other words, when D7 (OUT bit) is a '0,' then the IRQ
driven low. With the ABE bit set to '1,' the OUT pin will continue to be driven low in battery
backup.

Note: The IRQ

/OUT pin is an open drain which requires an external pull-up resistor.

3.13 Battery low warning

The M41ST87Y/W automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 0Fh, will be set if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain set until completion of battery replacement and
subsequent battery low monitoring tests, either during the next power-up sequence or the
next scheduled 24-hour interval.

If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct. A fresh battery should be
installed.

If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V
battery back-up mode, the battery should be replaced. The battery should be replaced while
V

is applied to the device.

CC

is supplied. In order to ensure data integrity during subsequent periods of

CC

/OUT pin will be

Doc ID 9497 Rev 10 39/54

Clock operation M41ST87Y, M41ST87W

The M41ST87Y/W only monitors the battery when a nominal VCC is applied to the device.
Thus applications which require extensive durations in the battery back-up mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.

3.14 t

rec

bit

Bit D7 of clock register 04h contains the t
of the deselect time after V

reaches V

CC

WRITEs may again be performed to the device after a power-down condition. The t
allow the user to set the length of this deselect time as defined by Tab le 1 2 .

Table 12. t

t

bit (TR) STOP bit (ST)

rec

1. Default setting.

definitions

rec

0 0 96 98

0140200ms

1 X 50 2000 µs

3.15 Electronic serial number

The M41ST87Y/W has a unique 8-byte lasered serial number with parity. This serial number
is “read only” and is generated such that no two devices will contain an identical number.

bit (TR). t

rec

. This allows for a voltage settling time before

PFD

refers to the automatic continuation

rec

t

time

rec

Min Max

(1)

rec

bit will

Units

ms

3.16 Oscillator stop detection

If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time, and can be used to judge the validity of the
clock and date data. This bit will be set to '1' any time the oscillator stops. The following
conditions can cause the OF bit to be set:

● The first time power is applied (defaults to a '1' on power-up).

● The voltage present on V

● The ST bit is set to '1.'

If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ
asserted. The IRQ
to '0,' or if the RST

/OUT output is cleared by resetting the OF bit to '0,' resetting the OFIE bit

output is asserted (but is NOT cleared by reading the flag register).

The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF bit to '0.' This function operates
both under normal power and in battery backup. If the trigger event occurs during a power­down condition, this bit will be set correctly.

Note: The ABE bit must be set to '1' for the IRQ

40/54 Doc ID 9497 Rev 10

or battery is insufficient to support oscillation.

CC

/OUT pin to be activated in battery backup.

/OUT pin will also be

M41ST87Y, M41ST87W Clock operation

3.17 Initial power-on defaults

Table 13. Default values

Condition TR ST OF OFIE HT

Initial power-up 0 0 1 0 1 1 0 0

Subsequent power-up (with
battery backup)

(2)(3)

UC UC UC 0 ⇑ 1 ⇓ UC 0 ⇓ 0 ⇑

(1)

Out FT AFE

Condition ABE SQWE SQWOD PFOD Watchdog register

Initial power-up 0 0 1 1 0

Subsequent power-up (with
battery backup)

(2)(3)

0 ⇑ 0 ⇑ UC UC 0 ⇓

Condition 32kE THS TEB1 and 2 TCM1 and 2 TPM1 and 2 TDS1 and 2

Initial power-up 1

Subsequent power-up (with
battery backup)

(2)

Condition

(5)

00 0 0 0

UC UC UC UC UC UC

TCHI/TCLO1

and 2

CLR1
and 2

TIE1 and 2 CLRPW0 CLRPW1

CLR1

CLR2

Initial power-up 0 0 0 0 0 0

Subsequent power-up (with
battery backup)

1. When TEBX is set to '1,' the HT bit will not be set on power-down (tamper time-stamp will have precedence).

2. UC = unchanged.

3. ⇑ = V

4. WDS, BMB0-BMB4, RB0, RB1.

5. 32 kHz output valid only on V

CC

(2)

rising; ⇓ = VCC falling.

UC UC 0 ⇑ UC UC UC

.

CC

(4)

and

EXT

EXT

Note: All other control bits are undetermined.

Doc ID 9497 Rev 10 41/54

Maximum ratings M41ST87Y, M41ST87W

4 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 14. Absolute maximum ratings

Symbol Parameter Value Unit

T

STG

T

SLD

V

IO

V

CC

I

O

P

D

θ

JA

1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.

2. Reflow at peak temperature of 240 °C. The time above 235°C must not exceed 20 seconds.

Storage temperature (VCC off, oscillator off) –55 to 125 °C

(1)

(2)

°C

°C

Lead solder temperature for 10 seconds

SSOP20 260

SOX28 240

Input or output voltage –0.3 to VCC+0.3 V

Supply voltage

M41ST87Y –0.3 to 7.0 V

M41ST87W –0.3 to 4.6 V

Output current 20 mA

Power dissipation 1 W

Thermal resistance, junction to ambient

SSOP20 83.0 °C/W

SOX28 °C/W

Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup

mode.

42/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W DC and AC parameters

5 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.

Table 15. DC and AC measurement conditions

Parameter M41ST87Y M41ST87W

VCC supply voltage 4.5 to 5.5 V 2.7 to 3.6 V

Ambient operating temperature –40 to 85 °C –40 to 85 °C

Load capacitance (C

Input rise and fall times ≤ 50 ns ≤ 50 ns

Input pulse voltages 0.2 to 0.8V

Input and output timing ref. voltages 0.3 to 0.7V

Note: Output high Z is defined as the point where data is no longer driven.

) 100 pF 50 pF

L

0.2 to 0.8V

CC

0.3 to 0.7V

CC

CC

CC

Figure 27. AC testing input/output waveforms

0.8V

0.2V

CC

CC

0.7V

0.3V

AI02568

CC

CC

Table 16. Capacitance

Symbol Parameter

C

C

OUT

t

LP

1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.

2. At 25 °C, f = 1 MHz.

3. Outputs are deselected.

Input capacitance 7 pF

IN

(3)

Output capacitance 10 pF

Low-pass filter input time constant (SDA and SCL) 50 ns

(1)(2)

Min Max Unit

Doc ID 9497 Rev 10 43/54

DC and AC parameters M41ST87Y, M41ST87W

Table 17. DC characteristics

Sym Parameter Test condition

Battery current

I

BAT

OSC ON

(2)

Battery current

= 25 °C, VCC = 0 V,

T

A

= 3 V

V

BAT

OSC OFF

I

Supply current f = 400 kHz 1.4 0.75 mA

CC1

I

CC2

I

LI

(3)

Supply current
(standby)

Input leakage
current

Input leakage

SCL, SDA ≥

0V ≤ V

IN

V

≤ V

current (PFI)

I

LO

I

OUT1

I

OUT2

V

V

(4)

current

V

OUT

current

(5)

(active)

V

current

OUT

(battery backup)

Input high

V

IH

voltage

V

Input low voltage –0.3 0.3V

IL

Battery voltage 2.5 3.0 V

BAT

Output high

(6)

OH

voltage

V

V

OUT2

0V ≤ V

OUT1

I

≤ V

IN

> VCC – 0.3 V 175 100 mA

> V

BAT

= –1.0 mA 2.4 2.4 V

OH

Output leakage

Pull-up supply
voltage

/OUT, RST, F

IRQ

(open drain)

(1)

M41ST87Y M41ST87W

Unit

Min Typ Max Min Typ Max

500 700 500 700 nA

50 50 nA

– 0.3 V 1 0.50 mA

CC

CC

±1 ±1 µA

–25 2 25 –25 2 25 nA

CC

±1 ±1 µA

– 0.3 V 100 100 µA

32k

0.7V

CC

VCC + 0.3 0.7V

CC

CC

CC

–0.3 0.3V

2.5 3.0 V

5.5 3.6 V

VCC + 0.3 V

CC

CC

V

V

V

OHB

V

V

V

V

(7)

OL

PFD

PFI1,

PFI2

backup)

Output low
voltage

Output low
voltage

(open drain)

Power fail
deselect

PFI input
threshold

(9)

= –1.0 µA

I

OUT2

= 3.0 mA 0.4 0.4 V

I

OL

IOL = 10 mA 0.4 0.4 V

THS bit = 0 4.20 4.35 4.50 2.55 2.62 2.70 V

THS bit = 1 4.50 4.60 4.75 2.80 2.88 3.00 V

= 5 V (Y) 1.225 1.250 1.275 V

V

CC

= 3 V (W) 1.225 1.250 1.275 V

V

CC

(8)

2.9 2.9 V

VOH (battery

PFI hysteresis PFI rising 20 70 20 70 mV

44/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W DC and AC parameters

Table 17. DC characteristics (continued)

Battery backup

V

SO

switchover

External switch

R

resistance on

SW

tamper pin

1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).

2. Measured with V

3. RSTIN1

4. Outputs deselected.

5. External SRAM must match RTC supervisor chip V

6. For PFO

7. Conditioned output (E

8. TP

9. For IRQ

and RSTIN2 internally pulled-up to VCC through 100 kΩ resistor. WDI internally pulled-down to VSS through

100 kΩ resistor.

and PFO2 (if PFOD = '0'), SQW/FT (if SQWOD = '0'), and TP

1

will reduce battery life.

output can source –300 µA (typ) for V

CLR

/OUT, SQW/FT (if SQWOD = '1'), PFO1 and PFO2 (if PFOD = '1'), RST, SDA, and F

OUT

and E

CON

open. Not including tamper detection current (see Table 4 on page 23).

CON

specification.

CC

) can only sustain CMOS leakage current in the battery backup mode. Higher leakage currents

= 2.9 V.

BAT

2.5 2.5 V

500 500 Ω

pins (CMOS).

CLR

pins (open drain).

32k

Table 18. Crystal

Symbol Parameter

f

O

R

S

C

L

1. User supplied for the 20-lead SSOP package. STMicroelectronics recommends the KDS DT-38 (3 x 8 mm) for thru-hole, or
the KDS DMX-26S (3.2 x 8 mm) for surface-mount, tuning fork-type quartz crystals. For contact information, see Section 8:

References on page 52.

2. Load capacitors are integrated within the M41ST87. Circuit board layout considerations for the 32.768 kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.

= –40 to 85 °C (guaranteed by design).

3. T

A

(1)

electrical characteristics

(2)

Min Typ Max Units

Resonant frequency 32.768 kHz

Series resistance 65

(3)

kΩ

Load capacitance 12.5 pF

Doc ID 9497 Rev 10 45/54

DC and AC parameters M41ST87Y, M41ST87W

Figure 28. Power down/up mode AC waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

VSO

1. E

t

F

t

PD

PFO

VALID

INPUTS

RST

OUTPUTS

(1)

E

CON

available in the SOX28 package only.

CON

VALID VALID

(PER CONTROL INPUT)

t

FB

DON'T CARE

HIGH-Z

t

RB

t

R

(PER CONTROL INPUT)

t

rec

VALID

RECOGNIZEDRECOGNIZED

AI07085

Table 19. Power down/up AC characteristics

Symbol Parameter

(2)

t

F

t

FB

t

PD

t

PFD

t

R

t

RB

t

rec

1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).

2. V

PFD

200 µs after V

3. V

PFD

4. Programmable (see Table 12 on page 40)

V

(3)

(max) to V

PFD

V

(min) to VSS VCC fall time 10 µs

PFD

(min) VCC fall time 300 µs

PFD

EX at VIH before power down 0 µs

PFI to PFO propagation delay 15 25 µs

V

(min) to V

PFD

VSS to V

PFD

(max) VCC rise time 10 µs

PFD

(min) VCC rise time 1 µs

Power-up deselect time 96 98

(max) to V

(min) to VSS fall time of less than tFB may cause corruption of RAM data.

(min) fall time of less than tF may result in deselection/write protection not occurring until

PFD

passes V

CC

PFD

(min).

(1)

Min Typ Max Unit

(4)

ms

46/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Package mechanical data

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Figure 29. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal outline

14

15

B

SO-E

Note: Drawing is not to scale.

Table 20. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal

mechanical data

D

1

E

H

28

AA2

e

A1

ddd

h x 45

LA1

°

C

millimeters inches

Symbol

Typ Min Max Typ Min Max

A 2.44 2.69 0.096 0.106

A1 0.15 0.31 0.006 0.012

A2 2.29 2.39 0.090 0.094

B 0.41 0.51 0.016 0.020

C 0.20 0.31 0.008 0.012

D 17.91 18.01 0.705 0.709

ddd 0.10 0.004

E 7.57 7.67 0.298 0.302

e1.27– –0.050– –

H 10.16 10.52 0.400 0.414

L 0.51 0.81 0.020 0.032

a 0°8° 0°8°

N28 28

Doc ID 9497 Rev 10 47/54

Package mechanical data M41ST87Y, M41ST87W

Figure 30. SSOP20 – 20-lead, shrink, small outline package outline

0061436_C

Table 21. SSOP20 – 20-lead, shrink, small outline package mechanical data

mm in

Sym

Min Typ Max Min Typ Max

A 2.000 0.079

A1 0.050 0.002

A2 1.650 1.750 1.850 0.065 0.069 0.073

b 0.220 0.380 0.009 0.015

c 0.090 0.250 0.004 0.010

D 6.900 7.200 7.500 0.272 0.283 0.295

E 7.400 7.800 8.200 0.291 0.307 0.323

E1 5.000 5.300 5.600 0.197 0.209 0.220

e 0.650 0.026

L 0.550 0.750 0.950 0.022 0.030 0.037

L1 1.250 0.049

k0d 4d 8d0d4d8d

ddd 0.100 0.004

48/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Package mechanical data

Figure 31. Carrier tape for SOX28 package

P

D

T

A

TOP COVER

TAPE

K

0

0

CENTER LINES
OF CAVITY

P

2

B

0

0

P

1

E

F

W

USER DIRECTION OF FEED

Table 22. Carrier tape dimensions for SOX28 package

Package W D E P

1.50

+0.10/

–0.00

1.75

±0.10

4.00

±0.10

SOX28

24.00
±0.30

P

0

2.00

±0.10

FA0B

2

11.50
±0.10

12.70
±0.10

Figure 32. Carrier tape for SSOP20 package

0

18.20
±0.10

K

0

3.20

±0.10

P

1

16.00
±0.10

AM03073v1

TUnit

0.30

±0.05

mm 1000

Bulk

Qty

Note: All dimensions in millimeters.

Doc ID 9497 Rev 10 49/54

Package mechanical data M41ST87Y, M41ST87W

Figure 33. Reel schematic

T

40mm min.

Access hole

At slot location

B

D

C

A

Tape slot

Full ra dius

In core for

Tape s tart

2.5mm min.width

N

G measured

At hub

AM04928v1

Table 23. Reel dimensions for 24 mm carrier tape (SOX28 package) and 16 mm carrier tape

(SSOP20 package)

Carrier tape

24 mm (SOX28)

16 mm (SSOP20)

A

(max)

330 mm

(13-inch)

330 mm

(13-inch)

B

(min)

1.5 mm

1.5 mm

C

13 mm

± 0.2 mm

13 mm

± 0.2 mm

D

(min)

N

(min)

20.2 mm 60 mm

20.2 mm 60 mm

G

24.4 mm

+ 2/–0 mm

16.4 mm

+ 2/–0 mm

T

(max)

30.4 mm

22.4 mm

Note: The dimensions given in Tab le 2 3 incorporate tolerances that cover all variations on critical

parameters.

50/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Part numbering

7 Part numbering

Table 24. Ordering information scheme

Example: M41ST 87Y MX 6 TR

Device type

M41ST

Supply voltage and write protect voltage

(1)

= VCC = 4.75 to 5.5 V

87Y

THS bit = '1': 4.50 V ≤ V

VCC = 4.5 to 5.5 V

THS bit = '0': 4.20 V ≤ V

87W = VCC = 3.0 to 3.6 V;

THS bit = '1': 2.80 V ≤ V

VCC = 2.7 to 3.6 V;

THS bit = '0': 2.55 V ≤ V

PFD

PFD

PFD

PFD

≤ 4.75 V

≤ 4.50 V

≤ 3.00 V

≤ 2.70 V

Package

(2)(3)

MX

SS

= SOX28

(4)

= SSOP20

Temperature range

6 = –40 to 85 °C

Shipping method

For SOX28:

Blank = ECOPACK

®

package, tubes (Not for new design - use TR)

(1)

TR = ECOPACK® package, tape & reel

For SSOP20:

®

F = ECOPACK

1. Not recommended for new design. Contact ST sales office for availability.

2. The SOX28 package includes an embedded 32,768 Hz crystal.

3. Lead-free second level interconnect and RoHS compliant (by exemption).

4. Available in 3.3 V (W) version only.

package, tape & reel

For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.

Doc ID 9497 Rev 10 51/54

References M41ST87Y, M41ST87W

8 References

KDS, the crystal component supplier mentioned in this document, can be contacted at
[e-mail] or http://www.kds.info/index_en.htm

52/54 Doc ID 9497 Rev 10

M41ST87Y, M41ST87W Revision history

9 Revision history

Table 25. Document revision history

Date Revision Changes

May-2002 1 First issue.

23-Apr-2003 2 Document promoted to preliminary data.

10-Jul-2003 2.1 Update tamper information ( Figure 4, 5, 14, 15, 16; Tab le 1 7 , 4, 12).

11-Sep-2003 2.2

15-Jun-2004 3

7-Sep-2004 4 Update maximum ratings (Ta bl e 1 4 ).

29-Jun-2005 5

28-Mar-2006 6 Update to “Avoiding inadvertent tamper paragraph“ paragraph.

10-Sep-2008 7

31-Mar-2010 8

25-Jan-2011 9

03-Oct-2011 10

Update electrical, charge pump, and clock information (Ta bl e 1 7; Figure 5,

19, 20).

Reformatted; added lead-free information; updated characteristics
(Figure 2; Ta bl e 1 , 14, 17, 24).

Clarify NC connections, add inadvertent tamper, update MX attribute
(Figure 2, 21; Ta bl e 1 , 6, 24).

Reformatted document and title change; updated cover page, Figure 4,

15, 20, Section 6: Package mechanical data.

Added SSOP 20-pin package (updated cover page, Section 1.1, Figure 1,

4, 5, 13, 28, Ta bl e 1 , 2, Section 3.4, Section 3.8, added Figure 3, 30,
Ta bl e 1 8, 21
Figure 15.16, 19, 24, 27, 28, text in Section 1, Section 2, Section 2.1,
Section 2.1.5, Section 2.4, Section 2.5, Section 2.6.1, Section 2.6.3,
Section 2.6.5, Section 2.6.6, Section 2.6.8, Section 2.6.9, Section 2.7,
Section 2.8, Section 3, Section 3.0.1, Section 3.1, Section 3.2,
Section 3.3, Section 3.4, Section 3.8, Section 3.9, Section 3.11,
Section 3.13, Section 3.16, Section 3.17, Section 6; reformatted

document.

5.0 V version of device (M41ST87Y) is not recommended for new design
(updated cover page, Ta bl e 2 4 ); added tape and reel specifications
(Figure 31, 32, 33, Ta bl e 2 2, 23).

Updated Table 24: Ordering information scheme
in tubes is not recommended for new design.

, Section 8); updated Ta bl e 1 1 , 14, 17, 18, 24, Figure 10, 11,

as the shipping method

Doc ID 9497 Rev 10 53/54

M41ST87Y, M41ST87W

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54/54 Doc ID 9497 Rev 10