5.0 or 3.0V, 512 bit (64 x 8) SERIAL RTC
with SUPERVISORY FUNCTIONS
FEATURES SUMMARY
■ 5.0 OR 3.0V OPERATING VO LTA G E
■ SERIAL INTERFACE SU PPO R TS I
(400 KHz)
■ OPTIMIZED FOR MINIMAL INTERCONNECT
TO MCU
■ 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
■ AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
■ CHOICE OF POWER-FAIL DESELECT
VOLTAGES:
– M41ST84Y : V
4.20V ≤ V
– M41ST84W: V
2.55V ≤ V
■ 1.25V REFERENCE (for PFI/PFO)
■ COUNTERS FOR TENTHS/HUNDREDTHS
PFD
PFD
= 4.5 to 5.5V;
CC
≤ 4.50V
= 2.7 to 3.6V;
CC
≤ 2.70V
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE , MONTH, YEAR, and
CENTURY
■ 44 BYTES OF GENERAL PURPOSE RAM
■ PROGRAMMABLE ALARM and INTE RRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
■ WATCHDOG T IME R
■ MICROPROCESSOR POWER-ON RESET
■ BATTERY LOW FLAG
■ ULTRA-LOW BATT ERY SU PPL Y C URRE N T
OF 500 nA (m ax)
■ OPTIONAL PACKAGING INCLUDES A 28-
LEAD SOIC and SNAPHAT
®
ordered separately)
■ SNAPHAT PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP,
WHICH CONTAINS THE BATTERY and
CRYSTAL
2
C BUS
TOP (to be
M41ST84Y
M41ST84W
Figure 1. 16-pi n S O I C Package
16
1
SO16 (MQ)
Figure 2. 28-pi n S O I C Package*
SNAPHAT (SH)
Battery & Crystal
28
1
SOH28 (MH)
* Contact Local Sales Office
Rev. 4.0
1/31June 2003
M41ST84Y, M41ST84W
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. 16-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. 28-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. AC Testing Input/Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Crystal Electrical Characteristics (Externally Supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Serial Bus Data Transfer Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Acknowledgement Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11. Bus Timing Requirements Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
Figure 13. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Alternate READ Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15. WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
2/31
M41ST84Y, M41ST84W
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 10. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18. Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square Wave Outp ut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Input (RSTIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. RSTIN Timing Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
t
Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REC
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Table 13. t
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REC
Table 14. Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. Crystal Accuracy Across Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
M41ST84Y, M41ST84W
SUMMARY DESCRIPTION
The M4 1S T84 Y/W Seria l supervi s o r y TIMEKEE P-
®
SRAM is a low power 512-bit static CMOS
ER
SRAM organized as 64 words by 8 bi ts. A built-in
32.768 kHz oscilla tor (external crystal controlled)
and 8 bytes of the SRAM (see Table 9, page 16)
are used for the c lock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Sq uare Wave functions. Addresses and data are transferred serially
via a two line, bi-directional I2C interface. The
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41ST84Y/W has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power
failure occurs. The energy needed to s ustain the
SRAM and clock operations can be supplied by a
small lithium button-cell supply when a power failure occurs. Functions available to the user include
a non-volatile, time-of-day clock/calendar, Alarm
interrupts, Watchdog Timer and programmable
Square Wave output. Other features include a
Power-On Reset as well as an additional input
(RSTIN
(RST
the century, year, month, dat e, day , hour, minute,
second and tenths/hun dredths of a second in 24
) which can also generate an output Reset
). The eight clock address locations contain
hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
made aut omatically.
The M41ST84Y/W is supplied in a 28-lead SOIC
SNAPHAT
®
package (which integrates b oth crystal and battery in a single SNAP HA T top) or a 16pin SOIC. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing containing the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the S OIC pack age after t he
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device surface-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The 28-pin SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 2 8-lead SOIC, t he ba ttery/crystal package (e.g., SNAPHAT) part number is “M4TXX-BR12SH” (see Table 20, page 29).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
Figure 3. Logic Diagram
V
V
CC
(1)
XI
(1)
XO
SCL
SDA
RSTIN
WDI
PFI
Note: 1. For SO16 package only.
M41ST84Y
M41ST84W
V
SS
BAT
(1)
RST
IRQ/FT/OUT
SQW
PFO
AI03677
Table 1. Signal Names
(1)
XI
(1)
XO
IRQ
/FT/OUT
PFI Power Fail Input
PFO
RST
RSTIN
SCL Serial Clock Input
SDA Serial Data Input/Output
SQW Square Wave Output
WDI Watchdog Input
V
CC
(1)
V
BAT
V
SS
Note: 1. For SO16 package only.
Oscillator Input
Oscillator Output
Interrupt/Frequency Test/Out
Output (Open Drain)
Power Fail Output
Reset Output (Open Drain)
Reset Input
Supply Voltage
Battery Supply Voltage
Ground
4/31
M41ST84Y, M41ST84W
Figure 4. 16-pi n S O I C Co nnections Figure 5. 28-pi n S O I C C onnections
1
XI V
XO
RST
WDI
RSTIN
PFO
V
BAT
V
SS
2
3
4
M41ST84Y
M41ST84W
5
6
7
8
Figure 6. Block Diagram
SDA
SCL
Crystal
16
15
14
13
12
11
10
9
AI03678
I2C
INTERFACE
32KHz
OSCILLA T OR
CC
NC
IRQ/FT/OUT
NC
PFI
SQW
SCL
SDA
SQW V
NC
NC
NC
NC
NC
NC
WDI
RSTIN
NC
NC
1
2
3
4
5
6
7
M41ST84Y
M41ST84W
8
9
10
11
12
PFO
V
SS
REAL TIME CLOCK
CALENDAR
44 BYTES
USER RAM
RTC w/ALARM
& CALIBRATION
WATCHDOG
SQUARE W AVE
13
14
AF
WDF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI03679
CC
NC
IRQ/FT/OUT
NC
NC
NC
PFI
NC
SCL
NC
RST
NCNC
SDA
NC
IRQ/FT/OUT
SQW
(1)
WDI
V
CC
V
BA T
RSTIN
PFI
1.25V
(Internal)
Note: 1. Open dra i n out put
VBL= 2.5V
V
SO
V
PFD
COMPARE
= 2.5V
= 4.4V
COMPARE
COMPARE
(2.65V for ST84W)
COMP ARE
POR
BL
POWER
(1)
RST
PFO
AI03931
5/31
M41ST84Y, M41ST84W
Figure 7. Hardware Hookup
Unregulated
Voltage
R1
R2
Regulator
V
IN
V
CC
From MCU
MAXIMUM RATIN G
Stressing the device ab ove the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the dev ice at
these or any other conditions above those indicated in the Operating sections of this specification is
M41ST84Y/W
V
SCL
WDI
RSTIN
PFI
V
CC
SS
IRQ/FT/OUT
SDA
RST
SQW
PFO
To INT
To RST
To LED Display
To NMI
AI03680
not implied. Exposure to Absol ute Maxim um Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
®
T
STG
Storage Temperature (VCC Off, Oscillator Off)
SNAPHAT
SOIC –55 to 125 °C
(1)
T
SLD
V
IO
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages
M41ST84Y –0.3 to 7.0 V
V
CC
I
O
P
D
Note: 1. Reflow at peak temperature of 215°C to 225° C f or < 60 seconds (total thermal budg et not to exce ed 180°C for between 90 to 120
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave sol der SOIC to av oi d damaging S NAPHAT sockets.
Supply Voltage
M41ST84W –0.3 to 4.6 V
Output Current 20 mA
Power Dissipation 1 W
secon ds).
6/31
–40 to 85 °C
–0.3 to V
CC
+ 0.3
V
M41ST84Y, M41ST84W
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-
Table 3. DC and AC Measurement Conditions
Parameter M41ST84Y M41ST84W
V
Supply Voltage
CC
Ambient Operating Temperature –40 to 85°C –40 to 85°C
Load Capacitance (C
)
L
Input Rise and Fall Times ≤ 50ns ≤ 50ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defi ned as the point where data i s no longer dri ven.
Figure 8. AC Testing Input/Output Waveforms
ment Conditions listed in the rel evant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
4.5 to 5.5V 2.7 to 3.6V
100pF 50pF
0.2 to 0.8V
0.3 to 0.7V
CC
CC
0.2 to 0.8V
0.3 to 0.7V
CC
CC
0.8V
CC
0.2V
CC
Note: 50pF f or M41ST84 W.
0.7V
0.3V
AI02568
CC
CC
Table 4. Capacitance
Symbol
C
IN
C
IO
t
LP
Note: 1. Effectiv e capacitan ce measured wi th power su pply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected .
Input Capacitance 7 pF
(3)
Input / Output Capacitance 10 pF
Low-pass filter input time constant (SDA and SCL) 50 ns
Parameter
(1,2)
Min Max Unit
7/31
M41ST84Y, M41ST84W
Table 5. DC Characteristics
Sym Parameter
Battery Current OSC
ON
I
BAT
Battery Current OSC
OFF
I
Supply Current f = 400kHz 1.4 0.75 mA
CC1
Supply Current
I
CC2
(Standby)
Input Leakage Current
(2)
I
LI
Input Leakage Current
Test
Condition
= 25°C,
T
A
VCC = 0V,
V
= 3V
BAT
SCL, SDA =
– 0.3V
V
CC
0V ≤ V
IN
≤ V
(1)
CC
(PFI)
Output Leakage
(3)
I
LO
Current
V
Input High Voltage
IH
V
Input Low Voltage –0.3
IL
V
Battery Voltage 2.5 3.0
BAT
V
OH
Output High Voltage
Output Low Voltage
V
OL
Output Low Voltage
(Open Drain)
V
Power Fail Deselect 4 .20 4.40 4.50 2 .55 2.60 2.70 V
PFD
PFI Input Threshold
V
PFI
(5)
(4)
0V ≤ V
IOH = –1.0mA
I
IOL = 10mA
V
VCC = 3V(V)
OUT
= 3.0mA
OL
= 5V(Y)
CC
≤ V
CC
0.7V
PFI Hysteresis PFI Rising 20 70 20 70 mV
Battery Back-up
V
SO
Switchover
Note: 1. Valid for Ambient Operating Temperature : TA = –40 to 85°C ; VCC = 2.7 to 3.6V or 4. 5 to 5.5V (except where noted).
2. RSTI N
3. Outputs deselected .
4. For PFO
5. For IRQ
6. For rechargeable back-up, V
internally pulled-up to VCC through 100KΩ resist or. WDI internally pulled- down to VSS through 100K Ω resistor.
and SQW pins (CMOS) .
/FT/OUT, RST pins (Ope n Drai n): i f pu ll ed- up to supp ly oth e r tha n VCC, this su ppl y mu st be equ al to, or l es s t han 3. 0V when
V
= 0V (durin g battery back-up mode).
CC
(max) may be considered VCC.
BAT
M41ST84Y M41ST84W
Min Typ Max Min Typ Max
400 500 400 500 nA
50 50 nA
1 0.50 mA
±1 ±1 µA
–25 2 25 –25 2 25 nA
±1 ±1 µA
CC
VCC + 0.3 0.7V
0.3V
3.5
(6)
CC
–0.3
2.5 3.0
CC
VCC + 0.3
0.3V
3.5
2.4 2.4 V
0.4 0.4 V
0.4 0.4 V
1.225 1.250 1.275 1.225 1.250 1.275 V
2.5 2.5 V
(6)
CC
Unit
V
V
V
Table 6. Crystal Electrical Characteristics (Externally Supplied)
Symbol
f
0
R
S
C
L
Note: 1. Load capacitors are integrated within the M41ST84Y/W. Circuit board layout considerations for the 32.768 kHz crystal of minimum
trace lengths and isolat i on from RF generating signals should be ta ken into account.
2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:
1TJS125 F H2A212, (SMD) quartz cry st al for indust ri al temperatur e operations. KDS can be contacted at k ouhou@kdsj .co.jp or http://www.kdsj.co.jp for further information on this crystal type.
Resonant Frequency 32.768 kHz
Series Resistance 50 kΩ
Load Capacitance 12.5 pF
Parameter
(1,2)
8/31
Typ Min Max Unit
OPERATING MODES
The M41ST84Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the
correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wav e Regi ster
21 - 64. User RAM
The M41ST84Y/W clock continually monitors V
CC
for an out-of tolerance condition. Should VCC fall
below V
, the device terminates an access in
PFD
progress and resets t he device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous dat a f rom bei ng wri tten
to the device from a an out-of-tolerance system.
When V
falls below VSO, the device a utomati-
CC
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve bat tery life. As system p ower returns an d
V
rises above VSO, the battery is disconnected,
CC
and the power supply is switched to external V
Write protection continues until V
V
PFD
(min) plus t
REC
(min).
CC
CC
reaches
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data trans fer, the dat a line mus t remain
stable whenever the clock line is High.
M41ST84Y, M41ST84W
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A c hange in the st ate of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The devices that are controlled by the master are cal led
“slaves”.
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
.
ed clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transm itter by not
generating an acknowledge on t he last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
9/31
M41ST84Y, M41ST84W
Figure 9. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
DATA ALLOWED
Figure 10. Acknowledgement Sequence
START
SCLK FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
12 89
MSB LSB
DATA OUTPUT
BY RECEIVER
Figure 11. Bus Timing Requirements Sequence
SDA
tHD:STAtBUF
tR
SCL
SP
tF
tHIGH
tLOW
CHANGE OF
tSU:DAT
tHD:DAT
STOP
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGEMENT
tHD:STA
SR
AI00587
AI00601
tSU:STOtSU:STA
P
10/31
AI00589
Table 7. AC Characteristics
Symbol
f
SCL
t
BUF
t
HD:DAT
t
HD:STA
t
F
SCL Clock Frequency 0 400 kHz
Time the bus must be free before a new transmission can start 1.3 µs
SDA and SCL Fall Time 300 ns
(2)
Data Hold Time 0 µs
START Condition Hold Time
(after this period the first clock pulse is generated)
Parameter
(1)
M41ST84Y, M41ST84W
Min Max Unit
600 ns
t
HIGH
t
LOW
t
R
t
SU:DAT
t
SU:STA
t
SU:STO
Note: 1. Valid for Ambient Operating Temperature : TA = –40 to 85°C ; VCC = 2.7 to 3.6V or 4. 5 to 5.5V (except where noted).
2. Transmi tter must internally provide a hold time to bridge the undefined region (300ns m ax) of the fallin g edge of SCL.
Clock High Period 600 ns
Clock Low Period 1.3 µs
SDA and SCL Rise Time 300 ns
Data Setup Time 100 ns
START Condition Setup Time
(only relevant for a repeated start condition)
600 ns
STOP Condition Setup Time 600 ns
11/31
M41ST84Y, M41ST84W
READ Mode
In this mode the master reads th e M41ST84Y/W
slave after setting the slave address (see Figure
12, page 12). Following the WRITE Mode Cont rol
Bit (R/W
address ‘An’ is written to the on-chip address
pointer. Next the START condition and slave address are repeated followed by the READ Mode
Control Bit (R/W
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an A cknowledge Bit to
the slave transmitter. The address poi nter is only
incremented on reception of an Acknowledge
Clock. The M41ST84Y/W slave transmitter will
now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges
the new byte and the address pointer is
incremented to “An+2.”
Figure 12. Slave Address Location
=0) and the Acknowledge Bit, the word
=1). At this point the master trans-
This cycle of reading con secutive addresses will
continue until the mast er receiver sends a STOP
condition to the slave transmitter (see F igure 13,
page 12).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resum e either due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41ST84Y/W
slave without first writing to the (volatil e) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure 14, page 13).
R/W
START A
Figure 13. READ Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
START
S
ADDRESS
SLAVE
R/W
ACK
DATA n+X
SLAVE ADDRESS
MSB
WORD
ADDRESS (An)
STOP
P
0100011
S
ACK
START
SLAVE
ADDRESS
LSB
AI00602
R/W
DATA n DATA n+1
ACK
ACK
ACK
12/31
AI00899
NO ACK
Figure 14. Al te rnat e R E A D Mo de S equence
M41ST84Y, M41ST84W
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
START
S
SLAVE
ADDRESS
R/W
DATA n DATA n+1 DATA n+X
ACK
WRITE Mode
In this mode the master transmitter transmits to
the M41ST84Y/W slave receiver. Bus protocol is
shown in Figure 15, page 13. Following the
START condition and slave address, a logic '0' (R/
=0) is placed on the bus and indicates to the ad-
W
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
Figure 15. WRITE Mode Se qu e nce
BUS ACTIVITY:
MASTER
START
R/W
STOP
PSDA LINE
ACK
ACK
ACK
NO ACK
AI00895
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST84Y/W sla ve receiver will send
an acknowledge clock to the master transmitter after it has received the slave address (see Figure
12, page 12) and aga in after it has received the
word address and each data byte.
STOP
BUS ACTIVITY:
S
ADDRESS
SLAVE
WORD
ADDRESS (An)
ACK
DATA n DATA n+1 DATA n+X
ACK
ACK
ACK
PSDA LINE
ACK
AI00591
13/31
M41ST84Y, M41ST84W
Data Retention Mode
With valid V
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M41ST84Y/W will automatically deselect,
write protecting itself when V
(max) and V
V
PFD
by internally inhibiting access to the clock registers. At this time, the Reset pin (RST
tive and will remain active until V
nominal levels. When V
Back-up Switchover Voltage (V
switched from the V
Figure 16. Power Down/Up Mode AC Waveforms
applied, the M 41ST84Y /W can be
CC
falls between
(min). Th is is accompl ished
PFD
CC
) is driven ac-
returns to
CC
), power input is
SO
tF
tFB
V
CC
V
PFD
V
PFD
VSO
falls below the Battery
CC
pin to the SNAPHAT® (or
CC
(max)
(min)
PFO
external) battery, and the clock registers and
SRAM are maintained from the attached battery
supply.
All outputs become high impedance. On power up,
when V
tion continues for t
returns to a nominal value, write protec-
CC
. The RST signal also re-
REC
mains active during this time (see Figure 16, page
14).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
tR
tREC
tDR
tRB
INPUTS
RST
OUTPUTS
DON'T CARE
VALID VALID
(PER CONTROL INPUT)
HIGH-Z
RECOGNIZEDRECOGNIZED
(PER CONTROL INPUT)
AI03681
Table 8. Power Down/Up AC Characteristics
Symbol
(2)
t
F
t
FB
t
PFD
t
R
t
RB
t
REC(4)
t
DR
Note: 1. Valid for Ambient Operating Temperature : TA = –40 to 85°C ; VCC = 2.7 to 3.6V or 4. 5 to 5.5V (except where noted).
2. V
3. V
4. Programmable (see Table 13, page 23)
5. At 25°C (when using SOH28 + M4T28-BR12SH SNA PHAT top); V
V
(max) to V
PFD
(3)
V
(min) to VSS VCC Fall Time
PFD
PFI to PFO Propagation Delay 15 25 µs
V
(min) to V
PFD
VSS to V
(min) VCC Rise Time
PFD
Power up Deselect Time 40 200 ms
(5)
Expected Data Retention Time
(max) t o V
PFD
(min) .
V
PFD
(min) to VSS fall time of less than tFB may cause corruption of RA M data.
PFD
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes
PFD
Parameter
(min) VCC Fall Time
PFD
(max) VCC Rise Time
PFD
(1)
CC
Min Typ Max Unit
300 µs
10 µs
10 µs
1µs
10
= 0V.
YEARS
14/31
CLOCK OPERATION
The eight byte clock register (see Table 9, page
16) is used to both set the clock and t o read the
date and time from the clock, in a binary coded
decimal format. Tenths/Hundredths of Seconds,
Seconds, Minutes, and Hours are contained within
the first four registers.
Note: A WRIT E to any c lock reg ister w ill resu lt in
the Tenths/Hundredths of Seconds bei ng reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Regi ster
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h contains the S TOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expected to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts
within one second.
The eight clock registers may be read on e byte at
a time, or in a sequential block. T he Control Register (Address location 08h) may be accessed independently. Provision has been made to assure
that a clock update does not occur while any of the
M41ST84Y, M41ST84W
eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halte d. This will pr event a trans ition of
data during the READ.
Note: When a power failure occurs, the Halt Update Bit (HT) will automatically be set to a '1.' This
will prevent the clock from updating the TIMEKEEPER
the exact time of the power-down event. Resetting
the HT Bit to a '0' will allow the clock to update the
TIMEKEEPER registers with the current time.
TIMEKEEPER
The M41ST84Y/W offers 12 additional internal
registers which contain the Alarm, Watchdog,
Flag, Square Wave and Control data. These registers are memory locations which contain external
(user accessible) and internal copies of the data
(usually referred to as BiPORT
cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the
incremented internal copy. The internal divider (or
clock) chain will be reset upon the completion of a
WRITE to any clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resum e either due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
TIMEKEEPER and Al arm Registers store data in
BCD. Control, Watchdog and Square Wave Registers store data in Binary Format.
®
registers, and will allow the user to read
®
Registers
™
TIMEKEEPER
15/31
M41ST84Y, M41ST84W
Table 9. TIMEKEEPER® Register Map
Address
Data
D7 D6 D5 D4 D3 D2 D1 D0
00h 0.1 Seconds 0.01 Seconds Seconds 00-99
01h ST 10 Seconds Seconds Seconds 00-59
02h 0 10 Minutes Minutes Minutes 00-59
03h CEB CB 10 Hours Hours (24 Hour Format) Century/Hours 0-1/00-23
04hTR0000 Day of Week Day 01-7
05h 0 0 10 Date Date: Day of Month Date 01-31
06h00010M Month Month 01-12
07h 10 Years Year Year 00-99
08h OUT FT S Calibration Control
09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
0Ah AFE SQWE ABE Al 10M Alarm Month Al Month 01-12
0Bh R PT4 RPT5 AI 10 Date Alarm Date Al Date 01-31
0Ch RPT3 HT AI 10 Hour Alarm Hour Al Hour 00-23
0Dh RPT2 Alarm 10 Minutes Alarm Minutes Al Min 00-59
Function/Ran ge
BCD Format
0Eh RPT1 Alarm 10 Seconds Alarm Seconds Al Sec 00-59
0Fh WDF AF 0 BL 0 0 0 0 Flags
10h00000000Reserved
11h00000000Reserved
12h00000000Reserved
13h RS3 RS2 RS1 RS0 0 0 0 0 SQW
Keys : S = Sig n Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag (Rea d only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Centur y B i t
OUT = Output level
AFE = Alarm Flag Enable Flag
RB0-RB 1 = Watchdog Resolution Bit s
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm f l ag (Read only)
SQWE = Square Wave Enable
RS0-RS 3 = S Q W Frequency
HT = Halt Up date Bit
REC
Bit
TR = t
16/31
Calibrating the Clock
The M41ST84Y/W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not exceed +/–35 PPM
(parts per million) oscillator frequency error at
o
C, which equates to about +/–1.53 minutes per
25
month. When the Calibration circuit is properly employed, accuracy improves to better than +1/–2
PPM at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 20, page 24). Therefore, the
M41ST84Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 21, page 24.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register (08h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 m inute
cycle. The first 62 m inutes i n t he c ycle m ay , onc e
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, t he first 12 will be affected,
and so on.
Therefore, each cal ibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustm ent per calibration step in the cal ibration registe r. Ass um ing that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
M41ST84Y, M41ST84W
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41ST84Y/W may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration byte.
The second approach is better suit ed to a manufacturing environment, and involves the use of the
/FT/OUT pin. The pin will toggle at 512Hz,
IRQ
when the Stop Bit (S T, D7 of 01h) is '0, ' the Frequency Test Bit (F T, D6 of 08h) is '1 ,' the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is '0, ' and the
Watchdog Steering Bit (WDS, D7 of 09h) is '1' or
the Watchdog Register (09h = 0) is reset.
Any deviation from 512 Hz i ndicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124 Hz would indicate a +20 PPM oscillator frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequency.
The IRQ
which requires a pull-up resistor to V
operation. A 500 to 10k resistor is recom mended
in order to control the rise time. The FT Bit is
cleared on power-down.
/FT/OUT pin is an open drain output
for proper
CC
17/31
M41ST84Y, M41ST84W
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm se ttings. The alarm can be configured to go off at a
prescribed time on a specific mont h, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can al so be programmed to go off while the M41ST84Y/W is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 10, p age 1 8 shows the possible configurations. Codes not listed in the table default to the once per second mode t o qu ick ly ale rt
the user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the m atch criteria d efined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activa te s th e IR Q
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad-
Figure 17. Alarm Interrupt Reset Waveform
/FT/OUT pin.
dress. It should also be noted that if the last address written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
The IRQ
/FT/OUT output is cleare d by a RE AD to
the Flags Register as sho wn in Figu re 17. A subsequent READ of the Flags Register is necessary
to see that the value of the Alarm Flag has been
reset to '0.'
The IRQ
battery back-up mode. The IRQ
/FT/OUT pin can also be activated in the
/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Bat tery Back-up Mode Enable) and A FE are set . The
ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41ST84Y/W wa s in the deselect mode during power-up. Figure 18, page 19
illustrates the back-up mode alarm timing.
0Fh0Eh 10h
ACTIVE FLAG
IRQ/FT/OUT
HIGH-Z
Table 10. Alarm Repeat Modes
RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting
11111Once per Second
11110Once per Minute
11100Once per Hour
11000Once per Day
10000Once per Month
00000Once per Year
AI03664
18/31
Figure 18. Back-Up Mode Alarm Waveform
V
CC
V
PFD
V
SO
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
M41ST84Y, M41ST84W
tREC
HIGH-Z
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second,
10 = 1 secon d, and 11 = 4 seconds. The am ount
of time-out is then determined to be the multiplication of t he five -bit m ult iplie r valu e w ith t he reso lution. (For example: writing 00001110 in the
Watchdog Register = 3*1, or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M41ST84Y/W s ets the WD F
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the wa tchdog will activ ate the IRQ
/FT/OUT
pin when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RS T
pin for t
. The Watchdog register, FT, AFE, ABE
REC
and SQWE Bits will reset t o a '0' at the end of a
Watchdog time-out when the WDS Bit is set to a
'1.'
HIGH-Z
AI03920
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) c an be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a WRITE of the
Watchdog Register. The time-out period then
starts over.
Note: The WDI pin should be tied to V
SS
if not
used.
In order to perform a software reset of the watch-
dog timer, the original time-out period can be written into the Watchdog Register, effectively
restarting the cou nt-d o wn cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ
/FT/OUT pin. This will also
disable the watchdog funct ion until i t is agai n programmed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ
/FT/OUT pin and the Frequency Test (FT)
function is activated, the watchdog function prevails and the Frequency Test function is denied.
19/31
M41ST84Y, M41ST84W
Square Wave Output
The M41ST84Y/W of fers the user a programmable square wave function which is output on the
SQW pin. The RS3-RS0 Bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 11. Once the selection
Table 11. Square Wave Output Frequency
Square Wave Bits Square Wave
RS3 RS2 RS1 RS0 Frequency Units
0000None–
0 0 0 1 32.768 kHz
0 0 1 0 8.192 kHz
0 0 1 1 4.096 kHz
0 1 0 0 2.048 kHz
0 1 0 1 1.024 kHz
0110512Hz
0111256Hz
of the SQW frequency has been c ompleted, the
SQW pin can be turned on and off under software
control with the Square Wave Enable Bit (S QWE)
located in Register 0Ah.
1000128Hz
100164Hz
101032Hz
101116Hz
11008Hz
11014Hz
11102Hz
11111Hz
20/31
M41ST84Y, M41ST84W
Power-on Reset
The M41ST84Y/W continuously monitors V
When V
the RST
power-up for t
The RST
falls to the power fail detect trip point,
CC
pulls low (open drain) and remains low on
after VCC passes V
REC
PFD
pin is an open drain output and an appro-
CC
(max).
priate pull-up resistor should be chosen to cont rol
rise time.
Figure 19. RSTIN
RSTIN
RST
Note: With pull- up r esist or
Timing Waveform
tRLRH
(1)
tRHRSH
Reset Input (RSTIN
.
The M41ST84Y/W prov id es an i ndependent input
)
which can generate an output reset. The duration
and function of this reset is identical to a reset generated by a power cycle. T able 12, page 21 and
Figure 19 , pa ge 21 illu st r at e t he A C re s et c h ar ac teristics of this function. Pulses shorter than t
will not gene ra te a reset condition. RS T IN is internally pulled up to V
through a 100kΩ resi stor.
CC
AI03682
RLRH
Table 12. Reset AC Characteristics
Symbol
(2)
t
RLRH
(3)
t
RHRSH
Note: 1. Valid for Ambient Operating Temperature : TA = –40 to 85°C ; VCC = 2.7 to 3.6V or 4. 5 to 5.5V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Programmable (see Table 14, page 23)
RSTIN Low to RSTIN High 200 ns
RSTIN High to RST High 40 200 ms
Parameter
(1)
Min Max Unit
21/31
M41ST84Y, M41ST84W
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an internal reference voltage (1.25V). If PFI is less than
the power-fail threshold (V
Output (PFO)
will go low. This function is intended
for use as an under-voltage de tector to signal a
failing power supply. Typically PFI is connected
through an external voltage divider (see Figure 7,
page 6) to either the unregula ted DC input (if it is
available) or the regulated output of the V
lator. The voltage divider can be set up such that
the voltage at PFI falls below V
onds before the regulated V
M41ST84Y/W or t he m icroproc essor drops below
the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO
curs after V
er returns, PFO
goes (or remains) low. This oc-
drops below V
CC
is forced high, irrespective of V
for the write protect time (t
from V
(max) until the inputs are recognized. At
PFD
the end of this time, the power-fail comparator is
enabled and PFO
follows PFI. If the comparator is
unused, PFI should be connected to V
left unconnected.
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a “1” will cause CB to toggle, either from a “0” to “1” or from “1” to “0” at the
turn of the century (depending upon its initial
state). If CEB is set to a “0”, CB will not toggle.
Output Driver Pin
When the FT Bit, AFE B it and watchdog register
are not set, the IRQ
/FT/OUT pin becomes an output driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT
Bit) and D6 (FT Bit) of address location 08h are a
'0,' then the IRQ
Note: The IRQ
/FT/OUT p in w ill be dr iv en lo w .
/FT/OUT pin is an open drain which
requires an external pull-up resistor.
Battery Low Warning
The M41ST84Y/W auto matically perf orms bat tery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to b e less than approximately 2.5V. T he
), the Power-Fail
PFI
several millisec-
PFI
input to the
CC
(min). When pow-
PFD
), which is the time
REC
SS
regu-
CC
PFI
and PFO
BL Bit will remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the nex t power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data sho uld
be considered suspect an d verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V
CC
is
supplied. In order to insure data integrity during
subsequent periods of bat tery back-up m ode, the
battery should be replaced. The SNAPHAT top
may be replaced while V
is applied to the de-
CC
vice .
Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is
disconnected.
The M41ST84Y/W only monitors the battery when
a nominal V
is applied to the device. Thus appli-
CC
cations which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
Bit
t
REC
Bit D7 of Clock Register 04h contains the t
(TR). t
the deselec t ti m e after V
refers to the automatic continuation of
REC
reaches V
CC
PFD
Bit
REC
. This al lows for a voltage setting time before WRITEs may
again be performed to the device after a powerdown condition. The t
Bit will allow the user to
REC
set the length of t his deselect tim e as defined by
Table 13, page 23.
Initial Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watchdog Register, TR, FT, AFE, ABE, and SQWE. The
following bits are set to a '1' state: ST, OU T, and
HT (see Table 14, page 23).
22/31
M41ST84Y, M41ST84W
Table 13. t
t
REC
Definitions
REC
Bit (TR)
0 0 96 98 ms
0140
1 X 50 2000 µs
Note: 1. Default S et ting
Table 14. Default Values
Condition TR ST HT Out FT AFE ABE SQWE
Initial Power-up
(Battery Attach for SNAPHAT)
Subsequent Power-up (with
battery back-up)
Note: 1. WDS, BM B0-BMB4, RB 0, RB1.
2. State o f ot her control b its undefined .
3. UC = Unchanged
(3)
(2)
t
Time
STOP Bit (ST)
REC
Min Max
(1)
200
WATCHDOG
Register
0111000 0 0
UC UC 1 UC 0 0 0 0 0
Units
ms
(1)
23/31
M41ST84Y, M41ST84W
Figure 20. Crystal Accuracy Across Temp eratur e
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0 10203040506070
∆F
F
Temperature °C
= -0.038 (T - T
ppm
C
2
T0 = 25 °C
)2 ± 10%
0
80–10–20–30–40
AI00999
Figure 21. Cloc k C al ib rat i on
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
24/31
PACKAGE MECHANICAL INFORMATION
Figure 22. SO16 – 16-lead Plastic Small Outline, Package Outline
M41ST84Y, M41ST84W
A2
A
B
e
CP
D
N
E
H
1
SO-b
Note: Drawing is not to scale.
Table 15. SO16 – 16-lead Plastic Small Outline, Package Mechanical Data
Symbol
T yp. Min. Max. Typ. Min. Max.
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
mm inches
C
LA1 α
A2 1.60 0.063
B 0.35 0.46 0.014 0.018
C 0.19 0.25 0.007 0.010
D 9.80 10.00 0.386 0.394
E 3.80 4.00 0.150 0.158
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
L 0.40 1.27 0.016 0.050
a0°8°0°8°
N16 16
CP 0.10 0.004
25/31
M41ST84Y, M41ST84W
Figure 23. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline
A2
A
C
Be
eB
CP
D
N
E
H
LA1 α
1
SOH-A
Note: Drawing is not to scale.
Table 16. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
Symbol
Typ Min Max Typ M in Max
A 3.05 0.120
millimeters inches
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.7 0 0.453 0.500
L 0.41 1.2 7 0.016 0 .050
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004
26/31
M41ST84Y, M41ST84W
Figure 24. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A2
A3
L
eA
D
A1
A
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 17. SH – 4-pin SN AP HAT Hous ing for 48mAh Battery & Cry stal, Package Mechanical Data
Symbol
T yp Min Max Typ Min Max
A 9.78 0.3850
millimeters inches
A1 6.73 7.24 0.2650 0.2850
A2 6.48 6.99 0.2551 0.2752
A3 0.38 0.0150
B 0.46 0.56 0.0181 0.0220
D 21.21 21.84 0.8350 0.8598
E 14.22 14.99 0.5598 0.5902
eA 15.55 15.95 0.6122 0.6280
eB 3.20 3.61 0.1260 0.1421
L 2.03 2.29 0.0799 0.0902
27/31
M41ST84Y, M41ST84W
Figure 25. SH – 4-pi n SNAPHA T Housing for 120mAh Battery & Crystal, Package Outline
A2
A3
L
eA
D
A1
A
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH – 4-pin SNAPH AT Hou sing for 1 20mAh B attery & C r ystal, Package Mechanical Data
Symbol
T yp Min Max Typ Min Max
millimeters inches
A 10.54 0.4150
A1 6.73 7.24 0.2650 0.2850
A2 6.48 6.99 0.2551 0.2752
A3 0.38 0.0150
B 0.46 0.56 0.0181 0.0220
D 21.21 21.84 0.8350 0.8598
E 14.22 14.99 0.5598 0.5902
eA 15.55 15.95 0.6122 0.6280
eB 3.20 3.61 0.1260 0.1421
L 2.03 2.29 0.0799 0.0902
28/31
M41ST84Y, M41ST84W
PART NUMBERING
Table 19. Ordering Information Scheme
Example: M41ST 84Y MQ 6 TR
Device Type
M41ST
Supply Voltage and Write Protect Voltage
84Y = V
84W = V
Package
MQ = SO16
MH
= 4.5 to 5.5V; 4.20V ≤ V
CC
= 2.7 to 3.6V; 2.55V ≤ V
CC
(1,2)
= SOH28
PFD
PFD
≤ 4.50V
≤ 2.70V
Temperature Rang e
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The 28-p i n SOIC package (SOH28) requires the battery/ crystal package (SNA P HAT®) which is ordered s eparately under the part
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell batt ery.
number “M 4T XX-BR12SHX” in plastic tube or “M4TX X-BR12SH X T R” in Tape & Re el form.
2. Con tact Local Sale s O ffice
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 20. SNAPHAT Battery Table
Part Number Description Package
M4T28-BR12SH Lithium Battery (48mAh) and Crystal SNAPHAT SH
M4T32-BR12SH Lithium Battery (120mAh) and Crystal SNAPHAT SH
29/31
M41ST84Y, M41ST84W
REVISION HIST ORY
Table 21. Document Revision History
Date Rev. # Revision Details
August 2000 1.0 First Issue
24-Aug-00 1.2 Block Diagram added (Figure 6)
08-Sep-00 1.3 SO16 package measures change
18-Dec-00 2.0 Reformatted, TOC added, and PFI Input Leakage Current added (Table 5)
18-Jun-01 2.1
Addition of t
graphic (see Figure 6); change to DC and AC Characteristics, Order Information (Tables 5, 7,
19); note added to “Setting Alarm Clock Registers” section; added temp./voltage info. to
information, table changed, one added (Tables 9, 13); changes to PFI/PFO
REC
tables (Table 4, 5, 6, 7, 8); addition of Default Values (Table 14); textual improvements
25-Jun-01 2.2 Special note added in “Clock Operation” section (page 15)
26-Jul-01 3.0 Change in Product Matu rity
07-Aug-01 3.1 Improve text for “Setting the Alarm Clock” section
20-Aug-01 3.2
06-Sep-01 3.3
03-Dec-01 3.4
Change V
DC Characteristics V
Electrical Characteristics Series Resistance spec. changed (Tables 5, 6)
Change READ/WRITE Mode Sequence drawings (Figure 13, 15); change in V
for 5V (M41ST84Y) part only (Table 5, 19)
values in document
PFD
changed; PFI Hysteresis (PFI Rising) spec. added; and Crystal
BAT
lower limit
PFD
14-Jan-02 3.5 Change Series Resistance (Table 6)
01-May-02 3.6
Change t
Definition (Table 13); modify reflow time and temperature footnote (Table 2)
REC
03-Jul-02 3.7 Modify DC and Crystal Electrical Characteristics footnotes, Default Values (Tables 5, 6, 14)
01-Aug-02 3.8 Add marketing status (Figure 2; Table 19)
16-Jun-03 4.0 New Si changes (Table 8, 12, 13, 14)
30/31
M41ST84Y, M41ST84W
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