6.ELECTRICAL PARTS LIST ··································· 27
SAFETY-RELATED COMPONENT WARNING!!
COMPONENTS IDENTIFIED BY MARK ! OR DO TTED LINE WITH
MARK ! ON THE SCHEMATIC DIAGRAMS AND IN THE PARTS
LIST ARE CRITICAL TO SAFE OPERATION. REPLACE THESE
COMPONENTS WITH SONY PARTS WHOSE PART NUMBERS
APPEAR AS SHOWN IN THIS MANUAL OR IN SUPPLEMENTS
PUBLISHED BY SONY.
— 2 —
SECTION 1
GENERAL
This section is extracted
from instruction manual.
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SECTION 2
)
e
DISASSEMBLY
Note: Follow the disassembly procedure in the numerical order given.
2-1.REMOVAL OF CASE (LOWER)
4
1
Battery lid
Case (upper)
Precision screwdriver
2
+K2 ×8
Case (lower)
Case (upper)
×
6
Claw
3
Insert a precision screwdriver tip in between the Case (upper
and the Case (lower). When the Cases are opened a little,
2
+K2 ×8
insert nail of your thumb into the clearance. Open the Covers
while sliding the Covers upwards.
2-2.REMOVAL OF T.T.P, LCD, RUBBER SWITCH, MAIN BOARD
2
Case (upper)
3
Remove soldering of th
T.T.P. and remove it.
4
LCD
5
Rubber switch
6
MAIN board
— 15 —
1
+P2 ×5
Case (lower)
TEST Mode (Operation Check)
SECTION 3
TEST MODE
Preform the following operation checks using the TEST Mode before
starting the repair works.
1. All Keys Operation Check
Connection Method :
Regulated power supply
(+6V constant voltage output)
set
+6V pin
(See Fig. 3-1.)
1) While pressing the PROGRAM + key and the Á + key,
ture ON the main power of the regulated power supply (DC
+6V). (Refer to Fig. 1-1.)
2) Remove all hands from pressing the all keys described in abov e
step 1). The all indications of the LCD must be turned OFF.
(Refer to Fig. 1-2.)
3) When any key of the Operation panel-key block (except
the COMMANDER OFF key), or any key of the LCD touchkey block is pressed, the signal (carrier 40kHz) as shown in
Fig. 1-3 must be transmitted in accordance the pressed key , when
operation of the machine is normal.
4) Press all keys of the Operation panel-key block (except the
COMMANDER OFF key, and of the LCD touch-key block
sequentially. When all keys are pressed, confirm that the long
buzzar sound and all LCD displays are turned off.
NOTE : Be careful that all data in S-RAM is cleared
when the above TEST mode is performed.
+
–
LCD touch-key block
Operation
panel-key block
PROGRAM
++
While pressing both keys
at the same time;
COMMANDER OFF
Á
Fig. 1-1
PROGRAM +
Á
+
Turn ON the
main power (DC 6V)
• This TEST Mode can be terminated in its middle before testing
all keys by pressing the COMMANDER OFF key . However
the conduction check of the remairing keys cannot be checked.
(S-RAM is not cleared.)
• P-ROM (IC8) is diagnosed to be free from defects when the
steps from 1) to 4) are performed correctly.
Fig. 1-2
2.4mscc2.4mscc2.4mscc
600 µ sec600 µ sec
— 16 —
Fig. 1-3
2. S-RAM (Learning Function) Operation Check
y
Connection Method :
3. Oscillation frequency Check
Connection Method :
MAIN board
Regulated power supply
(+6V constant voltage output)
set
+6V pin
+
–
1) While pressing the Á – key and the PROGRAM – key,
ture ON the main power of the regulated power supply (DC
+6V). (Refer to Fig. 2-1.)
2) When LEARN only of the LCD display appears, remove
hands from pressing the above mentioned keys. (Refer to Fig.
2-2.)
3) The display appears when the S-RAM is not defective. (The
diaplay NG appears when the S-RAM is defective.) (Refer to
Fig. 2-2.)
4) The display status as described in step 3) continues until any
key is pressed.
• S-RAM (IC3) is diagnosed to be free from defects when the
above steps from 1) to 4) are performed correctly.
PROGRAM –
PROGRAM
––
While pressing both keys at the same time;
Á
Turn ON the
regulated power suppl
Á
MAIN BOARD (CONDUCTOR SIDE)
–
TP GND
TP VDD
2140
41
20
Regulated
power supply
(DV +6V constant
voltage)
+
−
IC1
60
61
TP3
24
25
1
80
1
80
IC1 ^¡ pin
IC1 ^º pin
SW1
SW2
TP3
+
−
frequency cunter
IC2
40
41
65
64
(NG)(OK)
Fig. 2-1
Fig. 3-1
LEARN
1) After turning the switches SW1 and SW2 both ON, turn on the
main power of a frequency counter and that of the regulated
power supply (DC +6V constant voltage).
2) Take r eading of frequenc y counter indication value. This v alue
is named fA.
3) Turn off the regulated power supply, then turn OFF the switch
SW1. After that, turn back ON the regulated power supply.
4) Take reading of frequency counter value in the same way as
step 2). This value is named fB.
5) Using the frequency values that are measured in steps 2) and
After a while
4), calculate the crystal oscillator frequency f1 and the crystal
oscillator frequency f2 using the following equations. Confirm
that the respective specification values are satisfied.
Caution:
Pattern face side: Parts on the pattern face side seen from
(Conductor Side)the pattern face are indicated.
Parts face side:Parts on the parts face side seen from
(Component Side) the parts face are indicated.
• b : Switch pattern
: Through hole.
4-2.SCHEMATIC DIAGRAM – MAIN SECTION – • See Page 23, 25 IC Pin Function.
Pull-up resistor can be built-in in units of bit. (mask option).
10V withstand voltage in the open-drain connection.
Edge detection vector interrupt input terminal.
I
(Both of the rise-up and fall-down edge detections are usable.)
I/O
Serial clock input/output terminal.
Serial data output terminal.
I/O
Serial bus input/output terminal.
Serial data input terminal.
I/O
Serial bus input/output terminal.
Equipped with noise-rejection function.
4-bit input port (PORT 0).
The pull-up resistor built-in can be
specified in units of 3 bits by
software for PO1 to PO3.
4-bit input port (PORT 1).
The pull-up resistor built-in can
be specified in units of 4 bits by
software.
4-bit input port (PORT 2).
The pull-up resistor built-in can be
specified in units of 4 bits by
software.
Programmable 4-bit input/output
port. (PORT 3).
Input and output can be set in units
of bit.
The pull-up resistor built-in can be
specified in units of 4 bits by
software.
Positive power supply terminal.
Terminal to which sub-system clock oscillating crystal is connected.
I
When external clock is used, input the ext. clock to XT1 and leave XT2 open.
–
XT1 can be used as the 1-bit input (TEST) terminal.
–
Internally connected to VDD.
I
Terminal to which main system clock oscillating crystal/ceramic is connected.
–
When external clock is used, input the ext. clock to X1, and connect the inverted phase signal to XT2.
I/O
I/O
Parallel fall-down edge detection
I/O
testable input terminal.
I/O
I/O
I/O
Parallel fall-down edge detection
testable input terminal.
I/O
I/O
System reset input terminal.
I
Segment signal output terminals.
O
Pin Function
Programmable 4-bit input/output port. (PORT 8).
Input and output can be specified in units of bit.
The pull-up resistor built-in can be specified in units of
4 bits by software.
4-bit input/output port. (PORT 7).
The pull-up resistor built-in can be specified in units of
4 bits by software.
— 23 —— 24 —
• IC2 (µPD65012)
Pin No.
1 to 8
9 to11
12
13 to 20
21 to 28
29
30 to 32
33
34
35 to 38
39
40 to 42
43 to 50
51 to 52
53
54 to 59
60 to 63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
ID7 to ID0
IENN/IWIN
IRDN.
GND
IP30 to IP37
IP40 to IP47
KINT
IP50 to IP52
GND
VDD
KINT
IP53 to IP56
REC
RDO.WTO
OCE
OD0 to OD7
AD0 to AD1
GND
AD2 to AD7
AD8 to AD11
OUTP
RMO
OP60
OP61
OP62
OP63
OP64
GND
VDD
OP65
OP66
OP67
CLR
ICLK
RES
INT
IALE
I/O
I/O
Data transfer between µPD65012 and microprocessor.
I
Control input from microprocessor.
—
GND terminal.
I
Key scan input.
I
Key scan input.
I
Not used.
—
GND terminal.
—
Positive power supply terminal.
I
Not used.
I
Remote control signal received input.
O
External memory control output.
I/O
Data transfer between µPD65012 and external memory.
O
Terminals to which external memory is connected. Lower address (ADO to AD1)
—
GND terminal.
O
Terminals to which external memory is connected. Lower address (AD2 to AD7)
O
Terminals to which external memory is connected. Upper address (AD8 to AD11)
O
Not used.
O
Remote control signal output.
O
Remote control signal receiver block ON/OFF output.
O
SRAM IC3 (W24257S) ADD and IC8 (LH5359PA) ADD.
O
SRAM IC3 (W24257S) ADE and IC8 (LH5359PA) ADE.
O
Selector SRAM IC3 (W242575S) or ROM IC8 (LH5359PA)
O
EL control output. (Dark)
—
GND terminal.
—
Positive power supply terminal.
O
Terminals to which external memory is connected. Upper address. (AD12)
O
EL control output. (Bright).
O
Buzzer
I
GA reset input.
I
GA clock input.
I
Not used.
O
Microprocessor interrupt output.
I
Address latch enable input.
Pin Function
— 25 —
SECTION 5
EXPLODED VIEWS
NOTE:
• -XX, -X mean standardized parts, so they may
have some differences from the original one.
• Items marked “*” are not stocked since they
are seldom required for routine service. Some
delay should be anticipated when ordering these
items.
2
• The mechanical parts with no reference number
in the exploded views are not supplied.
12
19
The components identified by mark ! or
dotted line with mark ! are critical for safety .
Replace only with part number specified.