• Keep the temperature of the soldering iron around 270 ºC during repairing.
• Do not touch the soldering iron on the same conductor of the
circuit board (within 3 times).
• Be careful not to apply force on the conductor when soldering
or unsoldering.
Notes on chip component replacement
• Never reuse a disconnected chip component.
• Notice that minus side of a tantalum capacitor may be damaged
by heat.
CM-H777/H888 I/F boardCM-H777RC/H888RC I/F board
Note for the replacement of AT24C32N-10SI-2.7 (U8A)
• IC A T24C32N-10SI-2.7 (E
board is not available itself due to the volume data characteristics for audio and etc. is difference each IC.
Therefore, the RAGIC board have to replace completely.
2
PROM) of RA GIC mounted circuit
– 2 –
SECTION 2
CIRCUIT DESCRIPTION
2-1. LOGIC CIRCUIT DESCRIPTION
The functional block diagram is shown in LOGIC CIRCUIT
BLOCK DIAGRAM.
The logic circuit consists of the following parts.
The audio from the microphone is amplified at the microphone
amplifier, goes through the analog switch and transmit audio is
input at the transmit-audio terminal. The analog switch can be
turned off with Command 5100 (Change-path) of the test set when
the characteristics of transmit audio of the radio unit is measured.
The audio is compressed at the compressor. The compressor output does through the band pass filter, pre-emphasis, de viation limiter, and post-deviation filter, and is added with the control signal
at the audio signal processor. T he summed signal is applied to the
modulation input terminal of the radio portion.
The demodulated signal from the receiver goes through the deemphasis circuit in the audio signal processor, the band pass filter
and the expander, and is added at the summing amplif ier with the
tone signal. The summed signal is applied to the receive audio
terminal.
Analog SW , Compressor and e xpander is in the Audio signal processor.
Wide band data signal is applied to the audio signal processor via
FMDEM terminal, and is converted into the logic level signal at
the comparator. Then the signal goes to the digital processor
(KE5A220 or KE5A221) and acquires bit synchronization at the
digital phase locked loop circuit. Next, the signal is con verted into
non-return zero signal from Manchester code at the integrated and
dump circuit. From this signal Barker code (11100010010) is detected at the word synchronizing detection circuit, and then the
information and parity bit signal (40 bits) is cleaned up by a 3/5
majority vote circuit.
From the signal, syndrome is detected at the syndrome detector,
and an interrupt is requested on the MPU to inform the reception
of the signal. When an interrupt occurs the software of the MPU
allows 28 information bits and 12 parity bits to enter the MPU by
way of data bus. The software checks syndrome at first, then will
do error correction, if there are any.
2-2. RADIO CIRCUIT DESCRIPTION
2-2-1. General Description
The functional block diagram is shown in the radio circuit block
diagram.
Signals received from the cell site pass through the duplexer to the
receiver circuit, where they are amplified and demodulated. The
received signals may be voice and/or coded signaling information. From the receiver circuit, voice signals and coded signaling
information are sent to the logic circuit.
To transmit signals, the Transmitter carrier is frequency-modulation with voice and/or coded signaling information. The carrier is
then passed through a duplexer to the antenna.
For wideband data transmission, the data signal is first encoded
into the BCH code with the software for the MPU. The BCH code
is sent via the 8-bit data bus to digital processor (KE5A220 or
KE5A221). The parallel data bus is con verted to serial data to the
32-bit shift register of digital signal is sent to the audio signal
processor.
In the audio signal processor, the Manchester code signal goes
through analog switch, variable resistor T.DATA VR5 (variable
from +1.6 to –1.4 dB in 0.2 dB steps), the 4th order low pass filter
with 20 kHz cut-off frequency and lastly TX VR3 (variable from
–2.5 dB to –15.2 dB in 0.1 dB steps), and then appears at the
FMMOD terminal.
Supervisory audio tones (SAT: 6030 Hz, 6000 Hz, 5970 Hz) are
demodulated at the radio portion and appears at the FMDEM terminal. The SAT signal is then applied to the logic portion. The
SAT signal goes through the band pass filter having the 6-kHz
center frequency in the audio signal processor, and is con v erted to
logic level signal through the comparator . T he logic lev el signal is
phase-synchronized at the digital phase locked loop in digital processor. T he comparator output goes through SAT data remark and,
the low pass filter, TSAT VR6 (variable from –9.6 to –14.1 dB in
0.3 dB steps), analog switch in the audio signal processor. Thereafter, the SAT signal takes the same signal processing route as the
wide band data signal.
2-2-2. Synthesizer Circuit
The equipment has two phase-locked-loop frequency synthesizer .
One is used to produce the RF modulator. Another one is used to
produce the RF signals for 1st local oscillator injections of the
receiver.
The synthesizer of 1st local and TX local oscillator (U306) controls an RF signal, between 941 MHz and 966 MHz, or 824 MHz,
and 849 MHz according to a DC control voltage. The internal dual
modules prescaler divides the signal from the buffer amplifier by
128 or 129. The output of a portion of the programmable divider
function determines whether 128 or 129 is a divider. Channel assignment numbers are determined by a 18 bit serial data input sequence from the logic circuit.
The phase detector compares the phases of the two signals from
the dividers and drivers the charge pump according to the comparison result. If the loop goes out of lock, the phase detector generates an unlock detect signal.
The charge pump translates the digital output of the phase detector into a current source or sink (depending on the phase information). The low-pass filter integrates this change in correct to produce the DC voltage that controls the VCO (U305 and U404) output frequency.
Dual Tone Multipul-Frequency signal is generated at the audio
signal processor, and the signal is converted into sine wave. Then
the sine wave signal is passed through DTMF VR10. After that,
the signal takes the same signal processing route as voice.
The 14.4 MHz TCXO (U307) output is divided by 960 to produce
the 15.0 kHz reference frequency for the synthesizer.
– 3 –
2-2-3. Transmitter Circuit
The modulator generates transmit signal with VCO and to fed the
discrete switch circuit.
The output signal of the discrete switch circuit is fed to the power
amplifier (U402).
The output signal of the power amplifier is fed to the directional
coupler (U401) and then the duplexer filter (FL401).
A sample of the RF output power is coupled off, and passed through
the detector (CR401) and fed to the logic circuit for APC loop.
The p-cont signal from the logic circuit controls power amplifier
level controllers (Q403, Q405) to control the power amplifier
(U402) output level.
2-2-4. Receiver Circuit
The receiver is a double conversion super-heterodyne receiver,
capable of receiving frequencies from 869 MHz to 894 MHz.
The RX signal from duplexer filter (FL401) is amplified by LNA
(Q301) with band-pass filter (FL301) and fed to the double balanced mixer (U301).
The synthesizer output signal is also fed to the mixer to obtain the
first IF signal (72.06 MHz).
The first IF signal is fed to the second mixer through first amplifier (Q303) and x’tal filter (FL302) and then heterodyned with a
fixed 72 MHz second local VCO signal obtain a 60 kHz second IF
signal.
The second local oscillator signal is produce by signal synthesizer
(U304) and discrete VCO.
After this frequency conversion, the signal second IF fed to the
monolithic low-power IF system (U302) incorporating two limiting IF amplifiers quadrature detector, logarithmic signal strength
indication (RSSI) and voltage regulator.
The detected output signal and RSSI signal are fed to the logic
circuit.
– 4 –
2-3. POWER SUPPLY FLOW CHART
..................
BATTERY
SYNTHESIZER
U306 pin
!™
(SYN DATA)
V
DD
T
Tx EN
(U405 pin
1
)
SEND key
End key
V
DD
1, V
DD
2
Rx En
(U3 pin 7, !º)
V
DD
R1 ON
(U3 pin $¢)
Power SW
V
DD
U
V
DD
B
(U3 pin
3
)
+B
U306 pin
!¡
(SYN CLK)
U306 pin
!£
(SYN STB)
LOCKDET 1
(U1A pin
*∞
)
RF Power
(U402 pin
!™
)
ON
ENDSEND
C ch
V ch
C ch
OFF
LogicnRF
Logic
n
RF
Logic
n
RF
RF
n
Logic
Logic
n
RF
– 5 –
SECTION 3
r
TOOLS
Fig.DescriptionPart No.Remarks
1 LR Screw Bit3-387-376-01
2 Converter Box3-702-720-01RC232C Interface Box
3 Test Cable G3-702-721-01Test cable for Alignment.
4 Selectable connector 13-702-735-01Connector for monitoring software version
5 Test Cable H3-702-726-01Test cable for Auto NAM
6 Connector 13-702-725-01Connector for monitoring software version
Floppy disk for User's
7
information
Floppy disk for Test
8
commandCM-H333
3-702-724-01
3-702-727-01
9 ANT driver3-702-580-01
Special shape Bit
For removing the screw of the rear cabinet Assy.
Including Test Command for CM-H888 and
1 LR Screw Bit
2 Converter box (with AC Adaptor)
3 Test Cable G
To RF
UDC
Connector
YELLOW
RED (B+)
BLACK (GND)
T o TX-A udio
To RX-Audio
5 Test Cable H
Modula
Jack
6 Connector 1
7, 8 Floppy disk
This floppy disk can be used commonly to CM-H777/H888
and others.
9 pin
D-sub
connector
To Converter box
9 ANT driver
4 Selectable Connector 1
GREEN
• You can check either a software
version or the Lock code.
ResistorItem
1 kΩSoftware ver. display
10 kΩLock code Over-ride
– 6 –
[Connecting CM-H777RC/H888RC and HP-8920A]
t
t
Use test cable G when measuring CM-H777RC/H888RC with HP-8920A.
Cellular T ester
HP-8920A
RF
YELLOW
• Volume position switch
PositionRemarks
1 kΩFor software download
Test10 kΩ
Cable G
* Set to 10 kΩ
68 kΩHand-free mode
openHand-set mode
Alignment, Auto NAM,
User's information, Test command
GREEN
Power Supply
5.8 V DC
RED
(+B)
BLACK
(GND)
Tester Cable G
9 pin
D-Sub
Converter box
IBM-PC (not supplied)
9 pin
D-Sub
(not supplied)
25 pin
D-Sub
To DC in
To AC outle
(120 V)
[Connecting CM-H777RC/H888RC and test cable H for Auto NAM]
from PC
converter box
Test Cable H
To DC in
To AC outle
– 7 –
[Connecting connector 1 to CM-H777RC/H888RC]
You can read the current software version by turning
the power on after connecting the connector 1 or selectable connector 1 first.
Connector 1
Connect the connector 1 first,
and then turn the power on.
LCD Display
Ready
–210201–
[HP8920 test condition for alignment program]
1) RF Cable loss setting
1 Press key “SIFT” + “CONFIG”
2 Set RF Level offset “ON”
3 Set RF IN/OUT “–0.7” dB (Input RF cable loss)
2) Adjust TX power levels
1 Press key “TX TEST”
2 Setting Tune mode “Auto”
3) Adjust signal modulation
1 Press key “TX TEST”
2 Setting condition at HP8920A in accordance with the