This product is classified as a CLASS 1 LASER PRODUCT.
This label is located on the bottom of the
chassis.
This label is located on the drive unit's internal
chassis.
When replacing the chassis (T) of mechanism deck which have
the “CAUTION LABEL” attached, please be sure to put a new
CAUTION LABEL (3-223-913-11) to the chassis (T).
NOTES ON HANDLING THE OPTICAL PICK-UP BLOCK
OR BASE UNIT
The laser diode in the optical pick-up block may suffer electrostatic
breakdown because of the potential difference generated by the
charged electrostatic load, etc. on clothing and the human body.
During repair, pay attention to electrostatic breakdown and also use
the procedure in the printed matter which is included in the repair
parts.
The flexible board is easily damaged and should be handled with
care.
NOTES ON LASER DIODE EMISSION CHECK
The laser beam on this model is concentrated so as to be focused on
the disc reflective surface by the objective lens in the optical pickup block. Therefore, when checking the laser diode emission, observe from more than 30 cm away from the objective lens.
Notes on Chip Component Replacement
• Never reuse a disconnected chip component.
• Notice that the minus side of a tantalum capacitor may be dam-
aged by heat.
TABLE OF CONTENTS
1. GENERAL
Location of controls................................................................. 3
4-2. Front Panel Section ...........................................................43
4-3. CD Mechanism Section (1) ............................................... 44
4-4. CD Mechanism Section (2) ............................................... 45
4-5. CD Mechanism Section (3) ............................................... 46
SAFETY-RELATED COMPONENT WARNING!!
COMPONENTS IDENTIFIED BY MARK 0 OR DOTTED LINE
WITH MARK 0 ON THE SCHEMATIC DIAGRAMS AND IN
THE PARTS LIST ARE CRITICAL TO SAFE OPERATION.
REPLACE THESE COMPONENTS WITH SONY P ARTS WHOSE
PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL OR
IN SUPPLEMENTS PUBLISHED BY SONY.
2
5. ELECTRICAL PARTS LIST ........................................ 47
6
SECTION 2
DISASSEMBLY
Note : Follow the disassembly procedure in the numerical order given.
2-1. SUB PANEL ASSY
4 two claws
6 sub panel assy
2 PTT 2.6x8
2-2. CD MECHANISM BLOCK
5 CD mechanism block
2 PTT 2.6x6
3 claw
5 CN500
1 PTT 2.6x8
7 bracket (CD)
6 PTT 2.6x6
12
3
4 CN301
1 PTT 2.6x
8
8
2-3. MAIN BOARD
6 MAIN board
5 ground point screws
(PTT 2.6x6)
4 ground point screw
(PTT 2.6x6)
3 PTT 2.6x
2 PTT 2.6x8
1 PTT 2.6x8
2-4. HEAT SINK
6 heat sink
5 PTT 2.6x
4 PTT 2.6x8
3 PTT 2.6x12
1 PTT 2.6x8
2 PTT 2.6x8
13
2-5. CHASSIS (T) ASSY
2 P 2x3
3 P 2x3
2-6. LEVER ASSY
1 Unsolder the
lead wires.
4 chassis (T) assy
black
red
white
4 claws
5 guide (disc)
6 lever (R) assy
3 tension spring (LR)
7 lever (L) assy
1 PS 2x4
2 DISC IN SW board
14
Fig. 1
3 PS 2x3
4 LOAD SW board
1 tension spring (RA)
2 arm roller assy
washer
arm
arm
washer
washerwasher
2-7. SERVO BOARD
7 PS 2x4
8 PS 2x4
3 Removal the solders.
1 CN3
5 P 2x3
6 loading motor assy
(M903)
2 CN2
9 SERVO board
4 Removal the solders.
2-8. ARM ROLLER ASSY
• When installing, take note of the positions
arm (roller) and washers. (Fig. 1)
15
2-9. CHASSIS (OP) ASSY
8 compression spring (FL)
1 tension spring (KF1)
7 chassis (OP) assy
9 compression spring (FL)
2 tension spring (KR1)
5 Fit lever (D) in the
direction of the arrow.
6 Turn loading ring in the
direction of the arrow.
4 damper (T)
2-10. OPTICAL PICK-UP BLOCK
1 P 2x3
2 sled motor assy
(M902)
3 damper (T)
3 optical pick-up block
16
SECTION 3
DIAGRAMS
3-1. IC PIN DESCRIPTIONS
• IC501 CXD2598Q (DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR) (SERVO BOARD)
Pin No.Pin NameI/OPin Description
1DVDD—Digital power supply pin
2DVSS—Digital ground
3SOUTOServo brock serial data output (Not used.)
4SOCKOServo brock serial data read clock output (Not used.)
5XOLTOServo brock serial data latch output (Not used.)
6SQSOOSub Q 80 bit, PCM peak and level data output. CD TEXT data output
7SQCKIClock input from SQSO read output.
8SCSYIFixed at “L”.
9SBSOOSerial output of sub-P to W. (Not used.)
10EXCKIClock input from SBSO read output. (Fixed at “L”)
11XRSTISystem reset (“L”: Reset)
12STSMISystem mute input (Fixed at “L”)
13DATAISerial data input from CPU.
14XLATILatch input from CPU. Latch serial data at the falling edge.
15CLOKISerial data transfer clock input from CPU.
16SENSOSENS output for CPU.
17SCLKIClock input from SENS serial data read.
18ATSKI/OInput/output for anti-shock.
19WFCKOWFCK (Write Flame Clock) output (Not used.)
20XUGFOXUGF output (Not used.)
21XPCKOXPCK output (Not used.)
22GFSOGFS output
23C2POOC2PO output (Not used.)
24SCORO“H” output at either detection, sub code sync S0 or S1.
25C4MO4.2336 MHz output (Not used.)
26WDCKOWord clock input f=2Fs (Not used.)
27COUTI/OTrack number count signal input/output (Not used.)
28MIRRI/OMirror signal input/output (Not used.)
29DVSS—Digital ground
30DVDD—Digital power supply pin
31DFCTI/ODiffect signal input/output (Not used.)
32FOKI/OFocus OK signal output
33PWM1IExternal control input of spindle motor.
34LOCKI/OLock signal input/output
35MDPOServo control output of spindle motor.
36SSTPIDisc most inner track detection signal input
37FSTIOI/O2/3 frequency division output of pins ih and ij. (Not used.)
38SFDROSled drive output
39SRDROSled drive output
40TFDROTracking drive output
41TRDROTracking drive output
42FFDROFocus drive output
43FRDROFocus drive output
44DVDD—Digital power supply pin
45DVSS—Digital ground
46TESTITest pin (Fixed at “L”)
47TES1ITest pin (Fixed at “L”)
48XTSLIX’tal select input (“L”: 16.9344 MHz, “H”: 33.8688 MHz)
49VCICenter voltage input
50FEIFocus error signal input
51SEISled error signal input
17
Pin No.Pin NameI/OPin Description
52TEITracking error signal input
53CEICenter servo analog input
54RFDCIRF signal input
55ADIOOTest pin (Not used.)
56AVSSO—Analog ground
57IGENIConstant current input from OP amplifier.
58AVDDO—Analog ground
59ASYOOEFM full-swing output (“L”: VSS, “H”: VDD)
60ASYIIAsymmetry comparate voltage input
61RFACIEFM signal input
62AVSS3—Analog ground
63CLTVIVCO control voltage input from master.
64FILOOFilter output for master PLL (slave=digital PLL)
65FILIIFilter input from master PLL.
66PCOOCharge pump output for master PLL.
67AVDD3—Analog power supply pin
68BIASIAsymmetry circuit constant current input
69VCTLIVCO2 control input from wideband EFM PLL. (Not used.)
70V16MOVCO2 oscillator output for wideband EFM PLL. (Not used.)
71VPCOOCharge pump output for wideband EFM PLL. (Not used.)
72DVSS—Digital ground
73MD2IDigital out ON/OFF control input (“L”: OFF, “H”: ON)
74DOUTODigital out output
75ASYEIAsymmetry circuit ON/OFF input (“L”: OFF, “H”: ON)
76DVDD—Digital power supply pin
77LRCKOD/A interface LR clock output (f=Fs)
78LRCKIID/A interface LR clock input
79PCMDOD/A interface serial data output (2’s COMP, MSB fast)
80PCMDID/A interface serial data input (2’s COMP, MSB fast)
81BCKOD/A interface bit clock output
82BCKIID/A interface bit clock input
83EMPHOEmphasis ON/OFF signal output
84EMPHIIEmphasis ON/OFF signal input (“H”: ON, “L”: OFF)
85XVDD—Power supply for master clock.
86XTAIIX’tal oscillator input from master clock (16.9344 MHz).
87XTAOOX’tal oscillator output for master clock (16.9344 MHz).
88XVSS—Ground pin for master clock.
89AVDD1—Analog power supply pin
90AOUT1OLch analog output
91AIN1ILch OPAMP input
92LOUT1OLch LINE output
93AVSS1—Analog ground
94AVSS2—Analog ground
95LOUT2ORch LINE output
96AIN2IRch OPAMP input
97AOUT2ORch analog output
98AVDD2—Analog power supply pin
99RMUTORch “0” detect Flug (Not used.)
100LMUTOLch “0” detect Flug (Not used.)
18
• IC5 CXP84640-063Q (CD SYSTEM CONTROL) (SERVO BOARD)
Pin No.Pin NameI/OPin Description
1ITRPT—Not used in this set.
2, 3——Not used in this set.
4, 5NCO—Not used in this set.
6OPENIFront panel open detection input
7CLOSEOFront panel close control output
8LINKOFFIBus interface link input
9NCO—Not used in this set.
10D SWIDown switch input (SW4)
11SSTPILimit switch input (SW3)
12, 13NCO—Not used in this set.
14, 15——Not used in this set.
16EMPH OODe-emphasis ON/OFF control output
17CDMONOCD mechanism deck power control output
18CD ONOCD power control output
19A MUTOSystem attenuate control output
20LD ONOLaser power ON/OFF control output
21CD RSTOCD system reset output
22HOLDOHold switch output
23AGC CONTOAGC control output
24——Not used in this set.
25PH3INot used in this set.
26TSTIN0INot used in this set.
27TSTIN1INot used in this set.
28TST.CLVINot used in this set.
29NCO—Not used in this set.
30RESETISystem reset input (“L”=Reset)
31X INIX’tal oscillator input from system clock. (10 MHz)
32X OUTOX’tal oscillator output for system clock. (10 MHz)
33GND—Analog ground
34XT OUTONot used in this set.
35XT ININot used in this set.
36AVSS—A/D converter ground
37AVREFIA/D converter reference voltage input
38TEP LINot used in this set.
39TEP HINot used in this set.
40SLED–ISled drive input
41PH2INot used in this set.
42SEK/SMETIFixed at “H” in this set.
43GFS/MNT2 SELIFixed at “H” in this set.
44SC-JIG ON/OFFIFixed at “H” in this set.
45SCLKOCD-TEXT data read clock output
46LOCKI/OLock signal input/output
47——Not used in this set.
48SCK2OSub Q read clock output
49SI2ISub Q 80 bit, PCM peak and level data 16 bit input.
50——Not used in this set.
51BUS CLKI/OBus system serial clock input/output
52BUS SIIBus system serial interface input
53BUS SOOBus system serial interface output
54F OKIFocus OK signal input
55GFSIGFS signal detection input
56TEST MODEIFixed at “H” in this set.
19
Pin No.Pin NameI/OPin Description
57SENSISENS signal input
58——Not used in this set.
59——Not used in this set.
60BU.INIBack-up power detection input
61BUSONIBus on control input
62IN SWIDisc in switch input (SW1)
63SELF SWISelf switch input (SW2)
64SCOROSub-code sync output
65CD-CKOOCD signal process serial clock input
66LM LODOLoading motor control output
67CD DATAOCD signal process serial data output
68CD-XLATOCD signal process serial data latch output
69LM-EJOLoading motor control output
70DRV-OEOFocus/tracking coil/sled motor control output
71MD2ODigital out ON/OFF control output (“L”: OFF, “H”: ON)
72VDD—Power supply pin
73NIHIFixed at “H” in this set.
74V/ZIFixed at “H” in this set.
75PH1INot used in this set.
76——Not used in this set.
77DOUT-SELIFixed at “H” in this set.
9E2P SIOI/OE2P SONY-BUS serial data input/output
10E2P CKOI/OE2P SONY-BUS serial clock input/output
11SYSRSTOSONY-BUS system reset output
12DOORSW (WRITE OUT)IDOOR OPEN/CLOSE detection input (“L”: CLOSE, “H”: OPEN)
13LCDSO (WRITE IN)OLCD serial data output
14LCDCKOOLCD serial clock output
15LCDCEOLCD chip enable output
16BEEPOBEEP output
17UNISIISONY-BUS serial data input
18UNISOOSONY-BUS serial data output
19UNICKOOSONY-BUS serial clock output
20UNICKIISONY-BUS serial clock input
21CD MDICD/MD select input (“L”: CD, “H”: MD) (Fixed at “L” in this set)
22FLASHWIFlash memory write mode detection input
23——Not used. (Open)
24SIRCSIRemote commander (infrared ray reception) input
25 – 28——Not used. (Open)
29DOORINDODOOR indicator output
30IFWIDTHONot used in this set.
31——Not used. (Open)
32NS MASKONoise mask output
33VSS—Ground
34C—Condenser connection pin of power stabilization.
35AD ONOPower control output for A/D converter.
98DIM SELI
99TAP CDITAPE/CD select input (“L”: CD, “H”: TAPE) (Fixed at “L” in this set)
100 – 118——Not used. (Open)
119VSS—Ground
120PW ONOSystem power control output
Illumination color switch input (“L”: 2 colors, “H”: 1 color) (Fixed at “L” in
CDX-C4900R/C5000R, “H” in CDX-C5000RX)
Dimmer select input (“L”: With dimmer select, “H”: Without dimmer select)
(Fixed at “L” in this set)
22
3-2. BLOCK DIAGRAM — CD SECTION —
CDX-C4900R/C5000R/C5000RX
PD
LD
TRACKING
04
OPTICAL PICKUP
KSS-720A
A
C
B
D
CONV.
E
F
FOCUS
COIL
COIL
I-V
M902
SLED
MOTOR
M901
SPINDLE
MOTOR
M903
LOADING
MOTOR
A
5
C
7
B
6
D
8
FOCUS
ERROR
E
11
TRACKING
F
ERROR
10
PD
4
LD
LD
DRIVE
Q101
TRACKING/FOCUS COIL DRIVE
SLED/SPINDLE/LOADING MOTOR DRIVE
10
11
12
13
AMP
LD
3
IC7
FOCUS
COIL
DRIVE
TRACKING
8
COIL
DRIVE
9
SLED
6
MOTOR
7
DRIVE
SPINDLE
MOTOR
DRIVE
LOADING
5
MOTOR
4
DRIVE
RF AMP, LD APC,
ERROR AMP
IC1
22
21
25
24
31
32
18
1
2
MUTE 1
34
MUTE 2
35
RFORFAC
RF
EQ
FE
TE
LD ON
HOLD SW
AGC CONT
16
14
13
22
21
20
DIGITAL SERVO,
DIGITAL SIGNAL PROCESSOR
IC501
(Page 24)
Q706
(Page 24)
B
SW503
(RESET)
TUNER
SECTION
SYSTEM CONTROL
58
12
20
19
17
18
3
11
77
90
86
13
BUS INTERFACE
103
132
12
9
8
8
IC501 (1/3)
ATT
DOOR SW
UNI CKI
UNI CKO
UNI SI
UNI SO
BUS ON
SYS RST
BU IN
RSTX
HSTX
IC652
RESET
BATT (H)
CHECK
Q701
IC701
BATT (L)
CHECK
RESET
RESET
DATA
CLK
1
6
4
BU 5V
BATT
BATT
Q705
• Signal path
SIRCS
8
6
3
5
2
4
1
7
CN701
BUS
CONTROL IN
C
DISPLAY
SECTION
(Page 25)
LOUT1
LOUT2
LOCK
SQSO
SQCK
SCOR
XRST
DATA
XLAT
SCLK
CLOK
SENS
XTALI
XTALO
MD2
GFS
FOK
92
95
34
6
7
24
73
11
13
14
17
15
16
22
32
86
87
11V REG
Q361
SW4
(LIMIT)
SW1
(DISC IN)
SW3
(LOAD IN)
SW2
(SELF)
RFDC
FE
TE
SE
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
MDP
CD 5V
CD 6V
EFM
DEM
SERVO
CTL
61
54
50
52
51
42
43
40
41
38
39
35
5V REG
Q364
D/A
I/F
DIGITAL
CLV
D/A
CONV.
SUB
CODE
PROCESS
POWER
CONT
Q365
6V REG
Q362
X2
16MHz
POWER
CONT
Q363
CD L
R-CH
BATT
TUNER
A
SECTION
CD SYSTEM CONTROL
LOCK
46
SI2
49
SCK2
48
SCOR
64
MD2
71
CD RST
21
CD DATA
67
CD XLAT
68
SCLK
45
CD CKO
65
SENS
57
GFS
55
FOK
54
SSTP
11
D SW
10
IN SW
64
SELF SW
63
LM EJ
69
LM LOD
66
SLED –
40
DRIVE ON
70
LD ON
20
HOLD
22
AGC CONT
23
CD ON
18
CDM ON
17
IC5
A MUT
OPEN
BUS CLK
BUS SI
BUS ON
RESET
BU IN
X IN
X OUT
BUS SO
LNK OFF
19
51
52
61
30
60
31
32
53
6
8
(KEY BOARD)
X1
10MHz
ATT
:CD
2323
CDX-C4900R/C5000R/C5000RX
3-3. BLOCK DIAGRAM — TUNER SECTION —
J1
(ANTENNA)
TUNER UNIT
TU1
ANTFMMPX
210
AM DET
ANTAM
1
IF AM
S-METER
I2C SDA
I2C SCL
RDS DET
CNJ151–1, –2
BUS AUDIO IN
–1
–2
L
R
ELECTRONIC VOLUME
IC151
A
CD
CDL
Q121
MUTE
RDS DECODER
IC51
8
Q111
MUTE
IC90
NOISE
DET
9
SECTION
MUTE
CONT
Q90
NOISE ON
10
MULTI
PATH
DET
RDS/RDBS
DEM/DEC
Q131
(Page 23)
8
19
BUFFER
Q1
51
14
12
13
SDASCA
LV IN
202
9
MPX
16
R-CH
FDILOUT LF
330
SEL
1
MPX
13
AM
11
AM IF
12
LEVEL
14
MPIN
15
SDA
20
SCL
21
SM
18
SYSTEM CONTROL
VOL ATT
57
TUN ATT
56
QUALITY
50
NS MASK
32
VSM
53
I2C SIO
70
I2C CKO
71
MPTH
52
DAVN
64
IC501 (2/3)
AMP MUTE
OUT LR
BEEP
AMP ON
TEL ATT
ACC IN
TEST IN
TU ON
PW ON
29
MUTE
16
59
60
79
82
81
1
120
Q181
MUTE
CONT
Q621, 622
CNJ151–3, –4
AUDIO OUT REAR
–3L–4
R
R-CH
Q171
MUTE
ATT
SECTION
(Page 23)
BATT
CNJ151–5, –6
AUDIO OUT FRONT
–5L–6
R
-CH
R
B
CD
ACC
CHECK
Q661
POWER SUPPLY
IC671
76
VCCAMP +B
2
3
4
8.7V ON
5.6V ON
STB
ANT +B
BU+BBU 5V
COM 8V
TU 5.6V
TU 8.7V
POWER AMP
12
11
AUX IN
16
STAND BY
4
MUTE
22
TEL
ATT
Q571
8
5
9
10
11
C5000R/C5000RX
IC611
5
3
9
8
BATT
COM 8V
TU 5.6V
TU 8.7V
R-CH
F901
CN601
1
9
2
10
4
12
3
11
16
13
7
15
5
6
FL+
FL–
RL+
RL–
FR+
FR–
RR+
RR–
BATT
C5000R/C5000RX
ATT
ACC
TEST
AMP R
ANT R
OSCOOSCI
45
FM AGC
E2PROM SDA
E2PROM SCL
04
4
17
18
X51
4.332MHz
51
9
10
FM AGC
E2P SIO
E2P CKO
• Signal path
:FM
:MW
:CD
2424
t
CDX-C4900R/C5000R/C5000RX
3-4. BLOCK DIAGRAM — DISPLAY SECTION —
KEY MATRIX
LSW901-917
S901-904
LSW801
KEY
ACTIVE
Q651
CD
SECTION
(Page 23)
C
04
J501
(REMOTE IN)
SIRCS
Q704
ACTIVE
IC951
RECEIVE
ROTARY
ENCODER
RE901
SW504
(NOSE DET)
KEY
Q652
IR
KEY ACT
X502
32.768kHz
SYSTEM CONTROL
IC501 (3/3)
KEY IN0DATA
4613
KEY IN1
KEY ACK
76
AD ON
35
RC IN1
85
RC IN0
48
SIRCS
24
RE IN0
36
RE IN1
37
NOSE SW
67
XOA
73
XIA
74
LCD SO
LCD CKO
LCD CE
DOOR IND
ILL ON
14
1547
DOOR IND
29
POWER
7
BATT
XO
92
XI
3.68MHz
93
LCD DRIVE
IC901
64
CL
63
CE
62
GREEN
2
AMBER
1
C4900R/
C5000R
DRIVE
Q551
LED801-803 LED910-915LSW901-917
CONT
Q633
X501
+10V REG
Q631
ILL +B
LCD901
AMBER
DRIVE
Q901
LED901-904
GREEN
DRIVE
Q902
3-5. CIRCUIT BOARDS LOCATION
DISC IN SW board
SUB (CD) board
LOAD SW board
KEY board
SUB board
LIMIT SW board
tuner uni
(TU1)
MAIN board
SERVO board
2525
CDX-C4900R/C5000R/C5000RX
THIS NOTE IS COMMON FOR PRINTED WIRING
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is
printed in each block.)
for schematic diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ω and 1/
specified.
•%: indicates tolerance.
f
•
• C : panel designation.
Note: The components identified by mark 0 or dotted line
• U : B+ Line.
• Power voltage is dc 14.4V and fed with regulated dc power
• Voltages are tak en with a V OM (Input impedance 10 MΩ).
• Waveforms are taken with a oscilloscope.
• Circled numbers refer to waveforms.
• Signal path.
: internal component.
with mark 0 are critical for safety.
Replace only with part number specified.
supply from ACC and BATT cords.
Voltage variations may be noted due to normal produc-
tion tolerances.
Voltage variations may be noted due to normal produc-
tion tolerances.
F: FM
f: MW
J: CD
4
W or less unless otherwise
3-6. PRINTED WIRING BOARDS — CD MECHANISM SECTION —
for printed wiring boards:
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
•x: parts mounted on the conductor side.
a
•
• b : Pattern from the side which enables seeing.
Caution:
Pattern face side: Parts on the pattern face side seen from the
(Side B)pattern face are indicated.
Parts face side: Parts on the parts face side seen from the
(Side A)parts face are indicated.
: Through hole.
(The other layer’s patterns are not indicated.)
2626
(Page 31)
CDX-C4900R/C5000R/C5000RX
• Semiconductor
Location
Ref. No. Location
IC1C-1
IC5C-6
IC7F-2
IC501F-5
Q101B-2
2727
CDX-C4900R/C5000R/C5000RX
3-7. SCHEMATIC DIAGRAM — CD MECHANISM SECTION (1/2) — • Refer to page 39 for IC Block Diagrams.
(Page 29)
• Waveforms (MODE:PLAY)
1
0V
Approx. 200mVp-p
qd
(TE)
IC1
2
0V
Approx. 620mVp-p
qf
(FE)
IC1
3
1.2Vp-p
qh
(RFO)
IC1
(Page 33)
Note:
• Voltage and waveforms are dc
with respect to ground
under no-signal conditions.
no mark : CD PLAY
(Page 29)
2828
3-8. SCHEMATIC DIAGRAM — CD MECHANISM SECTION (2/2) — • Refer to page 40 for IC Block Diagrams.
CDX-C4900R/C5000R/C5000RX
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Note:
• Voltage is dc with respect to ground under no-signal
conditions.
no mark : CD PLAY