SONY CDX-525RF Service Manual

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Page 1

CDX-525RF

SERVICE MANUAL

SPECIFICATIONS

US Model

Canadian Model

AEP Model

UK Model

E Model

Model Name Using Similar Mechanism CDX-505RF CD Drive Mechanism Type MG-250C-137 Optical Pick-up Name KSS-521A/J2N

MICROFILM

COMPACT DISC CHANGER SYSTEM

Page 2

7-3. SCHEMATIC DIAGRAM – RF Section – • See page 33 for Waveforms. • See page 34 for IC Block Diagrams.

CDX-525RF

(Page 29)

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The components identified by mark ! or dotted line with mark ! are critical for safety. Replace only with part number specified.

– 24 –

Les composants identifiés par une marque ! sont critiques pour la sécurité. Ne les remplacer que par une piéce portant le numéro spécifié.

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CDX-525RF

7-6. SCHEMATIC DIAGRAM – MAIN Section (1/2) – • See page 33 for Waveforms. • See page 35 for IC Block Diagrams.

(Page 24)

– 29 –

– 30 –

Page 4

7-7. SCHEMATIC DIAGRAM – MAIN Section (2/2) – • See page 33 for Waveforms. • See page 35 for IC Block Diagrams.

CDX-525RF

– 31 –

– 32 –

Page 5

• Waveforms

7.3 Vp-p

22.7

– RF Board –

– MAIN Board (1/2) –

– MAIN Board (2/2) –

1 IC11 #£ (RF O)

500 mV/DIV, 500 ns/DIV

2 IC11 2 (FEI)

50 mV/DIV, 1 µs/DIV

3 IC11 $¶ (TEI)

200 mV/DIV, 500 µs/DIV

1.4 Vp-p

Approx. 110 mVp-p

1 IC101 @¶ (MDP)

2 IC101 %º (LRCK)

22.7

3 IC101 %¢ (BCK)

7.6

6 IC401 !£ (MCK)

2.5 Vp-p

6 Vp-p

7 IC401 !§ (XO)

6 Vp-p

8 IC401 @£ (BCK)

59.5 ns

58.6

5.8 Vp-p

Approx. 280 mVp-p

4 IC101 *ª (XTAI)

472 ns

59.2 ns

5 IC302 #¡ (EXTAL)

6.2 Vp-p

6 Vp-p

3.8 Vp-p

7.6 Vp-p

472 ns

9 IC401 @¢ (LRCK)

124 ns

– 33 –

Page 6

• IC Block Diagrams – RF Board –

IC11 CXA1992BR

BIAS

VEE TEO

LPFI

ATSC

TZC

TDFCT

FZC

RF O

33 32

TZC

RF I

FOCUS OK

COMPARATOR

PEAK/BOTTOM

HOLD

PEAK/BOTTOM

HOLD

FOL

FOH

IIC DATA REGISTER, INPUT SHIFT REGISTER,

ADDRESS DECODER, SENSE SELECTOR,

FZC

DFCTO

IFB1 – IFB6

CENTER

VOLTAGE

GENERATOR

VCC

FS1

COMPARATOR

LDON

LPCL

OUTPUT DECODER

FS1 – FS4

BAL1 – BAL4

TOG1 – TOG4

VCC

VEE

LPC

MIRR

TGFL

TG1 – TG2

TM7

TG2

IFB1 – IFB6

DFCT

PD1

PD 1

I-V AMP

TGFL

VEE

TOG1 – TOG4

TM1

FS4

PD2

PD 2

I-V AMP

VCC

VEE

TEI

F I-V

AMP

E I-V

AMP

43 44 45

BAL1 – BAL4

46 47 48

DFCT

36 34 31 30 29 28 27

AMP

LASER

POWER

CONTROL

FOCUS ERROR

AMP

TRACKING GAIN

WINDOW

COMPARATOR

E-F BALANCE

WINDOW

COMPARATOR

ATSC

WINDOW

COMPARATOR

TZC

COMPARATOR

FOCUS PHASE

COMPENSATION

RFTC

TG1

RF M

RF SUMMING

AMP

FOCUS BIAS

WINDOW

COMPARATOR

TGH

TGL BALH BALL

ATSC

TRACKING PHASE

COMPENSATION

FZC

COMPARATOR

CHARGE UP

FS2

DEFECT

AMP

TM1 – TM7

FSET

CC1

CC2

TTL

MIRR

VCC

PS1 – PS4

TM5

VEE

IIL

↓

TM4

TM3

FOK

DFCT1

TM6

VCC

CC1

↓

TTL

↓

IIL

VCC

ISET

– +

TM2

–

SENS1

C. OUT

XRST

DATA

22 21

XLT CLK

20 19

LOCK

VCC

ISET

SL O

SL M

SL P

SENS2

IIL

1 2 3

FEI

FEO

FDFCT

FLB

FGD

FE O

FE M

8 9 10

SRCH

VEE

TGU

11 12 13

TG2

FSET

VEE

TA M

TA O

– 34 –

Page 7

IC52 BA6287F

OUT1

TSD

VCC

POWER

SAVE

FIN

– MAIN Board –

DRIVER DRIVER

CONTROL LOGIC

GND

OUT2

VREF

RIN

IC101 CXD2530Q

TES6

VDD

VSS

79 78

81 82

VSS VDD

84 85

TES7

VSS

XVDD

XTAI

XTAO

90 91

XVSS

VSS

TES8

VDD

96 97

VSS

NC NC

XRST

99 100

1 234

VSS

VDD

TIMING

LOGIC

56789 10

TES2

LMUT

RMUT

EXCK

76 75 74

CKOUT

SBSO

SCOR

DEMODULATOR

PROCESSOR

CPU

INTERFACE

SQCK

SQSO

WFCK

TES5

73 72

EFM

SUB CODE

SENS

DATA

EMPH

12 13

XLAT

CLOK

SEIN

DOUT

C4M

69 68

15 16 17

CNIN

DATO

FSTT

XTSL

CORRECTOR

SERVO

AUTO

SEQUENCER

18 19 20

XLTO

CLKO

MNT0

MNT1

66 65 64

ERROR

16K RAM

SPOB

SPOA

MNT3

SPOC

XROF

63 62 61

22 23

XLON

SPOD

C2PO

RFCK

INTERFACE

DIGITAL OUT

FOK

VDD

GFS

XPCK

59 58

D / A

DIGITAL CLV

25 26 27

VSS

MON

XUGF

MDP

GTOP

VDD

56 55 54

28 29 30

MDS

LOCK

VSS

TES4

PWMI

BCK

TES3

PCMD

53 52 51

ASYMMETRY

CORRECTOR

DIGITAL

PLL

OSC

CLOCK

GENERATOR

TES9

LRCK

50 49

WDCK

ASYE

ASYO ASYI

BIAS

AVDD

43 42

CLTV AVSS

41 40

FILI

FILO PCO

VCTL

V16M

36 35

VCKI

VPCO1

VPCO2

TES1

TES0

– 35 –

Page 8

IC204 BA8272F-E2

IC301 BA6287F

VCC

BUS ON

LINK OFF

CLK OUT

DATA OUT

2 3

BUS ON OUT

BUS ON IN

5 6 7

GND

BUS CLK

VREF

BUS DATA

IC401 TC9464FN-EL

LRCK

BCK

DATA

(SM)

20 19 18 17 16 15 14 13

21222324

ATT

(EMP)

DATA IN

(BS)

RESET

891014 13 12 11

RESET

SWITCH

BUS RESET

VDXXOXI

GNDX

MCK

OUT1

VCC

FIN

DRIVER DRIVER

TSD

POWER

SAVE

CONTROL LOGIC

GND

OUT2

VREF

RIN

INTERFACE

CIRCUIT

DIGITAL FILTER CIRCUIT

ATTENUATOR OPERATIONAL CIRCUIT

DEEMPHASIS FILTER CIRCUIT

D-∆ MODULATION CIRCUIT

TEST

CIRCUIT

2 3

VDD

MICROCOMPUTER

INTERFACE

CIRCUIT

OUTPUT CIRCUIT

ANALOG

FILTER

5 6 7 8 9 10

P/S

VDA

GNDA

OSC

TIMING

GENERATOR

OUTPUT CIRCUIT

ANALOG

FILTER

GNDA

1211

VDA

GNDD

– 36 –

Page 9

7-8. IC PIN FUNCTION DESCRIPTION

• MAIN BOARD IC302 CXP84124-080Q (SYSTEM CONTROLLER)

Pin No. Pin Name I/O Function

1 LIM.SW I

2 BUSON I Bus on/off control signal input from the SONY bus interface (IC204) “H”: bus on 3 EJECT I Eject switch (SW303) input terminal “H” active

4 LOAD1 I

5 LOAD2 I

6 A.MUTE O Audio line muting on/off control signal output terminal “H”: muting on 7 EMPH O Emphasis mode output to the D/A converter (IC401) “L”: emphasis on

8 CH.R O

9 CH.F O

10 — O Not used (open)

11 ELV.R O

12 ELV.ON O Mechanism deck section power supply on/off control signal output “H”: power on 13 CD RST O System reset signal output to the CXA1992BR (IC11) and CXD2530Q (IC101) “L”: reset 14 CDON O D/A converter and servo section power supply on/off control signal output “H”: power on

15 to 23 — O Not used (open)

24 AUTO ON/OFF I

25 to 29 — O Not used (open)

30 RESET I

31 EXTAL I Main system clock input terminal (8 MHz) 32 XTAL O Main system clock output terminal (8 MHz) 33 VSS — Ground terminal 34 TX O Sub system clock output terminal Not used (open) 35 TEX I Sub system clock input terminal Not used (fixed at “L”) 36 AVSS — Ground terminal (for A/D converter) 37 AVREF I Reference voltage (+5V) input terminal (for A/D converter) 38 ATRIBT I Selection input of the custom file, D-BASS, etc.

39 MCK I

40 EHS I Elevator height position detect input from the RV302 (elevator height sensor) (A/D input)

41 to 47 — O Not used (open)

48 SCK I Serial data transfer clock signal input from the SONY bus interface (IC204) 49 SI I Serial data input from the SONY bus interface (IC204) 50 SO O Serial data output to the SONY bus interface (IC204) 51 SQCLK O Subcode Q data reading clock signal output to the CXD2530Q (IC101) 52 SUBQ I Subcode Q data input from the CXD2530Q (IC101) 53 — O Not used (open) 54 — I Not used (fixed at “H”)

55 MGLK I

Sled limit in detect switch (SW1) input terminal “L”: When the optical pick-up is inner position

Save end detect switch (SW12) input terminal “L”: When completion of the disc chucking operation

Chucking end detect switch (SW11) input terminal “L”: When completion of the disc chucking operation

Motor drive signal (save direction) output to the chucking motor drive (IC52) “H” active *1

Motor drive signal (load chucking direction) output to the chucking motor drive (IC52) “H” active *1

Motor drive signal (elevator down direction) output to the elevator motor drive (IC301) “L” active *2

Setting terminal for the automatic adjustment “L”: automatic adjustment, “H”: manual adjustment (fixed at “L” in this set)

System reset signal input from the reset signal generator (IC202) and SONY bus interface (IC204) “L”: reset For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”

Input of signal for the fine adjustment (linear position sensor adjustment; RV301) of elevator position (A/D input)

Magazine eject operation completion detect switch (SW301) input terminal “L”: eject completed

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Page 10

Pin No. Pin Name I/O Function

56 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101) 57 SENS2 I Internal status signal (sense signal) input from the CXA1992BR (IC11)

58 PWM O

59 — O Not used (open) 60 MAG.SW I Magazine in/out detect switch (SW302) input terminal “L”: magazine detected 61 BUCHECK I 62 W.UP I Bus on or eject switch (SW303) input terminal “H”: bus on or eject switch pushing 63 C.OUT I Track number count signal input from the CXA1992BR (IC11) 64 EEDATA I/O Two-way data bus with the EEPROM Not used (open) 65 EECLK O Serial clock signal output to the EEPROM Not used (open) 66 EEINIT I Initialize signal input for the EEPROM “H”: format Fixed at “L” in this set 67 — O Not used (open)

68 SINGLE I

69 FOK I Focus OK signal input from the CXA1992BR (IC11) “L”: NG, “H”: OK 70 GFS I Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK 71 SENS1 I Internal status signal (sense signal) input from the CXD2530Q (IC101) 72 VDD — Power supply terminal (+5V) 73 NC (VDD) — Connected to the power supply (+5V) 74 CDCLK O Serial data transfer clock signal output to the CXD2530Q (IC101) 75 CDXLT O Serial data latch pulse signal output to the CXD2530Q (IC101) 76 CDDATA O Serial data output to the CXD2530Q (IC101)

77 to 80 — O Not used (open)

Motor drive signal (elevator up direction) output to the elevator motor drive (IC301) “L” active *2

Battery detection signal input terminal “H”: battery on

Setting terminal for the single disc/multiple discs mode “L”: single mode, “H”: multiple discs mode (fixed at “H”)

*1 chucking motor (M103) control

Mod

Terminal

CH.F (pin 9) “L” “H” “L” “H” CH.R (pin 8) “L” “L” “H” “H”

*2 elevator motor (M104) control

Mod

Terminal

PWM (pin %•) “H” “L” “H” “L”

ELV.R (pin !¡) “H” “H” “L” “L”

STOP

LOAD

CHUCKING

ELEVATORUPELEVATOR

SAVE BRAKE

DOWN

BRAKE

– 38 –

SONY CDX-525RF Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual