Siemens SLA24C164-D-3-P, SLA24C164-D-P, SLA24C164-S-3-P, SLA24C164-S-P, SLE24C164-D-P Datasheet

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Standard EEPROM ICs

SLx 24C164/P 16 Kbit (2048 × 8bit)

Serial CMOS-EEPROM with

C Synchronous 2-Wire Bus

and Page Protection Mode

Data Sheet 1998-07-27

™

SLx 24C164/P Revision History: Current Version: 1998-07-27

Previous Version: 06.97 Page

(in previous Version)

Page (in current Version)

Subjects (major changes since last revision)

3 3 Text was changed to “Typical programming time 5 ms for up to

16 bytes”. 55WP= 11, 12 11, 12 The erase/write cycle is finished latest after 10

protects the upper half entire memory.

8ms. 15 15 Figure 11: second command byte is a CSR and not CSW. 21 21 The write or erase cycle is finished latest after 10

4ms. 19 24 “Capacitive l oad …” were added. 25 25 Some timings were changed. 25 25 The line “erase/write cycle” was removed. 25 25 Chapter 8.4 “Erase and Write Characteristics” has been added.

I2CBus

Purchase of Siemens I

C system p rovided the system conforms to the I2C specifications defined by Philips.

the I

C components conveys the license under the Philips I2C patent to use the components in

Edition 1998-07-27 Published by Siemens AG,

Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG 1998.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. B y agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For pa cking material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components written appr oval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2with the express

16 Kbit (2048 × 8bit)SerialCMOS

EEPROMs, I Page Protection Mode

Features

• Data EEPROM internally organized as

2048 bytes and 128 pages × 16 bytes

• Page protection mode, flexible page-by-page hardware write protection

– Additional protection EEPROM of 128 bits, 1 bit

per data page

– Protection setting for each data page by writing its

protection bit

– Protection managementwithoutswitching WPpin

• Low power CMOS

C Synchronous 2-Wire Bus,

™

SLx 24C164/P

P-DIP-8-4

•

• Two wire serial interface bus, I

= 2.7 to 5.5 V operation

C-Bus

compatible

• Three chip select pins to address 8 devices

• Filtered inputs for noise suppression with Schmitt trigger

P-DSO-8-3

• Clock frequency up to 400 kHz

• High programming flexibility

– Internal programming voltage – Self timed programming cycle including erase – Byte-write and page-write programming, between 1 and 16 bytes – Typical programming time 5 ms for up to 16 bytes

• High reliability

– Endurance 10

cycles

– Data retention 40 years

– ESD protection 4000 V on all pins

• 8 pin DIP/DSO packages

• Available for extended temperature ranges

– Industrial: − 40 °C to + 85 °C – Automotive: − 40°C to + 125 °C

Values are temperature dependent, for further information please refer to your Siemens Sales office.

Semiconductor Group 3 1998-07-27

SLx 24C164/P

Ordering Information Type Ordering Code Package Temperature Voltage

SLA 24C164-D/P Q67100-H3504 P-DIP-8-4 – 40 °C … + 85 °C 4.5 V...5.5 V SLA 24C164-S/P Q67100-H3499 P-DSO-8-3 – 40 °C … + 85 °C 4.5 V...5.5 V SLA 24C164-D-3/P Q67100-H3502 P-DIP-8-4 – 40 °C … + 85 °C 2.7 V...5.5 V SLA 24C164-S-3/P Q67100-H3498 P-DSO-8-3 – 40 °C … + 85 °C 2.7 V...5.5 V SLE 24C164-D/P Q67100-H3503 P-DIP-8-4 – 40°C … + 125 °C 4.5 V...5.5 V SLE 24C164-S/P Q67100-H3497 P-DSO-8-3 – 40°C … + 125 °C 4.5 V...5.5 V

Other types are available on request

– Temperature range (– 55 °C … + 150 °C) – Package (die, wafer delivery)

1 Pin Configuration

P-DSO-8-3

CS0

CS1

CS2

1 2 3 4

IEP02124

CS0

CS1

CS2

P-DIP-8-4

IEP02125

WP SCL63

SDA54

Figure 1 Pin Configuration (top view)

Pin Definitions and Functions Table 1 Pin No. Symbol Function

1, 2, 3 CS0, CS1, CS2 Chip select inputs

SCL SDA

Ground 5 SDA Serial bidirectional data bus 6 SCL Serial clock input 7 WP Write protection input 8

Semiconductor Group 4 1998-07-27

Supply voltage

SLx 24C164/P

Pin Description

Serial Clock (SCL)

The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. The output is open drain, performing a wired AND function with any number of other open drain or open collector devices. The SDA

bus requires a pull-up resistor to

Chip Select (CS0, CS1, CS2)

The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven

or VSS. These inputs allow the selection of one of eight possible devices sharing

acommonbus.

Write Protection (WP)

WP switched to WP switched to

allows normal read/write operations.

protects the entire EEPROM against changes (hardware write

protection). Additionally write protection is managed by a protection bit associated to each page.

(refer to chapter 7 Page Protection Mode

)

Semiconductor Group 5 1998-07-27

2 Description

SLx 24C164/P

The SLx 24C164/P device is a serial e

emory (EEPROM), organized as 2048 × 8 bit. The data memory is divided into

lectrically erasable and programmable read only

128 pages. The 16 bytes of a page can be programmed simultaneously. Each page may be protected individually against changes by its associated protection bit.

The device conforms to the specification of the 2-wire serial I

pins allow the addressing of 8 devices on the I

C-Bus. Low voltage design permits

C-Bus. Three chip select

operation down to 2.7 V with low active and standby currents. All devices have a

minimum endurance of 10

erase/write cycles.

The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at

2.7 ... 4.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V

type ( applications and as 3 V type (

= 4.5 … 5.5 V) with two temperature ranges for industrial and automotive

= 2.7 … 5.5 V) for industrial applications. The

EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.

CS0 CS1 CS2

SCL

SDA

Start/

Stop

Logic

Chip Address

Control

Logic

Serial

Control

Logic

Address

Logic

Programming

Control

H.V. Pump

EEPROM

DEC

Page Logic

Dout/ACK

Page

Prot. Bit

EEPROM

Y DEC

IEB02271

Figure 2 Block Diagram

Semiconductor Group 6 1998-07-27

SLx 24C164/P

3 I2C-Bus Characteristics

The SLx 24C164/P devices support a master/slave bidirectional bus oriented protocol in which the EEPROM always takes the role of a slave.

Slave 1 Slave 2 Slave 3 Slave 4

SCL

Master

SDA

Slave 8Slave 5 Slave 6 Slave 7

IES02183

Figure 3 Bus Configuration

Master Device that initiates the transfer of data and provides the clock for both

transmit and receive operations.

Slave Device addressed by the master, capable of receiving and transmitting

data.

Transmitter The device with the SDA as output is defined as the transmitter. Due to

the open drain characteristic of the SDA output the device applying a low level wins.

Receiver The device with the SDA as input is defined as the receiver.

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SLx 24C164/P

The conventions for the serial clock line and the bidirectional data line are shown in figure 4.

SCL

SDA

START Condition Data allowed STOP Condition

to Change

Acknowledge

ACK ACK

IED02128

Figure 4

C-Bus Timing Conventions for START Condition, STOP Condition, Data Valida-

tion and Transfer of Acknowledge ACK

Standby Mode in which the bus is not busy (no serial transmission, no

programming): both clock (SCL) and data line (SDA) are in high state. The device enters the standby mode after a STOP condition or after a programming cycle.

START Condition High to low transition of SDA when SCL is high, preceding all

commands.

STOP Condition Low to high transition of SDA when SCL is high, terminating all

communications. A STOP condition initiates an EEPROM programming cycle. A STOP condition after reading a data byte from the EEPROM initiates the Standby mode.

Acknowledge A successful reception of eight data bits is indicated by the

receiver by pulling down the SDA line during the following clock cycle of SCL (ACK). The transmitter on the other hand has to release the SDA line after the transmission of eight data bits. The EEPROM as the receiving device responds with an acknowledge, when addressed. The master, on the other side, acknowledges each data byte transmitted by the EEPROM and can at any time end a read operation by releasing the SDA line (no ACK) followed by a STOP condition.

Data Transfer Data must change only during low SCL state, data remains valid

on the SDA bus during high SCL state. Nine clock pulses are required to transfer one data byte, the most significant bit (MSB) is transmitted first.

Semiconductor Group 8 1998-07-27

SLx 24C164/P

4 Device Addressing and EEPROM Addressing

After a START condition, the master always transmits a Command Byte CSW or CSR. After the acknowledge of the EEPROM a Control Byte follows, its content and the transmitter depend on the previous Command Byte. The description of the Command and Control Bytes is shown in table 2.

Command Byte Selects one of the 8 addressable devices: the chip select bits c2,

and c0 (bit positions b6 to b4) are compared to their

c1 corresponding hard wired input pins CS2, CS1 and CS0, respectively (c1

Selects operation: the least significant bit b0 is low for a write operation (C read operation (C

Contains address information: in the CSW Command Byte, the bit positions b3 to b1 are decoded for the three uppermost EEPROM address bits A10, A9, A8 (in the CSR Command Byte, the bit positions b3 to b1 are left undefined).

is the complement of CS1 pin).

hip Select Write Command Byte CSW) or set high for a

hip Select Read Command Byte CSR).

Control Byte Following CSW (b0 = 0): contains the eight lower bits of the

EEPROM address (EEA) bit A7 to A0, or an additional command byte for the handling of the protection bit.

Following CSR (b0 = 1): contains the data read out, transmitted by the EEPROM. The EEPROM data are read as long as the master pulls down SDA after each byte in order to acknowledge the transfer. The read operation is stopped by the master by releasing SDA (no acknowledge is applied) followed by a STOP condition.

Table 2

Command and Control Byte for I

C-Bus Addressing of Chip and EEPROM

Definition Function

b7 b6 b5 b4 b3 b2 b1 b0

CSW 1 c2 c1 CSR 1 c2 c1

c0A10A9A80 ChipSelectforWrite c0 x x x 1 Chip Select for Read

EEA A7 A6 A5 A4 A3 A2 A1 A0 EEPROM address The device has an internal address counter which points to the current EEPROM

address. The address counter is incremented

– after a data byte to be written has been acknowledged, during entry of further data

byte

– during a byte read, thus the address counter points to the following address after

reading a data byte.

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SLx 24C164/P

The timing conventions for read and write operations are described in figures 5 and 6.

Command Byte (CSW) Data Transfer to EEPROM

SCL

SDA

1234

c2 c1

A10 A9 A8

START from Master Acknowledge from EEPROMAcknowledge from EEPROM

Figure 5 Timing of the Command Byte CSW

Command Byte (CSR) Data Transfer from EEPROM

SCL

SDA

1234

XXX

ACK

11 12

A6 A5

11 12

15 16

A2 A1

15 16

ACK

IED02184

ACK

START from Master Acknowledge from MasterAcknowledge from EEPROM

Figure 6 Timing of the Command Byte CSR

IED02275

Semiconductor Group 10 1998-07-27

SLx 24C164/P

5 Write Operations

Changing of the EEPROM data is initiated by the master with the command byte CSW. Depending on the state of the Write Protection pin WP and of the Protection Bits (refer

to chapter 7 Page Protection Mode (Page Write) are modified in one programming procedure.

5.1 Byte Write Address Setting After a START condition the master transmits the Chip Select

Write byte CSW. The EEPROM acknowledges the CSW byte during the ninth clock cycle. The following byte with the EEPROM address (A0 to A7) is loaded into the address counter of the EEPROM and acknowledged by the EEPROM.

Transmission of Data Finally the master transmits the data byte which is also

acknowledged by the EEPROM into the internal buffer.

) either one byte (Byte Write) or up to 16 byte

Programming Cycle Then the master applies a STOP condition which starts the

internal programming procedure. The data bytes are written in the memory location addressed in the EEA byte (A0 to A7) and the CSW byte (A8 to A10). The programming procedure consists of an internally timed erase/write cycle. In the first step, the selected byte is erased to “1”. With the next internal step, the addressed byte is written according to the contents of the buffer.

Master

SDA Line

Bus Activity EEPROM

T A

Command Byte

R T

CSW

EEPROM Address

EEA

A C K

Data ByteBus Activity

S T O P

A C K

IED02129

Figure 7 Byte Write Sequence

The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3 Acknowledge Polling).

Semiconductor Group 11 1998-07-27

SLx 24C164/P

5.2 Page Write Address Setting Thepagewriteprocedureisthesameasthebytewrite

procedure up to the first data byte. In a page write instruction however, entry of the EEPROM address byte EEA is followed by a sequence of one to maximum sixteen data bytes with the new data to be programmed. These bytes are transferred to the internal page buffer of the EEPROM.

Transmission of Data The first entered data byte will be stored according to the

EEPROM address n given by EEA (A0 to A7) and CSW (A8 to A10). The internal address counter is incremented automatically after the entered data byte has been acknowledged. The next data byte is then stored at the next higher EEPROM address. EEPROM addresses within the same page have common page address bits A4 through A10. Only the respective four least significant address bits A0 through A3 are incremented, as all data bytes to be programmed simultaneously have to be within the same page.

Programming Cycle The master stops data entry by applying a STOP condition,

which also starts the internally timed erase/write cycle. In the first step, all selected bytes are erased to “1”. With the next internal step, the addressed bytes are written according to the contents of the page buffer.

Those bytes of the page that have not been addressed are not included in the programming.

Master

SDA Line

Bus Activity EEPROM

T A

Command Byte

T S

CSW

EEPROM Address

EEA n

A C K

Data Byte n Data Byte n+1 Data Byte n+15Bus Activity

A C K

S T O P

A C K

IED02140

Figure 8 Page Write Sequence

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SLx 24C164/P

5.3 Acknowledge Polling

During the erase/write cycle the EEPROM will not respond to a new command byte until the internal write procedure is completed. At the end of active programming the chip returns to the standby mode and the last entered EEPROM byte remains addressed by the address counter. To determine the end of the internal erase/write cycle acknowledge polling can be initiated by the master by sending a START condition followed by a command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/ write cycle is not completed, the device will not acknowledge the transmission. If the internal erase/write cycle is completed, the device acknowledges the received command byte and the protocol activities can continue.

Internal Programming

Procedure

Send CS-Byte

Acknowledge

from EEPROM

Next Operation

Figure 9 Flow Chart “Acknowledge Polling”

Send Start

received?

Yes

IED02131

Semiconductor Group 13 1998-07-27

STOP from Master initiates erase/write cycle

START from Master

CSR

SLx 24C164/P

CSR

SDA

STOP from Master initiates erase/write cycle

START from Master

CSW

Figure 10 Principle of Acknowledge Polling

Acknowledge of EEPROM indicates complete erase/ write cycle

S S

Acknowledge of EEPROM indicates complete erase/ write cycle

e.g. STOP condition

CSW

IED02166

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SLx 24C164/P

6 Read Operations

Reading of the EEPROM data is initiated by the Master with the command byte CSR.

6.1 Random Read

Random read operations allow the master to access any memory location. Address Setting The master generates a START condition followed by the

command byte CSW. The receipt of the CSW-byte is acknowledged by the EEPROM with a low on the SDA line. Now the master transmits the EEPROM address (EEA) to the EEPROM and the internal address counter is loaded with the desired address.

Transmission of CSR After the acknowledge for the EEPROM address is received,

the master generates a START condition, which terminates the initiated write operation. Then the master transmits the command byte CSR for read, which is acknowledged by the EEPROM.

Transmission of EEPROM Data

STOP Condition from Master

S T

Bus Activity Master

SDA Line

Bus Activity EEPROM

Command Byte

T S

Figure 11 Random Read

During the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter.

During the following clock cycle the masters releases the bus and then transmits the STOP condition.

P P

IED02133

CSW

EEPROM Address

EEA n

A C K

T A

Command Byte

R T

A C K

CSR

A C K

Data Byte

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SLx 24C164/P

6.2 Current Address Read

The EEPROM content is read without setting an EEPROM address, in this case the current content of the address counter will be used (e.g. to continue a previous read operation after the Master has served an interrupt).

Transmission of CSR For a current address read the master generates a START

condition, which is followed by the command byte CSR (c

elect read). The receipt of the CSR-byte is acknowledged by

s the EEPROM with a low on the SDA line.

hip

Transmission of EEPROM Data

STOP Condition from Master

Bus Activity Master

SDA Line

Bus Activity EEPROM

Figure 12 Current Address Read

During the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter.

During the following clock cycle the masters releases the bus and then transmits the STOP condition.

S T A

Command Byte

T S

CSR

A C K

Data Byte

S T O P

IED02132

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SLx 24C164/P

6.3 Sequential Read

A sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM then continues the data transmission. The internal address counter is incremented by one during each data byte transmission.

A sequential read allows the entire memory to be read during one read operation. After the highest addressable memory location is reached, the internal address pointer “rolls over” to the address 0 and the sequential read continues.

The transmission is terminated by the master by releasing the SDA line (no acknowledge) and generating a STOP condition (see figure 13).

Bus Activity Master

T A

Command Byte

R T

CSW

A C K

S T

SDA Line

Bus Activity EEPROM

Figure 13 Sequential Read

A C

C K

Data Byte n

Data Byte n+xData Byte n+1

IED02134

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SLx 24C164/P

7 Page Protection Mode

Each page (16 byte) in the Data Memory can be protected against unintended data changes by an associated protection bit. The protection bit memory consists of an additional EEPROM of 128 bit (figure 14).

Data in the Data Memory can be modified only if the assigned protection bit is erased (logicalstate“1”).Afterwritingthedatabytestoapage,theprotectionisachievedby writing the associated protection bit (logical state “0”). Further changes in the data in a protected page is possible only after erasing the protection bit.

Data Memory Area

15. . .

0 1 2 3

. . ..

Protection Bit Memory Area

IED02272

Page 0

Page 1 Page 2 Page 3

. .

Page n

1023

. . .

Byte Bit

Figure 14 Data Page and Assigned Protection Memory

A special procedure to write or erase a protection bit guarantees proper activation or deactivation respectively of page protection. For protection bit write or erase, all 16 data bytes of the respective page have to be entered for a second time. The data then are compared internally with the data to be protected, and in case of identity the protection bit is written or erased respectively.

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SLx 24C164/P

7.1 Protection Bit Handling

The bits of the protection memory can be addressed directly for reading or programming. A protection bit address corresponds to the lowest address within the respective page (A4 to A10, A0 to A3 = zero). The status of each protection bit is sensed internally. A written state (“0”) prevents programming in the associated page. If an already protected memory page is accidentally addressed for programming, the programming procedure is suppressed.

The conventional I Therefore an independent instruction sequence for addressing and manipulation of protection bits is implemented. For protection bit instructions, the command byte CSW with its preceding START condition followed by the associated control byte has to be entered twice (figures 15 through 17).ThefirstcommandbyteCSW(withA8toA10)is followed by the control byte EEA with the bit/page address A0 through A3 always at zero. The second CSW is required for entering a control byte CTx for protection bit manipulation. The three control bytes for read, write or erase of a protection bit are listed below (table 3):

C-Bus protocol allows data bytes to be read and programmed only.

Table 3 Control Byte for Protection Bit Manipulation

Address Name

b7 b6 b5 b4 b3 b2 b1 b0

Definition Function

CTR xxxxxx00Protectionbitread CTW xxxxxx01Protectionbitwrite CTE xxxxxx11Protectionbiterase

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SLx 24C164/P

7.2 Protection Bit Write and Erase

For writing or erasing a protection bit, the data of the respective page have to be known by the master. The data of the page are not affected by the write or erase procedure of

the protection bit. The I figure 16 for protection bit erase.

C-Busprotocolisshowninfigure 15 for protection bit write and

Bus Activity Master

SDA Line

Bus Activity EEPROM

Command

Byte

CSW

T S

EEPROM

Address

EEA n

A C K

S T A

T S

A C K

Figure 15 Sequence for Protection Bit Write

S T A

Bus Activity Master

S T

Command

Byte

CSW

EEPROM

Address

EEA n

Command

Byte

CSW

Command

Byte

CSW

A C K

Control

Byte

CTW

Control

Byte CTE

Data

Byte n

0000000

A C K

Data

Byte n

Data

Byte n+1

A C K

Data

Byte n+1

Data

...

Byte n+15

A C

Data

...

Byte n+15

S T O P

A C K

IED02273

S T O P

SDA Line

Bus Activity EEPROM

A C K

000000

A C K

IED02274

Figure 16 Sequence for Protection Bit Erase

The first command byte CSW followed by the control byte EEA addresses the page to be protected. The second command byte CSW (identical content of first CSW) is followed by the control byte CTW = 01

for protection bit write or CTE = 03Hfor protection

bit erase. Depending on CTx, the addressed protection bit will be either written or erased.

Semiconductor Group 20 1998-07-27

SLx 24C164/P

The control byte CTx is followed by 16 parameter bytes identical to the 16 data bytes of the page to be protected or unprotected. The data of the first entered byte must be identical to the data byte stored at the lowest address of the current page. The other 15 bytes have to be identical to the bytes stored in ascending address order within the same page.

A successful verification of each byte is indicated by the EEPROM by pulling the SDA line to low (acknowledge ACK).

After verification of the last byte, the bit programming procedure is initiated by the STOP condition. Programming is started only if all 128 bits of a page have been verified successfully. If bit programming has taken place, the address counter points to the uppermost address of the respective page. The write or erase cycle is finished latest after 4 ms. Acknowledge polling may be used for speed enhancement in order to indicate the end of the write or erase cycle (refer to chapter 5.3 Acknowledge Polling).

Semiconductor Group 21 1998-07-27

7.3 Protection Bit Read The byte sequence for random bit read is shown in figure 17.

SLx 24C164/P

Bus Activity Master

SDA Line

Bus Activity EEPROM

S T

Command

Byte

CSW

T S

EEPROM

Address

EEA n

A C K

S T A R T

0000

A C K

Command

Byte

CSW

A C K

Control

Byte CTR

A C K

b b b

A C K

Data

Byte n

Data

Byte n+1

A C K

...

S T O P

A C K

IED02139

b = Protection Bit

Figure 17 Byte Sequence for Protection Bit Read

The first command byte CSW followed by the control byte EEA addresses the protection bit to be read. The second command byte CSW is followed by the control byte 00

for

protection bit read. The first bit (MSB) of the transferred byte is the protection bit of the addressed page. The other 7 bits are not valid. The page protection status is indicated as following Protection Bit = 1: A normal write operation changes the data in the associated page Protection Bit = 0: The data in the associated page are protected against changes.

If the master acknowledges a byte with a low state of the SDA line, the protection bit of the next page can be read as the first bit of the following byte. If the master releases the SDA line, a STOP condition has to complete the read procedure. Any number of bytes with a page protection status at the first bit position can be requested by the master. If the bit of the uppermost page has been addressed, the counter has its overflow to the lowest address according to the first page.

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SLx 24C164/P

8 Electrical Characteristics

The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not

otherwise specified, typical characteristics apply at voltage.

8.1 Absolute Maximum Ratings

Stresses above those listed here may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

Parameter Limit Values Units

=25°C and the given supply

Operating temperature range 1 (industrial)

range 2 (automotive)

–40to+85 –40to+125

°C

°C Storage temperature – 65 to + 150 °C Supply voltage – 0.3 to + 7.0 V

All inputs and outputs with respect to ground – 0.3 to

+0.5 V

ESD protection (human body model) 4000 V

8.2 DC Characteristics Parameter Symbol Limit Values Units Test Condition

min. typ. max.

Supply voltage

Supply current

4.5 5.5 V 5 V type

2.7 5.5 V 3 V type 13 mAVCC=5V;fc=100kHz

(write) Standby

current

50 µA Inputs at VCCor V

Input leakage

0.1 10 µA VIN= VCCor V

current Output leakage

0.1 10 µA V

= VCCor V

OUT

current Input low

–0.3 0.3× V

voltage

Semiconductor Group 23 1998-07-27

SLx 24C164/P

8.2 DC Characteristics (cont’d) Parameter Symbol Limit Values Units Test Condition

min. typ. max.

Input high

0.7 × V

voltage Output low

voltage Input/output

I/O

capacitance (SDA)

Input

capacitance (other pins)

Capacitive load

for each bus line

The values for ICCare maximum peak values

Valid over the whole temperature range

This parameter is characterized only

+0.5 V

0.4 V IOL=3mA;VCC=5V

=2.1mA;VCC=3V

pF VIN=0V;VCC=5V

400 pF

Semiconductor Group 24 1998-07-27

8.3 AC Characteristics

SLx 24C164/P

Parameter Symbol Limit Values

= 2.7-5.5 V

min. max. min. max.

SCL clock frequency Clock pulse width low Clock pulse width high SDA and SCL rise time SDA and SCL fall time Start set-up time Start hold time Data in set-up time Data in hold time SCL low to SDA data out valid Data out hold time Stop set-up time

SCL

low

high

SU.STA

HD.STA

SU.DAT

HD.DAT

SU.STO

4.7 1.2 µs

4.0 0.6 µs

4.7 0.6 µs

4.0 0.6 µs 200 100 ns 00µs

0.1 4.5 0.1 0.9 µs 100 50 ns

4.0 0.6 µs

100 400 kHz

1000 300

Limit Values

=4.5-5.5V

300 ns 300 ns

Units

Time the bus must be free before

BUF

4.7 1.2 µs

a new transmission can start SDA and SCL spike suppression

50 100 50 100 ns

time at constant inputs

The minimum rise and fall times can be calculated as follows: 20 + (0.1/pF) × Cb[ns]

Example:

= 100 pF → tR=20+0.1× 100 [ns] = 30 ns

8.4 Erase and Write Characteristics Parameter Symbol Limit Values

= 2.7-5.5 V

Limit Values

=4.5-5.5V

Units

typ. max. typ. max.

Erase + write cycle (per page)

5858 ms Erase page protection bit 2.5 4 2.5 4 ms Write page protection bit 2.5 4 2.5 4 ms

Semiconductor Group 25 1998-07-27

SCL

SLx 24C164/P

LOW

HIGH

SU.STA

HD.STA

SDA In

Start Condition

SDA Out

Figure 18 Bus Timing Data

HD.DAT

SU.DAT

SU.STO BUF

Stop Condition

IED02127

Semiconductor Group 26 1998-07-27

9 Package Outlines

P-DIP-8-4

(Plastic Dual In-line Package)

SLx 24C164/P

P-DSO-8-3

(Plastic Dual Small Outline Package)

GPD05583

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”.

SMD = Surface Mounted Device

Semiconductor Group 27 1998-07-27

Dimensions in mm

GPS09032

Siemens SLA24C164-D-3-P, SLA24C164-D-P, SLA24C164-S-3-P, SLA24C164-S-P, SLE24C164-D-P Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Pin Configuration

2 Description

3 I2C-Bus Characteristics

4 Device Addressing and EEPROM Addressing

5 Write Operations

5.1 Byte Write Address Setting After a START condition the master transmits the Chip Select

5.2 Page Write Address Setting Thepagewriteprocedureisthesameasthebytewrite

5.3 Acknowledge Polling

6 Read Operations

6.1 Random Read

6.2 Current Address Read

6.3 Sequential Read

7.1 Protection Bit Handling

7.2 Protection Bit Write and Erase

7.3 Protection Bit Read The byte sequence for random bit read is shown in figure 17.

8 Electrical Characteristics

8.1 Absolute Maximum Ratings

8.3 AC Characteristics

8.4 Erase and Write Characteristics Parameter Symbol Limit Values

9 Package Outlines