Siemens SLA24C08-D, SLA24C08-D-3, SLA24C16-S-3, SLA24C08-S, SLA24C08-S-3 Datasheet

Standard EEPROM ICs

SLx 24C08/16
8/16 Kbit (1024/2048 × 8bit)

Serial CMOS-EEPROM with

2

C Synchronous 2-Wire Bus

I

Data Sheet 1998-07-27

SLx 24C08/16
Revision History: Current Version: 1998-07-27

Previous Version: 06.97
Page

(in previous
Version)

Page
(in current
Version)

Subjects (major changes since last revision)

3 3 Text was changed to “Typical programming time 5 ms for up to

16 bytes”.

55WP=V

protects upper half entire memory.

CC

4, 5 4, 5 CS0, CS1 and CS2 were replaced by n.c.
5 – The paragraph “Chip Select (CS0, CS1, CS2)” was removed

completely.

11, 12 11, 12 The erase/write cycle is finished latest after 10

8ms.
15 15 Figure 11: second command byte is a CSR and not CSW.
19 19 “Capacitive l oad …” were added.
20 20 Some timings were changed.
20 20 The line “erase/write cycle” was removed.
20 20 Chapter 7.4 “Erase and Write Characteristics” has been added.

I2CBus

Purchase of Siemens I

2

C system p rovided the system conforms to the I2C specifications defined by Philips.

the I

2

C components conveys the license under the Philips I2C patent to use the components in

Edition 1998-07-27
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

©

Siemens AG 1998.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC man ufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. Yo u must bear the costs of transport.

For pa cking material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in­curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
written appr oval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2with the express

8/16 Kbit (1024/2048 × 8bit)SerialCMOS

2

EEPROMs, I

Features

• Data EEPROM internally organized as

1024/2048 bytes and 64/128 pages × 16 bytes

• Low power CMOS

V

•

• Two wire serial interface bus, I

• Filtered inputs for noise suppression with

• Clock frequency up to 400 kHz

• High programming flexibility

= 2.7 to 5.5 V operation

CC

compatible

Schmitt trigger

C Synchronous 2-Wire Bus

2

C-Bus

SLx 24C08/16

P-DIP-8-4

– Internal programming voltage
– Self timed programming cycle including erase
– Byte-write and page-write programming, between

1 and 16 bytes

– Typical programming time 5 ms for up to 16 bytes

• High reliability

6

– Endurance 10

cycles

– Data retention 40 years

1)

1)

– ESD protection 4000 V on all pins

• 8 pin DIP/DSO packages

• Available for extended temperature ranges

– Industrial: − 40 °C to + 85 °C
– Automotive: − 40 °C to + 125 °C

P-DSO-8-3

1)

Values are temperature dependent, for further information please refer to your Siemens Sales office.

Semiconductor Group 3 1998-07-27

SLx 24C08/16

Ordering Information
Type Ordering Code Package Temperature Voltage

SLA 24C08-D Q67100-H3572 P-DIP-8-4 – 40 °C … + 85 °C 4.5 V...5.5 V
SLA 24C08-S Q67100-H3518 P-DSO-8-3 – 40 °C … + 85 °C 4.5 V...5.5 V
SLA 24C08-D-3 Q67100-H3435 P-DIP-8-4 – 40 °C … + 85 °C 2.7 V...5.5 V
SLA 24C08-S-3 Q67100-H3517 P-DSO-8-3 – 40 °C … + 85 °C 2.7 V...5.5 V
SLE 24C08-D Q67100-H3226 P-DIP-8-4 – 40°C … + 125 °C 4.5 V...5.5 V
SLE 24C08-S Q67100-H3227 P-DSO-8-3 – 40°C … + 125 °C 4.5 V...5.5 V
SLA 24C16-D Q67100-H3513 P-DIP-8-4 – 40 °C … + 85 °C 4.5 V...5.5 V
SLA 24C16-S Q67100-H3508 P-DSO-8-3 – 40 °C … + 85 °C 4.5 V...5.5 V
SLA 24C16-D-3 Q67100-H3512 P-DIP-8-4 – 40 °C … + 85 °C 2.7 V...5.5 V
SLA 24C16-S-3 Q67100-H3507 P-DSO-8-3 – 40 °C … + 85 °C 2.7 V...5.5 V
SLE 24C16-D Q67100-H3229 P-DIP-8-4 – 40°C … + 125 °C 4.5 V...5.5 V
SLE 24C16-S Q67100-H3230 P-DSO-8-3 – 40°C … + 125 °C 4.5 V...5.5 V

Other types are available on request

– Temperature range (– 55 °C … + 150 °C)
– Package (die, wafer delivery)

1 Pin Configuration

P-DSO-8-3P-DIP-8-4

N.C.
N.C.
N.C.

V

SS

V

18

CC

72

WP
SCL63

SDA54

N.C.
N.C.
N.C.

V

SS

1
2
3
4

IEP02514

V

8

CC

7

WP

6

SCL
SDA

5

IEP02515

Figure 1
Pin Configuration (top view)

Semiconductor Group 4 1998-07-27

Pin Definitions and Functions
Table 1
Pin No. Symbol Function

1, 2, 3 N. C. Not connected

SLx 24C08/16

4

V

SS

Ground
5 SDA Serial bidirectional data bus
6 SCL Serial clock input
7 WP Write protection input
8

V

CC

Supply voltage

Pin Description

Serial Clock (SCL)

The SCL input is used to clock data into the device on the rising edge and to clock data
out of the device on the falling edge.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses, data or control information into the
device or to transfer data out of the device. The output is open drain, performing a wired
AND function with any number of other open drain or open collector devices. The SDA

V

bus requires a pull-up resistor to

CC

.

Write Protection (WP)

V

WP switched to
WP switched to

allows normal read/write operations.

SS

V

protects the entire EEPROM against changes (hardware write

CC

protection).

Semiconductor Group 5 1998-07-27

2 Description

SLx 24C08/16

The SLx 24C08/16 device is a serial e

emory (EEPROM), organized as 1024/2048 × 8 bit. The data memory is divided into

m

lectrically erasable and programmable read only

64/128 pages. The 16 bytes of a page can be programmed simultaneously.

2

The device conforms to the specification of the 2-wire serial I

C-Bus.Low voltagedesign

permits operation down to 2.7 V with low active and standby currents.
The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at

2.7 ... 4.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V

V

type (
applications and as 3 V type (

= 4.5 … 5.5 V) with two temperature ranges for industrial and automotive

CC

V

= 2.7 … 5.5 V) for industrial applications. The

CC

EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as
chips.

V

SS

V

CC

Chip Address

Control

Logic

WP

Programming

Control

H.V. Pump

SCL

SDA

Start/

Stop

Logic

Serial

Control

Logic

Address

Logic

X

DEC

EEPROM

Page Logic

Y DEC

Dout/ACK

IEB02530

Figure 2
Block Diagram

Semiconductor Group 6 1998-07-27

SLx 24C08/16

3 I2C-Bus Characteristics

The SLx 24C08/16 devices support a master/slave bidirectional bus oriented protocol in
which the EEPROM always takes the role of a slave.

V

CC

Slave 1 Slave 2 Slave 3 Slave 4

SCL

Master

SDA

Slave 8Slave 5 Slave 6 Slave 7

V

CC

IES02183

Figure 3
Bus Configuration

Master Device that initiates the transfer of data and provides the clock for both

transmit and receive operations.

Slave Device addressed by the master, capable of receiving and transmitting

data.

Transmitter The device with the SDA as output is defined as the transmitter. Due to

the open drain characteristic of the SDA output the device applying a low
level wins.

Receiver The device with the SDA as input is defined as the receiver.

Semiconductor Group 7 1998-07-27

SLx 24C08/16

The conventions for the serial clock line and the bidirectional data line are shown in
figure 4.

SCL

SDA

START Condition Data allowed STOP Condition

12

to Change

8

Acknowledge

9

ACK ACK

1

9

IED02128

Figure 4

2

C-Bus Timing Conventions for START Condition, STOP Condition, Data Valida-

I

tion and Transfer of Acknowledge ACK

Standby Mode in which the bus is not busy (no serial transmission, no

programming): both clock (SCL) and data line (SDA) are in high
state. The device enters the standby mode after a STOP condition
or after a programming cycle.

START Condition High to low transition of SDA when SCL is high, preceding all

commands.

STOP Condition Low to high transition of SDA when SCL is high, terminating all

communications. A STOP condition initiates an EEPROM
programming cycle. A STOP condition after reading a data byte
from the EEPROM initiates the Standby mode.

Acknowledge A successful reception of eight data bits is indicated by the

receiver by pulling down the SDA line during the following clock
cycle of SCL (ACK). The transmitter on the other hand has to
release the SDA line after the transmission of eight data bits.
The EEPROM as the receiving device responds with an
acknowledge, when addressed. The master, on the other side,
acknowledges each data byte transmitted by the EEPROM and
can at any time end a read operation by releasing the SDA line (no
ACK) followed by a STOP condition.

Data Transfer Data must change only during low SCL state, data remains valid

on the SDA bus during high SCL state. Nine clock pulses are
required to transfer one data byte, the most significant bit (MSB)
is transmitted first.

Semiconductor Group 8 1998-07-27

SLx 24C08/16

4 Device Addressing and EEPROM Addressing

After a START condition, the master always transmits a Command Byte CSW or CSR.
After the acknowledge of the EEPROM a Control Byte follows, its content and the
transmitter depend on the previous Command Byte. The description of the Command
and Control Bytes is shown in table 2.

Command Byte Selects operation: the least significant bit b0 is low for a write

operation (C
read operation (C

Contains address information: in the CSW Command Byte, the
bit positions b2 or b3 to b1 are decoded for the two or three
uppermost EEPROM address bits A9 or A10 to A8 (in the CSR
Command Byte, the bit positions b3 to b1 are left undefined).

Control Byte Following CSW (b0 = 0): contains the eight lower bits of the

EEPROM address (EEA) bit A7 to A0.

hip Select Write Command Byte CSW) or set high for a

hip Select Read Command Byte CSR).

Following CSR (b0 = 1): contains the data read out, transmitted by
the EEPROM. The EEPROM data are read as long as the master
pulls down SDA after each byte in order to acknowledge the
transfer. The read operation is stopped by the master by releasing
SDA (no acknowledge is applied) followed by a STOP condition.

Table 2

2

Command and Control Byte for I

C-Bus Addressing of Chip and EEPROM

Definition Function

b7 b6 b5 b4 b3 b2 b1 b0

CSW 1 0 1 0 A10 A9 A8 0 Chip Select for Write
CSR 1 0 1 0 x x x 1 Chip Select for Read
EEA A7 A6 A5 A4 A3 A2 A1 A0 EEPROM address

The device has an internal address counter which points to the current EEPROM
address.

The address counter is incremented
– after a data byte to be written has been acknowledged, during entry of further data

byte

– during a byte read, thus the address counter points to the following address after

reading a data byte.

Semiconductor Group 9 1998-07-27

SLx 24C08/16

The timing conventions for read and write operations are described in figures 5 and 6.

Command Byte (CSW) Data Transfer to EEPROM

SCL

SDA

1234

0

1

1

5

0

A10 A9 A8

6

START from Master Acknowledge from EEPROMAcknowledge from EEPROM

Figure 5
Timing of the Command Byte CSW

Command Byte (CSR) Data Transfer from EEPROM

SCL

SDA

1234

0

1

1

5

6

0

XXX

8

7

0

8

7

ACK

1

10

9

9

A7

10

11 12

A6 A5

11 12

13

A4

13

14

A3

14

15 16

A2 A1

15 16

17

A0

ACK

IED02257

17

ACK

18

18

START from Master Acknowledge from MasterAcknowledge from EEPROM

IED02185

Figure 6
Timing of the Command Byte CSR

Semiconductor Group 10 1998-07-27

SLx 24C08/16

5 Write Operations

Changing of the EEPROM data is initiated by the master with the command byte CSW.
Depending on the state of the Write Protection pin WP either one byte (Byte Write) or up
to 16 bytes (Page Write) are modified in one programming procedure.

5.1 Byte Write Address Setting After a START condition the master transmits the Chip Select

Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following byte with the
EEPROM address (A0 to A7) is loaded into the address
counter of the EEPROM and acknowledged by the EEPROM.

Transmission of Data Finally the master transmits the data byte which is also

acknowledged by the EEPROM into the internal buffer.

Programming Cycle Then the master applies a STOP condition which starts the

internal programming procedure. The data bytes are written in
the memory location addressed in the EEA byte (A0 to A7)
andtheCSWbyte(A8toA9orA10).Theprogramming
procedure consists of an internally timed erase/write cycle. In
the first step, the selected byte is erased to “1”. With the next
internal step, the addressed byte is written according to the
contents of the buffer.

S

Master

SDA Line

Bus Activity
EEPROM

T
A

Command Byte

R
T

S

CSW

EEPROM Address

EEA

0

A
C
K

Data ByteBus Activity

A
C
K

S
T
O
P

P

A
C
K

IED02129

Figure 7
Byte Write Sequence

The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3 Acknowledge Polling).

Semiconductor Group 11 1998-07-27

SLx 24C08/16

5.2 Page Write Address Setting Thepagewriteprocedureisthesameasthebytewrite

procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address byte EEA is followed
by a sequence of one to maximum sixteen data bytes with the
new data to be programmed. These bytes are transferred to
the internal page buffer of the EEPROM.

Transmission of Data The first entered data byte will be stored according to the

EEPROM address n given by EEA (A0 to A7) and CSW (A8 to
A9 or A10). The internal address counter is incremented
automatically after the entered data byte has been
acknowledged. The next data byte is then stored at the next
higher EEPROM address. EEPROM addresses within the
same page have common page address bits A4 through A10.
Only the respective four least significant address bits A0
through A3 are incremented, as all data bytes to be
programmed simultaneously have to be within the same page.

Programming Cycle The master stops data entry by applying a STOP condition,

which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.

Those bytes of the page that have not been addressed are not included in the
programming.

S

Master

SDA Line

Bus Activity
EEPROM

T
A

Command Byte

R
T

S

CSW

EEPROM Address

EEA n

0

A
C
K

Data Byte n Data Byte n+1 Data Byte n+15Bus Activity

A
C
K

A
C
K

A
C
K

S
T
O
P

P

A
C
K

IED02140

Figure 8
Page Write Sequence

The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3 Acknowledge Polling).

Semiconductor Group 12 1998-07-27

SLx 24C08/16

5.3 Acknowledge Polling

During the erase/write cycle the EEPROM will not respond to a new command byte until
the internal write procedure is completed. At the end of active programming the chip
returns to the standby mode and the last entered EEPROM byte remains addressed by
the address counter. To determine the end of the internal erase/write cycle acknowledge
polling can be initiated by the master by sending a START condition followed by a
command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/
write cycle is not completed, the device will not acknowledge the transmission. If the
internal erase/write cycle is completed, the device acknowledges the received command
byte and the protocol activities can continue.

Internal Programming

Procedure

Send CS-Byte

Acknowledge

from EEPROM

Next Operation

Figure 9
Flow Chart “Acknowledge Polling”

Send Start

No

received?

Yes

IED02131

Semiconductor Group 13 1998-07-27

STOP from Master initiates erase/write cycle

START from Master

CSR

CSR

SLx 24C08/16

CSR

SDA

SDA

P

S

STOP from Master initiates erase/write cycle

START from Master

CSW

P

S

1

S

CSW

0

S

Figure 10
Principle of Acknowledge Polling

1

S

Acknowledge of EEPROM
indicates complete erase/
write cycle

0

S S

S

Acknowledge of EEPROM
indicates complete erase/
write cycle

1

e.g. STOP condition

CSW

0

P

P

IED02166

Semiconductor Group 14 1998-07-27

SLx 24C08/16

6 Read Operations

Reading of the EEPROM data is initiated by the Master with the command byte CSR.

6.1 Random Read

Random read operations allow the master to access any memory location.
Address Setting The master generates a START condition followed by the

command byte CSW. The receipt of the CSW-byte is
acknowledged by the EEPROM with a low on the SDA line.
Now the master transmits the EEPROM address (EEA) to the
EEPROM and the internal address counter is loaded with the
desired address.

Transmission of CSR After the acknowledge for the EEPROM address is received,

the master generates a START condition, which terminates
the initiated write operation. Then the master transmits the
command byte CSR for read, which is acknowledged by the
EEPROM.

Transmission of
EEPROM Data

STOP Condition from
Master

S
T

Bus Activity
Master

SDA Line

Bus Activity
EEPROM

A

Command Byte

R

T
S

Figure 11
Random Read

During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.

During the following clock cycle the masters releases the bus
and then transmits the STOP condition.

S

S
T

O

P
P

IED02133

CSW

EEPROM Address

EEA n

0

A
C
K

T
A

Command Byte

R
T

S

A
C
K

CSR

1

A
C
K

Data Byte

Semiconductor Group 15 1998-07-27

SLx 24C08/16

6.2 Current Address Read

The EEPROM content is read without setting an EEPROM address, in this case the
current content of the address counter will be used (e.g. to continue a previous read
operation after the Master has served an interrupt).

Transmission of CSR For a current address read the master generates a START

condition, which is followed by the command byte CSR (c

elect read). The receipt of the CSR-byte is acknowledged by

s
the EEPROM with a low on the SDA line.

hip

Transmission of
EEPROM Data

STOP Condition from
Master

Bus Activity
Master

SDA Line

Bus Activity
EEPROM

Figure 12
Current Address Read

During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.

During the following clock cycle the masters releases the bus
and then transmits the STOP condition.

S
T
A

Command Byte

R

T
S

CSR

1

A
C
K

Data Byte

S
T
O
P

P

IED02132

Semiconductor Group 16 1998-07-27

SLx 24C08/16

6.3 Sequential Read

A sequential read is initiated in the same way as a current read or a random read except
that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM
then continues the data transmission. The internal address counter is incremented by
one during each data byte transmission.

A sequential read allows the entire memory to be read during one read operation. After
the highest addressable memory location is reached, the internal address pointer “rolls
over” to the address 0 and the sequential read continues.

The transmission is terminated by the master by releasing the SDA line (no
acknowledge) and generating a STOP condition (see figure 13).

S

Bus Activity
Master

T
A

Command Byte

R
T

CSW

A
C
K

A
C
K

S
T
O
P

SDA Line

Bus Activity
EEPROM

Figure 13
Sequential Read

S

1

A

A
C

C
K

K

Data Byte n

Data Byte n+xData Byte n+1

P

IED02134

Semiconductor Group 17 1998-07-27

SLx 24C08/16

7 Electrical Characteristics

The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not

T

otherwise specified, typical characteristics apply at
voltage.

7.1 Absolute Maximum Ratings

Stresses above those listed here may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational section of this data sheet is not implied.
Exposure to absolute maximum ratings for extended periods may affect device reliability.

Parameter Limit Values Units

=25°C and the given supply

A

Operating temperature range 1 (industrial)

range 2 (automotive)

–40to+85
–40to+125

°C

°C
Storage temperature – 65 to + 150 °C
Supply voltage – 0.3 to + 7.0 V

V

All inputs and outputs with respect to ground – 0.3 to

+0.5 V

CC

ESD protection (human body model) 4000 V

7.2 DC Characteristics
Parameter Symbol Limit Values Units Test Condition

min. typ. max.

Supply voltage

Supply current

V

CC

V

CC

1)

I

CC

4.5 5.5 V 5 V type

2.7 5.5 V 3 V type
13 mAVCC=5V;fc= 100 kHz

(write)
Standby

current

I

2)

SB

50 µA Inputs at VCCor V

SS

Input leakage

I

LI

0.1 10 µA VIN= VCCor V

SS

current
Output leakage

I

LO

0.1 10 µA V

= VCCor V

OUT

SS

current
Input low

V

IL

–0.3 0.3× V

CC

V

voltage

Semiconductor Group 18 1998-07-27

SLx 24C08/16

7.2 DC Characteristics (cont’d)
Parameter Symbol Limit Values Units Test Condition

min. typ. max.

Input high

V

IH

0.7 × V

voltage
Output low

V

OL

voltage
Input/output

C

I/O

capacitance
(SDA)

Input

C

IN

capacitance
(other pins)

Capacitive load

C

b

for each bus line

1)

The values for ICCare maximum peak values

2)

Valid over the whole temperaturerange

3)

This parameter is characterized only

CC

V

+0.5 V

CC

0.4 V IOL=3mA;VCC=5V

I

=2.1mA;VCC=3V

OL

3)

8

3)

6

pF VIN=0V;VCC=5V

pF VIN=0V;VCC=5V

400 pF

Semiconductor Group 19 1998-07-27

7.3 AC Characteristics

SLx 24C08/16

Parameter Symbol Limit Values

V

= 2.7-5.5 V

CC

min. max. min. max.

SCL clock frequency
Clock pulse width low
Clock pulse width high
SDA and SCL rise time
SDA and SCL fall time
Start set-up time
Start hold time
Data in set-up time
Data in hold time
SCL low to SDA data out valid
Data out hold time
Stop set-up time

f

SCL

t

low

t

high

t

R

t

F

t

SU.STA

t

HD.STA

t

SU.DAT

t

HD.DAT

t

AA

t

DH

t

SU.STO

4.7 1.2 µs

4.0 0.6 µs

4.7 0.6 µs

4.0 0.6 µs
200 100 ns
00µs

0.14.50.10.9µs
100 50 ns

4.0 0.6 µs

100 400 kHz

1000
300

Limit Values

V

= 4.5-5.5 V

CC

1)

1)

300 ns
300 ns

Units

Timethe bus must befree before

t

BUF

4.7 1.2 µs

a new transmission can start
SDA and SCL spike suppression

t

l

50 100 50 100 ns

time at constant inputs

1)

Theminimumriseandfalltimescanbecalculatedasfollows:20+(0.1/pF)× Cb[ns]
Example:

C

= 100 pF → tR=20+0.1× 100 [ns] = 30 ns

b

7.4 Erase and Write Characteristics Parameter Symbol Limit Values

V

= 2.7-5.5 V

CC

Limit Values

V

= 4.5-5.5 V

CC

Units

typ. max. typ. max.

Erase + write cycle (per page)

t

WR

5858 ms
Erasepageprotectionbit 2.5 4 2.5 4 ms
Write page protection bit 2.5 4 2.5 4 ms

Semiconductor Group 20 1998-07-27

SCL

SLx 24C08/16

t

R

t

F

t

LOW

t

HIGH

t

SU.STA

t

HD.STA

SDA In

Start Condition

SDA Out

Figure 14
Bus Timing Data

AA

t

HD.DAT

tt

DH

t

SU.DAT

t

SU.STO BUF

t

Stop Condition

IED02127

Semiconductor Group 21 1998-07-27

8 Package Outlines

P-DIP-8-4

(Plastic Dual In-line Package)

SLx 24C08/16

P-DSO-8-3

(Plastic Dual Small Outline Package)

GPD05583

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.

SMD = Surface Mounted Device

Semiconductor Group 22 1998-07-27

Dimensions in mm

GPS09032