Siemens HYB3164800J-50, HYB3164800J-60, HYB3164800T-50, HYB3164800T-60, HYB3165800J-50 Datasheet

...
8M x 8-Bit Dynamic RAM
(4k & 8k Refresh)
HYB 3164800J/T -50/-60 HYB 3165800J/T -50/-60
Preliminary Information
8 388 608 words by 8-bit organization
0 to 70 ˚C operating temperature
Fast access and cycle time
RAS access time: 50 ns (-50 version) 60 ns (-60 version) Cycle time: 90 ns (-50 version) 110 ns (-60 version) CAS access time: 13 ns ( -50 version) 15 ns ( -60 version)
Fast page mode cycle time
35 ns (-50 version) 40 ns (-60 version)
Single + 3.3 V (± 0.3V) power supply
Low power dissipation
max. 396 active mW ( HYB 3164800J/T-50) max. 360 active mW ( HYB 3164800J/T-60) max. 504 active mW ( HYB 3165800J/T-50) max. 432 active mW ( HYB 3165800J/T-60)
7.2 mW standby (TTL) 720 W standby (MOS)
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
Fast page mode capability
8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800J/T)
4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800J/T)
Plastic Package:
P-SOJ-34-1 500 mil HYB 3164(5)800J P-TSOPII-34-1 500 mil HYB 3164(5)800T
Semiconductor Group 121
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in SIEMENS/IBM’s most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800J/T to be packaged in a 500 mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.
Ordering Information Type Ordering
Code
HYB 3164800J-50 on request P-SOJ-34-1 500 mil DRAM (access time 50 ns) HYB 3164800J-60 on request P-SOJ-34-1 500 mil DRAM (access time 60 ns) HYB 3164800T-50 on request P-TSOPII-34-1 500 mil DRAM (access time 50 ns) HYB 3164800T-60 on request P-TSOPII-34-1 500 mil DRAM (access time 60 ns) HYB 3165800J-50 on request P-SOJ-34-1 500 mil DRAM (access time 50 ns) HYB 3165800J-60 on request P-SOJ-34-1 500 mil DRAM (access time 60 ns) HYB 3165800T-50 on request P-TSOPII-34-1 500 mil DRAM (access time 50 ns) HYB 3165800T-60 on request P-TSOPII-34-1 500 mil DRAM (access time 60 ns)
Pin Names
A0-A12 Address Inputs for HYB 3164800J/T A0-A11 Address Inputs for HYB 3165800J/T RAS Row Address Strobe OE Output Enable I/O1-I/O8 Data Input/Output
Package Descriptions
CAS Column Address Strobe WRITE Read/Write Input Vcc Power Supply ( + 3.3V) Vss Ground
Semiconductor Group 122
P-SOJ-34-1 (500 mil)
P-TSOPII-34-1 (500 mil)
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Pin Configuration
Semiconductor Group 123
TRUTH TABLE
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
FUNCTION RAS CAS WRITE OE ROW
ADDR Standby H H - X X X X X High Impedance Read L L H L ROW COL Data Out Early-Write L L L X ROW COL Data In Delayed-Write L L H - L H ROW COL Data In Read-Modify-Write L L H - L L - H ROW COL Data Out, Data In Fast Page Mode Read 1st Cycle L H - L H L ROW COL Data Out
2nd Cycle L H - L H L n/a COL Data Out
Fast Page Mode Early Write
Fast Page Mode RMW 1st Cycle L H - L H - L L - H ROW COL Data Out, Data In
RAS only refresh L H X X ROW n/a High Impedance CAS-before-RAS refresh H - L L H X X n/a High Impedance Test Mode Entry H - L L L X X n/a High Impedance Hidden Refresh READ L-H-L L H L ROW COL Data Out
1st Cycle L H - L L X ROW COL Data In
2nd Cycle L H - L L X n/a COL Data In
2st Cycle L H - L H - L L - H n/a COL Data Out, Data In
WRITE L-H-L L L X ROW COL Data In
COL
ADDR
I/O1-
I/O8
Semiconductor Group 124
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Block Diagram for HYB 3165800J/T
Semiconductor Group 125
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Block Diagram for HYB 3164800J/T
Semiconductor Group 126
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 ˚C
Storage temperature range.........................................................................................– 55 to 150 ˚C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics
T
= 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165800J/T)
A
Parameter Symbol Limit Values Unit Note
min. max.
Input high voltage Input low voltage Output high voltage (LVTTL)
V
IH
V
IL
V
OH
2.0 Vcc+0.3 V 1) – 0.3 0.8 V 1)
2.4 V
Output „H“ level voltage (Iout = -2mA) Output low voltage (LVTTL)
V
OL
0.4 V
Output „L“level voltage (Iout = +2mA) Output high voltage (LVCMOS)
V
OH
Vcc-0.2 - V
Output „H“ level voltage (Iout = -100uA) Ouput low voltage (LVCMOS)
V
OL
- 0.2 V
Output „L“ level voltage (Iout = +100uA) Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
I
I
I(L)
O(L)
– 2 2 µA
– 2 2 µA
Average Vcc supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Vcc supply current
(RAS=CAS= Vih)
Semiconductor Group 127
I
I
CC1
CC2
– –
110 (140) 100 (120)mAmA
2 mA
2) 3) 4)
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
DC Characteristics
T
= 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165800J/T)
A
(cont’d)
Parameter Symbol Limit Values Unit Note
min. max.
Average Vcc supply current, during RAS-only refresh cycles: -50 ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
Average Vcc supply current,
during fast page mode: -50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
Average Vcc supply current, during
CAS-before-
RAS refresh mode: -50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
Self Refresh Current
Average Power Supply Current during Self Refresh. (CBR cycle with tRAS>TRASSmin,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
CAS held low,
I
I
I
I
I
CC3
CC4
CC5
CC6
CC7
– –
– –
110 (140) 100 (120)mAmA
85 (85) 75 (75)mAmA
200 A
– –
110 (140) 100 (120)mAmA
400 A
2) 4)
2) 3) 4)
2) 4)
Capacitance
T
= 0 to 70 ˚C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
A
Parameter Symbol Limit Values Unit
min. max.
Input capacitance (A0 to A11,A12) Input capacitance (
RAS, CAS, WRITE, OE) C
I/O capacitance (I/O1-I/O8)
C
I1
I2
C
IO
–5pF –7pF –7pF
Semiconductor Group 128
AC Characteristics (note: 6,7,8)
T
= 0 to 70 ˚C,
A
V
= 3.3 ± 0.3V
CC
HYB 3164(5)800J/T-50/-60
8M x 8-DRAM
Parameter Symbol HYB
3164(5)800
J/T-50
min. max. min. max.
common parameters
Random read or write cycle time t
RAS precharge time t
RAS pulse width t CAS pulse width t Row address setup time t Row address hold time t Column address setup time t Column address hold time t RAS to CAS delay time t RAS to column address delay time t RAS hold time t CAS hold time t CAS to RAS precharge time Transition time (rise and fall) t Refresh period for HYB3164800 t Refresh period for HYB3165800 t
RC
RP
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
t
CRP
T
REF
REF
90 110 ns 30 40 ns 50 100k 60 100k ns 13 100k 15 100k ns 0–0–ns 8–10–ns 0–0–ns 10 10 ns 18 37 20 45 13 25 15 30 ns 13 15 ns 50 60 ns 5–5–ns 3 30 3 30 ns – 128 128 ms – 64 64 ms
HYB
3164(5)800
J/T-60
Unit Note
7
Read Cycle
Access time from RAS t Access time from CAS t Access time from column address t OE access time t Column address to RAS lead time t Read command setup time t Read command hold time t Read command hold time referenced
to
RAS
RAC
CAC
AA
OEA
RAL
RCS
RCH
t
RRH
Semiconductor Group 129
50 60 ns – 13 15 ns – 25 30 ns – 13 15 ns
8, 9 8, 9 8, 10 8
25 30 ns 0–0–ns 0–0–ns 0–0–ns
11 11
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