Sharp LH543620P-30, LH543620P-20, LH543620M-30, LH543620M-25, LH543620M-20 Datasheet
...
LH543620
1024 × 36 Synchronous FIFO
FEATURES
•• Fast Cycle T imes: 20/25/30 ns
•• Selectable 36/1 8/9-Bit Word Widt h for Both
Input Port and Output Port
•• Byte-O rder- Reversal Funct ion (i.e. ,
‘Big-Endian’ ↔ ‘Little-Endian’ Conversion)
•• 16-mA-I
OL
Three-State Outputs
•• Automatic Byte Parity Checking
•• Selectable Byte Parity Generati on
•• Five Status Flags: Full, Almost-Full,
Half-F ull, Almost -Em pty, and Empt y
•• All FIFO Status Fl ags are Synchro nous
(
AE, HF, AF Through Programming of
Control Register)
•• Programmed Values may be entered from
either Port
•• T wo Enable Control Signals for each Port
•• Mailbox Register with Synchronized Flags
•• Asynchronous Data-Byp ass Function
•• ‘Smart’ Data- R etransmit Funct i on
•• Configurable for Paralleled FIFO Operat ion
(72-Bit Data Width)
•• Space-Saving PQFP and TQFP
1
Packages
•• PQFP-to-PGA Pack a ge Conversion
2
FUNCTIONAL DESCRIP TIO N
The LH543620 i s a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS RAM technology,
capable of containing up to 1024 36-bit words. It can
replace four or more nine-bit-wide FIFOs in many applications.
The input port and the output port operate independently of each other. Write operations are performed
on the rising edge o f the input clock CKI, an d enable d by
two enabled signals ENI1, ENI2. Read operations are
performed on the rising ed ge of the output clock CKO and
ena b led by two ena b led signals ENO1, ENO2.
Five status flags are available to monitor the memory
array status: Ful l, Almost-Full, Half-Full, Almost-Empty,
and Empty . The Almost-Full and Almost-Empt y flags a re
initialized to a default offset of eight locations from their
respec tive boundaries, but they are each pr ogramm able
ove r the ent ire FI FO dept h.
Both the input port and the output port may be set
independently to operate at three data-word widths: 36
bits, 18 bits, or 9 bits. This setting may be changed during
system operation. The LH543620 can per form Byte-Order-Re versal on the f our nine- bit byt es of each 36-bit data
word pass ing thr ough it , thus ac com plishing ‘Big Endian ’
↔ ‘Little Endian’ conversion.
When dat a is read out of the FI FO a byte -pa rit y check
is performed. The parity flag is used to indicate that a
parity error was detected in one of the 9-bit bytes of the
output word .
Parity g eneratio n, when select ed, crea tes the par ity bit
of each 8-bit byte of the input word. The result is written
into the MSB-bit of each 9-bit byte, overwri ting the previous contents of the bit. The default is odd parity. Howeve r, the FIFO m ay be pr ogr amm ed to use even parity .
The LH543620 has a data-by pass mode that connects
the out put port t o the input p ort asynchronous ly . A m ailbox
facility with Synchronized Flags is pr ovided from the inpu t
port to the out put port.
The LH543620’s ‘Smart-Retransmit’ capability sets the
internal-memory read pointer to any arbitrary memory
location. The ‘Smart-Retransmit’ capability includes a
Markin g Function and a Programm able Offset to support
data communication and digital signal processing applications.
1. This is a final data sheet; except that all references to the TQFP
package have Preliminary status.
2. For PQFP-to-PGA conversion for thru-hole board designs, Sharp
recommend s ITT Pomona Electronics’ SMT /PGA Generic Converter model #5853®. This converter maps t he LH543620 132pin PQFP to a generic 13 × 13, 132-pin PGA (100-mil pitch). For
more information, contact Sharp or ITT Pomona Electronics at
1500 East Ninth Street, Pomona, CA 91766, (909) 469-2900.
1
RESET
LOGIC
INPUT
PORT
RS
MAILBOX
OUTPUT
PORT
LOGIC
D[35:0]
ADI
0
ENI
2
ENI
1
CKO
ENO
1
ENO
2
ADO
0
WSO0WSO
1
ADO1ADO
2
WSI
0
FIFO
MEMORY ARRAY
1024 x 36
WRITE
POINTER
READ
POINTER
STATUS FLAGS
CONTROL
AE OFFSET
AF OFFSET
RT OFFSET
RT BASE
PARITY
MUX
RESOURCE REGISTERS
BUS
SWITCHING
(FUNNELING)
PARITY
GENERATOR
BUS
SWITCHING
(DEFUNNELING)
PARITY
CHECK
MUX
OUTPUT PORT
OUTPUT BUFFER
OUTPUT PORT
INPUT BUFFER
OE
Q[35:0]
MEF
PF
INPUT
PORT
LOGIC
ADI1ADI
2
FF
AF
HF
CAPR
BYE
RESOURCE
REGISTER
OUTPUT
LOGIC
MUX
RESOURCE
REGISTER
INPUT
LOGIC
WSI
1
CKI
MFF
EF
AE
RETRANSMIT
LOGIC
RT
RTMD0RTMD
1
543620-6
16 (Q [15:0])
Figure 1. LH543620 Block Diagram
LH543620 1024 × 36 Synchronous FIFO
2
PIN DESCRIPTIONS (SUMMARY)
PIN NAME
PIN
TYPE *
DESCRIPTION
DATABUS
D[35:0 ]
I
36-Bit Input-Port Databus
Q[15:0]
I/ O/ Z
Th ree -St ate 36- Bit Outpu tPort Databus
Q[35:16]
O/Z
CLOCKS
CKI
I
Input-Port Clock
CKO
I
Out put-Port C loc k
ASYNCHRONOUS CONTROL
RS
I
Master Reset
OE
I
Output Enable
BYE
I
Data-Bypas s Enable
CAPR
I
Comm and- Addr ess Por t
Refer ence
CONTROL SIGNALS SYNCHRONOUS
TO THE INPUT CLOCK
ENI1,ENI
2
I
Input-Por t Enables
ADI[2:0]
I
Input- Port Address
WSI[1:0]
I
Input-Por t Word-Width
Selection
STATUS FLAGS SYNCHRONOUS
TO THE INPUT CLOCK
FF
O
Full Flag
AF
O
Almost-Full Flag
HF
1
O
Half-Fu ll Flag
MFF
O
Mailbox-Full F lag
PIN NAME
PIN
TYPE *
DESCRIPTION
CONTROL SIGNALS SYNCHRONOUS
TO THE OUTPUT CLOCK
ENO1,ENO
2
I
Output-Port Enables
ADO[2:0 ]
I
Output-Por t Address
WSO[ 1: 0]
I
Out put-Por t W o rd -Width
Se lection
R TMD[1: 0]
I
Retransmit Mode Control
RT
I
Retransmit
STATUS FLAGS SYNCHRONOUS
TO THE OUTPUT CLOCK
AE
O
Almost-Empty Flag
EF
O
Empty Flag
PF
O
Parity-Error Flag
MEF
O
Mailbox-Empt y Flag
VOLTAGES AND GROUNDS
V
CC
V
Positive Power
V
SS
V
Ground
* I = Input, O = Output, V = Voltag e , Z = High-Impedance
1. The half-full flag is user-selectable to be synchronize d to either
CKI or CKO.
1024 × 36 Synchronous FIFO LH543620
3
PIN CONNECTIONS
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
MEF
MFF
EF
AE
V
SS
HF
AF
FF
CKO
Q
35
Q
30
Q
28
Q
27
Q
25
Q
24
Q
23
Q
22
PF
V
SS
V
CC
V
SS
49
50
Q
31
515253545556575859606162636465666768697071727374757677787980818283
D
29
D
30
D
31
D
33
D
34
D
35
ENI
1
ENI
2
ADI
0
ADI
2
WSI
0
WSI
1
BYE
ENO
1
ADO
0
ADO
1
ADO
2
WSO
0
WSO
1
RS
RTMD
1
RT
OE
V
CC
ADI
1
CAPR
ENO
2
V
CC
RTMD
0
V
CC
17
16151413121110
9876543
2
Pin 1
Pin 132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
D
0D1D2
D
3
D4D5D6D8VSSD9D
11
D
12
D25D
26
D
10
D
27
V
CC
Q
20
Q
19
Q
17
Q5Q
4
Q
2
V
SS
Q
1
Q
0
543620-4
D
7
D13D
14
V
CC
V
CC
Q
34
V
SS
Q
33
Q
32
V
CC
Q
29
V
CC
Q
26
V
SS
V
CC
Q
18
Q
21
Q
16
V
CC
Q15Q14Q13Q
12
Q
11
Q
10
Q9Q
8
Q
7
Q
6
V
SS
V
CC
V
CC
V
CC
Q
3
V
SS
V
SS
D
32
D
28
V
SS
V
CC
D15D16D17CKI
D18D19D20D21D22D23D
24
V
SS
V
SS
V
SS
TOP VIEW
CHAMFERED
EDGE
132-PIN PQFP
Figur e 2. Pin Connections f or 132-Pin PQFP Package
(T op Vi ew )
LH543620 1024 × 36 Synchronous FIFO
4
PIN LIST
PIN NAME PIN NO.
D
14
1
D
13
2
D
12
3
D
11
4
D
10
5
D
9
6
D
8
8
D
7
9
D
6
10
D
5
11
D
4
12
D
3
13
D
2
14
D
1
15
D
0
16
MEF 18
MFF
19
EF
20
AE
21
HF
23
AF
24
FF
25
PF
26
CKO
27
Q
35 29
Q
34
30
Q
33
32
Q
32
33
Q
31
35
Q
30
36
Q
29
38
Q
28
39
Q
27 41
Q
26
42
Q
25
44
Q
24
45
Q
23
47
Q
22
48
Q
21
52
Q
20
53
Q
19 55
Q
18
56
Q
17
58
Q
16
59
PIN NAME PIN NO.
Q
15
61
Q
14
62
Q
13
64
Q
12
65
Q
11
67
Q
10
68
Q
9
70
Q
8
71
Q
7
73
Q
6
74
Q
5
76
Q
4
77
Q
3
79
Q
2
80
Q
1
82
Q
0
83
OE
85
RT
86
RTMD
1
87
RTMD
0
88
RS
89
WSO
1
90
WSO
0
91
ADO
2
93
ADO
1 94
ADO
0
95
ENO
2
96
EN0
1
97
BYE
98
CAPR
99
WSI
1
101
WSI
0
102
ADI
2 103
ADI
1
104
ADI
0
105
ENI
2
106
ENI
1
107
D
35
109
D
34
110
D
33
111
D
32 112
D
31
113
D
30
114
D
29
115
PIN NAME PIN NO.
D
28
116
D
27
117
D
26
119
D
25
120
D
24
121
D
23
122
D
22
123
D
21
124
D
20
125
D
19
126
D
18
127
CKI
128
D
17
130
D
16
131
D
15
132
V
SS
7
V
CC
17
V
SS
22
V
CC
28
V
SS
31
V
CC
34
V
SS
37
V
CC
40
V
SS
43
V
CC 46
V
SS
49
V
SS
50
V
CC
51
V
CC
54
V
SS
57
V
CC
60
V
SS
63
V
CC 66
V
SS
69
V
CC
72
V
SS
75
V
CC
78
V
SS
81
V
CC
84
V
CC
92
V
SS 100
V
CC
108
V
SS
118
V
CC
129
1024 × 36 Synchronous FIFO LH543620
5
ABSOLUTE MAXIMUM RATINGS
1
PARAMETER RATING
Supply Voltage to VSS Potential –0.5 V to 7 V
Signal Pin Voltage to VSS Potentia l
2
–0.5 V to VCC + 0.5 V
DC O utput Cu rrent
3
± 75 mA
Stor age Temp era tur e Range –65oC to 150oC
Power Dissipat io n (Package Limit ) 2.5 Wat ts (Quad Flat Pack)
NOTES:
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for
transient conditions only. Functional operation of the device at these or any other conditions outside those indicated in the ‘Operating Range’
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Negative undershoot of 1.5 V i n amplitude is permitted for up to 10 ns, once per cy cle.
3. O utp uts should not be shorted f or more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGE
SYMBOL PARAMETER MIN MAX UNIT
T
A
T emper ature, Ambient
070
o
C
VCCSupply V olta ge
4.5 5.5 V
V
SS
Supply V olta ge
00V
VILLogic LOW Input V oltag e
1
–0.5 0.8 V
V
IH
Logic HIGH Input Volt age
2.2 Vcc + 0.5 V
NOTE:
1. Negative undershoot of 1.5 V i n amplitude is permitted for up to 10 ns, once per cy cle.
DC ELECTRICAL CHARACTERISTICS (O ver Operating Range)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
LI
Input Le akage Cur rent VCC = 5.5 V, VIN = 0 V T o V
CC
–10 10
µA
I
LO
I/O Leakage Current
OE ≥ VIH, 0 V ≤ V
OUT
≤ V
CC
–10 10
µA
V
OL
Logic LOW Output Volt age IOL = 16. 0 mA
0.4 V
V
OH
Logic HIGH Outpu t Volt age IOH = –8.0 mA
2.4 V
I
CC
Average Supply Current
1,2
Measur ed at fC = maximum
205 380 mA
I
CC2
Average St andby Supply Current
1,3
All Input s = V
IHMIN
(Clock idle)
40 85 mA
I
CC3
Power-Dow n S upply Current
1
All Input s = VCC,
Out put s – open,
Contro l – deasserted,
Clocks = V
CC
0.01 1.0 mA
NOTE:
1. ICC, I
CC2
, and I
CC3
are dependent upon actual output loading, and ICC is also dependent on cycle times.
Specified values are with outputs open (for ICC: CL = 0 pF); and, for ICC, operating at minimum cycle times.
2. ICC (MAX): Using worst case conditions and data pattern. ICC (TYP): Using VCC = 5 V and average data pattern.
3. I
CC2
(TYP): Using VCC = 5 V and TA = 25°C.
LH543620 1024 × 36 Synchronous FIFO
6
AC TEST CONDITIONS
PARAMETER RATING
Input Pulse Leve ls
VSS to 3 V
Inpu t Rise and Fall Times (10% to 90% )
3 ns
Output Re ference Levels
1.5 V
Input Timing Reference Levels
1.5 V
Output Load , Timin g T es ts
Fig ure 3
CAPACITANCE
1,2
PARAMETER RATING
CIN MAX. (Input Capacitance)
8 pF
C
OUT
MAX. (Output Capacit ance)
10 pF
NOTES :
1. Sample tested only.
2. Capacitances are maximum values at 25oC,
measured at 1.0 MHz, with VIN = 0 V.
543620-27
INCLUDES JIG AND SCOPE CAPACITANCES
*
DEVICE
UNDER
TEST
+5 V
30 pF
1.1 k Ω
680 Ω
*
Figur e 3. Output Load Circui t
1024 × 36 Synchronous FIFO LH543620
7
AC ELECTRIC AL CHARACTERIST ICS 1 (See Timing Diagrams Pages 21-35)
SYMBOL DESCRIPTION
–20 –25 –30
UNIT
MIN MAX MIN MAX MIN MAX
f
C
Clock Cycle Frequency 50 40 33 MHz
t
C
Clock Cycle Time 20 25 30 ns
t
CH
Clock HIGH Time 8 10 12 ns
t
CL
Clock LOW Time 9 12 14 ns
t
DS
Data In Setup Time
567ns
t
DSO
Data Setup Time When Writing to Resource
Register From Output Port
10 12 14 ns
t
DH
Data In Hold Time 2 2 2 ns
t
DHO
Data Hold Time When Writing to Resource Register
From Output Port
222ns
t
A
Data Out Acc ess T im e 14 16 18 ns
t
OH
Data Out Hold Time
444ns
t
ES
Enable Setup Time 5 6 7 ns
t
EH
Enable Hold Time 2 2 2 ns
t
OES
Outp ut Enab le Setu p Ti me 6 7 8 ns
t
OEH
Outp ut Enab le Hold Tim e 2 2 2 ns
t
OL
OE to Data Out Low-Z
2
111ns
t
OZ
OE to Data Out High-Z
2
12 15 19 ns
t
OE
OE to Data Valid 10 12 14 ns
t
EF
Empt y Flag Acces s T ime
14 16 18 ns
t
FF
Full Flag Access Time 14 16 18 ns
t
AE
AE Fla g Acces s T ime 14 16 18 ns
t
AF
AF Fla g Acce ss T ime 14 16 18 ns
t
HF
HF Fla g Acce ss T ime 14 16 18 ns
t
PF
Pari ty Fla g Acce ss T im e
14 16 18 ns
t
MFF
Mail box FF Ac cess T ime 14 16 18 ns
t
MEF
Mail box EF Ac cess T ime 14 16 18 ns
t
AS
Addr ess Setu p T ime 10 12 14 ns
t
AH
Addr ess Hold Ti me 2 2 2 ns
t
WSS
WSI and WSO Setup T ime 10 12 14 ns
t
WSH
WSI and WSO Hold Ti me 2 2 2 ns
t
RTMS
Retransmit Mode Setup Time 5 6 7 ns
t
RTMH
Retr ansm it Mod e Hold T ime
222ns
t
RTS
Retr ansm it Setu p T ime 5 6 7 ns
t
RTH
Retr ansm it Hold Ti me 2 2 2 ns
t
RS
Reset Pulse Width 20 25 30 ns
t
RSR
Reset Recovery Time
2
10 12 15 ns
t
RF
Reset LOW to Flag Valid 30 35 40 ns
t
RO
Reset to Data Out LOW 18 20 22 ns
t
BA
Bypass LOW to Data Valid 12 16 18 ns
t
BD
Bypass Propagation Delay
12 16 18 ns
t
SKEW1
Skew Time Between CKO and CKI for FF
3
7911ns
t
SKEW2
Skew Time Between CKI and CKO for EF
4
7911ns
t
SKEWM
Skew Time Between Clock for Mailbox Flags 7 9 11 ns
NOTES:
LH543620 1024 × 36 Synchronous FIFO
8
PIN NAME DESCRIPTION
DATABUS
D[35:0]
36-bit Input-Port Databus. The D port is the input port for the FIFO memory array, the resource
registe rs, and the mailbo x, or it may be directly connected to the output port. See F igure 4.
D[35:0] is sync hronous t o the rising edge of CKI.
Q[35:0]
Three-St at e 36-Bit Output -Por t Databus. Th e Q port is the out put port for the FIFO memor y array,
the resourc e reg iste rs, and the ma ilbo x, or it may be directly connect ed to the input port. See Figure
4. Q[35:0] is synchronou s to the risin g edge of CKO. The lower 16 bits of the Q port (Q[15: 0]) may
also be used as the input port for the resourc e register .
CLOCKS
CKI
Input-Port Clock. CKI is a free-running wavef or m controlled by an osc illator . It may be irre gular or
asynchronous i f minimum clock-HIGH times and clock- LOW t imes are met.
CKO
Output-Port Clock. CKO is a fr ee-running wavef orm controlled by an oscillator. It may be irregular
or asynchrono us if minimum clock-HIG H times and cloc k-LOW tim es ar e met.
PIN DESCRIPTIONS (FUNCTIONAL)
CAPR
D → MAILBOX
MFF = L
MEF = H
IDLE
*
All the operations are synchronized to CKI,
except MEF is set HIGH on CKO.
*
All the operations are synchronized to CKO,
except MFF is set HIGH on CKI.
543620-5
SELECT INPUT
PORT FUNCTION
ADI [2:0] =
MAILBOX
RESOURCE
REGISTER
OE
MAILBOX → Q
MFF = H
MEF = L
RESOURCE
REGISTER (ADO) → Q
SELECT OUTPUT
PORT FUNCTION
ADO [2:0] =
MAILBOX
CAPR
Q → RESOURCE
REGISTER (ADO)
LH L H
LH
D → RESOURCE
REGISTER (ADI)
RESOURCE
REGISTER
IDLE
INPUT PORT
OUTPUT PORT
Figure 4. Resource Register s, Read and Write
1024 × 36 Synchronous FIFO LH543620
9
Table 1. I nput- P ort Address
ADI2ADI1ADI
0
SELECTION
DEFAULT VALU E
(of the selected
REGISTER)
L L L RBASE register
0
LLH
ROFFSET
register
0
LHLA F off set value
8
L H H Parit y register
0
HL LAE offset value
8
HL HControl register 1
H H L Mailbox
0
HHH
Resource
regist ers writ e
disabled
T abl e 2. Input- Por t Word- Wi dt h Selecti on
WSI1WSI
0
FU NCTION
LL
9-B it Data -Path
Width
Input data D[8:0]
LH
18-Bit Dat a-Pat h
Width
Input dat a D[17:0]
HL
Reserved
HH
36-Bit Dat a-Pat h
Width
Input dat a D[35:0]
PIN NAME DESCRIPTION
ASYNCHRONOUS CONTROL
RS
Master Reset. When asser t ed LOW , the LH543620 int ern al reso urce regis ters are set to their
default value. See Table 1. The stat us flags indicate Emp ty FIFO.
OE
Output Enable. Whe n asserted LOW, OE forces Q[35:0] to be active. When deasser ted HIGH, OE
forces Q[35:0] into a Hi-Z state. Bit 6 of the control regis ter gove rns whether OE suppr esses the
advancement of the Read Pointer (RP). In this case, OE must obey setup time and hold time
relative t o CKO.
BYE
Data-Bypass Enable. When asser te d LOW, BYE conn ect s Q[35:0] directly to D[35:0].
CAPR
Command-Address Port Reference. CAPR determ ines the source of the 16-bit word t o be loaded
into the resource regist er. Whenev er CAPR is LOW, the word comes from the Input Port. Whenever
CAPR is HIGH (OE is HIGH), the word comes from the Output Port.
NOTES:
1. The destination of the resour ce reg iste r is always t he Outp ut Port .
2. CAPR is assumed to be a steady signal. It is not allowed to change ‘on- the-fl y’ during operation .
CONTROL SIGNALS SYNCHRONOUS TO THE INPUT CLOCK
ENI1, ENI
2
Input-Port Enables. ENI1 and ENI2 are active HIGH and synch ron ous to the rising edge of C KI.
Data is written into the FIFO memor y array when both ENI1 and ENI2 are asserted HIGH.
NOTE: ENI1, ENI2 DO NOT ENABLE writing data into the Resour ce Registers or the Mailbox.
ADI[2:0]
Input- Port Ad dress. ADI [2 :0] sp ecifies the In put-Port destination. Se e Table 1. ADI [ 2:0 ] is
synchro nized to the rising edge of CKI.
WSI[1:0]
Input- Port Word-Widt h Se lection. WSI[1:0] selects the Inp ut-Por t Wor d-Widt h. See Table 2.
WSI[1:0] is synchron ous t o the rising edge of CKI.
LH543620 1024 × 36 Synchronous FIFO
10
T able 3. HF Synchronization Modes
CONTROL
REGISTER
FUNCTION
BIT 4 BIT 3
L * L * Asynchr onous Mode: HF
LH
Synchronous Mode I: HF is
synchr onou s to the risin g edge of CKO
HL
Synchronous Mode II: HF is
synchr onou s to the risin g edge of CKI
HH
* Default Mode
T abl e 4. Out put -Por t Address
ADO2ADO1ADO
0
SEL ECTION
DEFAULT VAL UE
(of the selected
REGISTER)
LLL
RBASE
register
0
LLH
ROFFSET
register
0
LHL
AF offset value
8
L H H Parity re giste r 0
HLL
AE offset value
8
HLH
Control
regis ter
1
HHL
Mailbox
0
HHH
Resour c e
regis ters r ead
disabled
Not applicable
PIN NAME DESCRIPTION
STATUS FLAGS SYNCHRONOUS TO THE INPUT CLOCK
FF
Full Flag. FF is synchronous to the rising edge of CKI. When asserted LOW , 1024 36-bit words of
the FIFO memo ry arr ay contain m eaningf ul dat a. When FF is asser t ed, writing da ta to the FIFO is
disabled.
AF
Almost-Full Flag. When asserted LOW , AF indica tes that t her e are at mo st ‘p’ vacant 36-bit
words remaining in the FIFO memory array, where ‘p’ is the value of the Alm ost-Fu ll-Of fset-Value.
AF has t wo synchronization modes depending on Bit 5 of the contro l register.
Bit 5 = 0
(Default ) Asynchr onou s Mode
Bit 5 = 1
: AF is synchr onou s to the rising edge of CKI.
HF
Half-Ful l Flag. When asserted LO W , ther e are at least 513 36-bit words in the FIFO memor y
array. HF has three synchroniza tion modes depending on Bits 3 and 4 of the control register. See
Table 3.
MFF
Mailbox-Full Fla g. MFF is synchronized to th e rising edge of CKI. When assert ed LOW, it
indicates that a new mail word has been placed in the mailbox.
CONTROL SIGNALS SYNCHRONOUS TO THE OUTPUT CLOCK
ENO1, ENO
2
Output - Port Enables. ENO1 and ENO2 are active HIGH, sync hr onous to the rising edg e of CKO.
Data is read fro m the FIFO memo ry array when bot h ENO1, ENO2 are a sserted.
NOTE: ENO1, ENO2 DO NOT ENABLE reading data from the Resource Registe r or the Mailbox.
ADO[2:0]
Output -Port Address. ADO[ 2: 0] specifies the Output-Port source/destination. See Table 4.
ADO[2: 0] is synchr onou s to the risin g edge of CKO.
NOTE: In order to read the resour ce regist er at the out put bus, BYE sho uld be deasserted and the
FIFO memory array sho uld be disabled.
1024 × 36 Synchronous FIFO LH543620
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Table 5. Output -Port Word-Width Selection
WSO1WSO
0
FUNCTION
LL
9-B it Data-Path
Width
Out p ut d a ta Q [ 8:0]
LH
18-Bit Dat a- Path
Width
Out p ut d a ta Q [ 17:0]
HL
36-Bit Dat a- Path
Width Wit h Byt eOrder-Rever sa l
Out p ut d a ta Q [ 35:0]
HH
36-Bit Dat a- Path
Width
Out p ut d a ta Q [ 35:0]
T able 6. Retra nsmi t Oper atio n Modes
RTMD1RTMD0OPERATION ACTION TAKEN
LL
Depth
Cascade
Mode
The Alm ost-Empt y
Flag is a handsh ake
signal for cascading
LH
Retransmit
(RBASE) +
(ROFFSET) → RP
HL
Retransmit
and Mark
(RBASE) +
(ROFFSET) → RP
and
(RBASE) +
(ROFFSET) →
RBASE
HH
Mark (RP) → RBASE
PIN NAME DESCRIPTION
CONTROL SIGNALS SYNCHRONOUS TO THE OUTPUT CLOCK (cont’d)
WSO[1:0]
Output-Port Word-Width Selection. WSO[ 1:0] is synchr onous to the rising edge of CKO.
WSO[1:0] selects the O utput -Por t Wor d-Widt h and cont r ols byte- ord er-r ever sal acco rding to
Tab le 5.
RTMD[1:0]
Retransm it Mode Contr ol. RTMD[1:0] is synchr onized to the rising edge of CKO. RTMD[1:0 ]
contr ols the plac ement of new contents int o the Read Pointer (RP) and/or the Ret rans mit Base
(RBASE) regist ers. Wheneve r Retransm it (RT) is assert ed, one of three operat ions is performed
according t o the setting of RTMD[1: 0] . See Table 6.
NOTES:
1. When RTM D[1: 0] is set to 0, the FIFO is in depth cascade mode, and the Ret ran smit
mechanism can not be used. In cascade m ode, the Almost -Empt y Flag is a han dshake signal f or
cascading. The Almost-Empt y Flag is used as an input to the ENI of the next FIFO in the chain.
2. In standard FIFO operation RTMD[ 1:0] must not be set to 0 and the Retransmit signal mus t be
HIGH.
RT
Retransm it. RT is synchronized t o the rising edge of CKO. When asser t ed LOW , RT causes one
of the Retransm it Mode operat ions to be perfor med, according to the encoding of RTMD[1: 0] . See
Tab le 6.
NOTE : When RTM D[ 1:0 ] = 0 (FIFO is in cascade mo de) RT is ignored.
LH543620 1024 × 36 Synchronous FIFO
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