Sharp LH28F800SGB-L10, LH28F800SGR-L70, LH28F800SGR-L10, LH28F800SGHR-L70, LH28F800SGHR-L10 Datasheet

- 1 -

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

DESCRIPTION

The LH28F800SG-L/SGH-L flash memories with
SmartVoltage technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F800SG-L/SGH-L
can operate at V

CC = 2.7 V and VPP = 2.7 V. Their

low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Their symmetrically-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for resident flash
arrays, SIMMs and memory cards. Their enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F800SG-L/SGH-L
offer three levels of protection : absolute protection
with V

PP at GND, selective hardware block locking,

or flexible software block locking.These alternatives
give designers ultimate control of their code security
needs.

FEATURES

• SmartVoltage technology
– 2.7 V, 3.3 V or 5 V V

CC

– 2.7 V, 3.3 V, 5 V or 12 V VPP

• High performance read access time
LH28F800SG-L70/SGH-L70
– 70 ns (5.0±0.25 V)/80 ns (5.0±0.5 V)/

85 ns (3.3±0.3 V)/100 ns (2.7 to 3.0 V)
LH28F800SG-L10/SGH-L10
– 100 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/

120 ns (2.7 to 3.0 V)

• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read

• Enhanced data protection features
– Absolute protection with V

PP = GND

– Flexible block locking
– Block erase/word write lockout during power

transitions

• SRAM-compatible write interface

• High-density symmetrically-blocked architecture
– Sixteen 32 k-word erasable blocks

• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/chip

• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I

CC

in static mode

• Automated word write and block erase
– Command user interface
– Status register

• ETOX

TM

∗

V nonvolatile flash technology

• Packages
– 48-pin TSOP TypeI (TSOP048-P-1220)

Normal bend/Reverse bend

–48-ball CSP(FBGA048-P-0808)

∗

ETOX is a trademark of Intel Corporation.

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

8 M-bit (512 kB x 16) SmartVoltage

Flash Memories

LH28F800SG-L/SGH-L
(FOR TSOP, CSP)

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 2 -

PIN CONNECTIONS

48-PIN TSOP (Type I)

(TSOP048-P-1220)

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE#

RP#

V

PP

WP#

RY/BY#

A

18

A17

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
NC
GND
DQ

15

DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A

0

A2

1

A

A3B

A

1C

A

0D

GND

E

CE#

A5

2

A6

A4

OE#

DQ

8

DQ0

A17

WP# WE#

3

A

7

DQ1

DQ2

DQ9

4

VPP

DQ10

DQ11

DQ3

5

RP#

NC

DQ12

VCC

DQ4

A8

6

NC

A9

DQ6

DQ5

DQ13

A11

7

A10

A12

DQ15

DQ14

DQ7

A14

8

A13

A15

A16

GND

NC

F

RY/BY#

A18

(FBGA048-P-0808)

48-BALL CSP

TOP VIEW

COMPARISON TABLE

VERSIONS

OPERATING TEMPERATURE

PACKAGE

WRITE PROTECT FUNCTION

LH28F800SG-L

0 to +70˚C

48-pin TSOP (I)

Controlled by

(FOR TSOP, CSP)

48-ball CSP WP# and RP# pins

LH28F800SGH-L

–40 to +85˚C

48-

pin

TSOP (I)

Controlled by

(FOR TSOP, CSP)

48-

ball

CSP

WP# and RP# pins

LH28F800SG-L

∗

1

0 to +70˚C 44-pin SOP Controlled by RP# pin

(FOR SOP)

∗1 Refer to the datasheet of LH28F800SG-L (FOR SOP).

NOTE :

Reverse bend available on request.

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 3 -

BLOCK DIAGRAM

Y GATING

Y DECODER

INPUT

BUFFER

OUTPUT
BUFFER

DQ0-DQ15

VCC

CE#
WE#
OE#
WP#
RP#

ADDRESS

LATCH

DATA

COMPARATOR

PROGRAM/ERASE
VOLTAGE SWITCH

STATUS

REGISTER

COMMAND

USER

INTERFACE

WRITE
STATE

MACHINE

DATA

REGISTER

OUTPUT

MULTIPLEXER

IDENTIFIER

REGISTER

ADDRESS
COUNTER

A0-A18

X DECODER

16

32 k-WORD

BLOCKS

RY/BY#

VCC
GND

V

PP

INPUT

BUFFER

I/O

LOGIC

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 4 -

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

A

0-A18 INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.

CE# INPUT

CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
RP# at V

HH allows to set permanent lock-bit. Block erase, word write, or lock-bit

configuration with V

IH < RP# < VHH produce spurious results and should not be

attempted.

OE# INPUT OUTPUT ENABLE : Controls the device's outputs during a read cycle.

WE# INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.

WP# INPUT

WRITE PROTECT : Master control for block locking. When V

IL, locked blocks cannot be

erased and programmed, and block lock-bits can not be set and reset.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, word write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and word write is inactive, word write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.

BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :

For erasing array blocks, writing words, or configuring lock-bits. With V

PP ≤ VPPLK,

memory contents cannot be altered. Block erase, word write, and lock-bit configuration
with an invalid V

PP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious

results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configured the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp V

CC down to GND and then

ramp V

CC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write

attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not internal connected; recommend to be floated.

DQ0-DQ15

INPUT/

OUTPUT

RP#

INPUT

RY/BY# OUTPUT

V

PP SUPPLY

V

CC SUPPLY

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

1 INTRODUCTION

This datasheet contains LH28F800SG-L/SGH-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800SG-L/
SGH-L flash memories documentation also includes
ordering information which is referenced in
Section 7.

1.1 New Features

Key enhancements of LH28F800SG-L/SGH-L
SmartVoltage flash memories are :

• SmartVoltage Technology

• Enhanced Suspend Capabilities

• In-System Block Locking

• Permanent Lock Capability,

Note following important differences :

•V

PPLK has been lowered to 1.5 V to support

3.3 V and 5 V block erase, word write, and lock­bit configuration operations. Designs that switch
V

PP off during read operations should make sure

that the V

PP voltage transitions to GND.

• To take advantage of SmartVoltage technology,
allow V

CC connection to 2.7 V, 3.3 V or 5 V.

• Once set the permanent lock bit, the blocks
which have been set block lock-bit can not be
erased, written forever.

1.2 Product Overview

The LH28F800SG-L/SGH-L are high-performance
8 M-bit SmartVoltage flash memories organized as
512 k-word of 16 bits. The 512 k-word of data is
arranged in sixteen 32 k-word blocks which are
individually erasable, lockable, and unlockable in­system. The memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of V

CC

and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.

2.7 to 3.6 V V

CC consumes approximately one-fifth

the power of 5 V V

CC. But, 5 V VCC provides the

highest read performance. V

PP at 2.7 V, 3.3 V and

5 V eliminates the need for a separate 12 V
converter, while V

PP = 12 V maximizes block erase

and word write performance. In addition to flexible
erase and program voltages, the dedicated V

PP pin

gives complete data protection when V

PP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations

Offered by SmartVoltage Technology

Internal VCC and VPP detection circuitry auto­matically configures the device for optimized read
and write operations.

A command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timing
necessary for block erase, word write, and lock-bit
configuration operations.

A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (5 V
V

CC, 12 V VPP) independent of other blocks. Each

block can be independently erased 100 000 times
(1.6 million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.

Writing memory data is performed in word
increments typically within 7.5 µs (5 V V

CC, 12 V

V

PP). Word write suspend mode enables the

system to read data from, or write data to any other
flash memory array location.

VCC VOLTAGE VPP VOLTAGE

2.7 V

2.7 V, 3.3 V, 5 V, 12 V

3.3 V 3.3 V, 5 V, 12 V
5 V 5 V, 12 V

- 5 -

- 6 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

The selected block can be locked or unlocked
individually by the combination of sixteen block lock
bits and the RP# or WP#. Block erase or word
write must not be carried out by setting block lock
bits and setting WP# to low and RP# to V

IH. Even

if WP# is high state or RP# is set to V

HH, block

erase and word write to locked blocks is prohibited
by setting permanent lock bit.

The status register or RY/BY# indicates when the
WSM’s block erase, word write, or lock-bit
configuration operation is finished.

The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, word write, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and word write is inactive), word
write is suspended, or the device is in deep power­down mode.

The access time is 70 ns (t

AVQV) at the VCC supply

voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F800SG-L)/
– 40 to +85°C (LH28F800SGH-L). At 4.5 to 5.5 V
V

CC, the access time is 80 ns or 100 ns. At lower

V

CC voltage, the access time is 85 ns or 100 ns

(3.0 to 3.6 V) and 100 ns or 120 ns (2.7 to 3.0 V).

The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I

CCR current is 1 mA at

5 V V

CC and 3 mA at 2.7 to 3.6 V VCC.

When CE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t

PHQV) is

required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t

PHEL)

from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.

Fig. 1 Memory Map

32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block
32 k-Word Block

7FFFF
78000

77FFF
70000

6FFFF
67FFF

68000
60000

5FFFF
58000

57FFF
50000

4FFFF
48000

47FFF
40000

3FFFF
38000

37FFF
30000

2FFFF
28000

27FFF
20000

1FFFF
18000

17FFF
10000

0FFFF
08000

07FFF
00000

15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

- 7 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

2 PRINCIPLES OF OPERATION

The LH28F800SG-L/SGH-L SmartVoltage flash
memories include an on-chip WSM to manage
block erase, word write, and lock-bit configuration
functions. It allows for : 100% TTL-level control
inputs, fixed power supplies during block erasure,
word write, and lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.

After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby, and output disable operations.

Status register and identifier codes can be
accessed through the CUI independent of the V

PP

voltage. High voltage on VPP enables successful
block erasure, word writing, and lock-bit
configuration. All functions associated with altering
memory contents — block erase, word write, lock­bit configuration, status, and identifier codes — are
accessed via the CUI and verified through the
status register.

Commands are written using standard micro­processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
word write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal verification, and margining
of data. Addresses and data are internally latched
during write cycles. Writing the appropriate
command outputs array data, accesses the
identifier codes, or outputs status register data.

Interface software that initiates and polls progress
of block erase, word write, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read/write

data from/to blocks other than that which is
suspended. Word write suspend allows system
software to suspend a word write to read data from
any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer
may choose to make the V

PP power supply

switchable (available only when memory block
erases, word writes, or lock-bit configurations are
required) or hardwired to V

PPH1/2/3. The device

accommodates either design practice and
encourages optimization of the processor-memory
interface.

When V

PP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase, word
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V

PP. All write

functions are disabled when V

CC is below the write

lockout voltage V

LKO or when RP# is at VIL. The

device’s block locking capability provides additional
protection from inadvertent code or data alteration
by gating erase and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in­system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes, or status register independent of the V

PP

voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power­down mode, the device automatically resets to read
array mode. Five control pins dictate the data flow
in and out of the component : CE#, OE#, WE#,

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the
device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ

0-DQ15) control and when active drives

the selected memory data onto the I/O bus. WE#
must be at V

IH and RP# must be at VIH or VHH.

Fig. 13 illustrates read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ

0-DQ15 are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ

0-DQ15 outputs are placed

in a high-impedance state independent of OE#. If
deselected during block erase, word write, or lock­bit configuration, the device continues functioning,
and consuming active power until the operation
completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t

PHQV is required

after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.

During block erase, word write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time t

PHWL is required

after RP# goes to logic-high (V

IH) before another

command can be written.

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
word write, or lock-bit configuration modes. If a
CPU reset occurs with no flash memory reset,
proper CPU initialization may not occur because
the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In
this application, RP# is controlled by the same
RESET# signal that resets the system CPU.

- 9 -

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

3.5 Read Identifier Codes

The read identifier codes operation outputs the
manufacture code, device code, block lock
configuration codes for each block, and the
permanent lock configuration code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms. The block lock and
permanent lock configuration codes identify locked
and unlocked blocks and permanent lock-bit setting.

Fig. 2 Device Identifier Code Memory Map

3.6 Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register.

The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.
Set Permanent and Block Lock-Bit commands
require the command and address within the device
(Permanent Lock) or block within the device (Block
Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address
within the device.

The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 14 and
Fig. 15 illustrate WE# and CE# controlled write
operations.

4 COMMAND DEFINITIONS

When the VPP ≤ VPPLK, read operations from the
status register, identifier codes, or blocks are
enabled. Placing V

PPH1/2/3 on VPP enables

successful block erase, word write and lock-bit
configuration operations.

Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.

7FFFF

78004
78003
78002
78001
78000

0FFFF

08004
08003
08002
08001
08000
07FFF

00004
00003
00002
00001
00000

Reserved for

Future Implementation

Block 15 Lock Configuration Code

Block 15

Block 1

Block 0

(Blocks 2 through 14)

Reserved for

Future Implementation

Reserved for

Future Implementation

Block 1 Lock Configuration Code

Reserved for

Future Implementation

Reserved for

Future Implementation

Permanent Lock Configuration Code

Block 0 Lock Configuration Code

Device Code

Manufacture Code

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

- 10 -

Table 2 Bus Operations

MODE NOTE RP# CE# OE# WE#

ADDRESS

V

PP

DQ

0-15

RY/BY#

Read 1, 2, 3, 8

VIHor V

HH

V

IL

V

IL

V

IH

XXD

OUT

X

Output Disable 3

VIHor V

HH

V

IL

V

IH

V

IH

X X High Z X

Standby 3

VIHor V

HH

V

IH

XXXXHigh Z X

Deep Power-Down 4 VIL XXXXXHigh Z V

OH

Read Identifier Codes 8

VIHor V

HH

V

IL

V

IL

V

IH

See Fig. 2

X(

NOTE 5)

V

OH

Write 3, 6, 7, 8

VIHor V

HH

V

IL

V

IH

V

IL

XXDINX

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V

IL or VIH for control pins and addresses, and

V

PPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC

CHARACTERISTICS" for V

PPLK and VPPH1/2/3 voltages.

3. RY/BY# is V

OL when the WSM is executing internal

block erase, word write, or lock-bit configuration
algorithms. It is V

OH during when the WSM is not busy,

in block erase suspend mode (with word write inactive),
word write suspend mode, or deep power-down mode.

4. RP# at GND±0.2 V ensures the lowest deep power­down current.

5. See Section 4.2 for read identifier code data.

6. V

IH < RP# < VHH produce spurious results and should

not be attempted.

7. Refer to Table 3 for valid D

IN during a write operation.

8. Don’t use the timing both OE# and WE# are V

IL.

COMMAND

BUS CYCLES

NOTE

FIRST BUS CYCLE SECOND BUS CYCLE

REQ’D.

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 5 Write BA 20H Write BA D0H
Word Write 2 5, 6 Write WA

40H or 10H

Write WA WD

Block Erase and

1 5 Write X B0H

Word Write Suspend
Block Erase and

1 5 Write X D0H

Word Write Resume
Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H
Set Permanent Lock-Bit 2 7 Write X 60H Write X F1H
Clear Block Lock-Bits 2 8 Write X 60H Write X D0H

Table 3 Command Definitions

(NOTE 9)

NOTES :

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever
goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read
operations access manufacture, device, block lock, and
permanent lock codes. See Section 4.2 for read
identifier code data.

5. If the block is locked and the permanent lock-bit is not
set, WP# must be at V

IH or RP# must be at VHH to

enable block erase or word write operations. Attempts to
issue a block erase or word write to a locked block while
WP# is V

IH or RP# is VHH.

6. Either 40H or 10H is recognized by the WSM as the
word write setup.

7. If the permanent lock-bit is set, WP# must be at V

IH or

RP# must be at V

HH to set a block lock-bit. RP# must

be at V

HH to set the permanent lock-bit. If the permanent

lock-bit is set, a block lock-bit cannot be set. Once the
permanent lock-bit is set, permanent lock-bit reset is
unable.

8. If the permanent lock-bit is set, clear block lock-bits
operation is unable. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the permanent
lock-bit is not set, the Clear Block Lock-Bits command
can be done while WP# is V

IH or RP# is VHH.

9. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

4.1 Read Array Command

Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, word write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Word
Write Suspend command. The Read Array
command functions independently of the V

PP

voltage and RP# can be VIH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and permanent lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the V

PP voltage and RP# can be

V

IH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

NOTES :

1. X selects the specific block lock configuration code to be
read. See Fig. 2 for the device identifier code memory map.

2. Block lock status and permanent lock status are output
by DQ

0. DQ1-DQ15 are reserved for future enhancement.

4.3 Read Status Register Command

The status register may be read to determine when
a block erase, word write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs. OE# or CE# must toggle to
V

IH before further reads to update the status

register latch. The Read Status Register command
functions independently of the V

PP voltage. RP#

can be V

IH or VHH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.

To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V

PP voltage. RP# can

be V

IH or VHH. This command is not functional

during block erase or word write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,

CODE ADDRESS DATA

Manufacture Code 00000H 00B0H
Device Code 00001H 0050H
Block Lock Configuration

(NOTE 2)

XX002H

(NOTE 1)

•Unlocked DQ0 = 0

•Locked DQ0 = 1

•

Reserved for future enhancement

DQ1-15

Permanent Lock Configuration

(NOTE 2)

00003H

•Unlocked DQ0 = 0

•Locked DQ0 = 1

•

Reserved for future enhancement

DQ1-15

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.

This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when V

CC =

V

CC1/2/3/4 and VPP = VPPH1/2/3. In the absence of

this high voltage, block contents are protected
against erasure. If block erase is attempted while
V

PP ≤ VPPLK, SR.3 and SR.5 will be set to "1".

Successful block erase requires that the
corresponding block lock-bit be cleared or, if set,
that WP# = V

IH or RP# = VHH. If block erase is

attempted when the corresponding block lock-bit is
set and WP# = V

IL and RP# = VIH, SR.1 and SR.5

will be set to "1". Once permanent lock-bit is set,
the blocks which have been set block lock-bit are
unable to erase forever. Block erase operations
with V

IH < RP# < V HH produce spurious results and

should not be attempted.

4.6 Word Write Command

Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the

completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.

When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.

Reliable word writes can only occur when V

CC =

V

CC1/2/3/4 and VPP = VPPH1/2/3. In the absence of

this high voltage, memory contents are protected
against word writes. If word write is attempted while
V

PP ≤ VPPLK, status register bits SR.3 and SR.4 will

be set to "1". Successful word write requires that
the corresponding block lock-bit be cleared or, if
set, that WP# = V

IH or RP# = VHH. If word write is

attempted when the corresponding block lock-bit is
set and WP# = V

IL and RP# = VIH, SR.1 and SR.4

will be set to "1". Once permanent lock-bit is set,
the blocks which have been set block lock-bit are
unable to write forever. Word write operations with
V

IH < RP# < VHH produce spurious results and

should not be attempted.

4.7 Block Erase Suspend Command

The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to V

OH.

Specification t

WHRH2 defines the block erase

suspend latency.

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LH28F800SG-L/SGH-L (FOR TSOP, CSP)

At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to V

OL.

However, SR.6 will remain "1" to indicate block
erase suspend status.

The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V

OL. After the Erase

Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). V

PP must remain at VPPH1/2/3

(the same VPP level used for block erase) while
block erase is suspended. RP# must also remain at
V

IH or VHH (the same RP# level used for block

erase). WP# must also remain at V

IL or VIH (the

same WP# level used for block erase). Block erase
cannot resume until word write operations initiated
during block erase suspend have completed.

4.8 Word Write Suspend Command

The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will

also transition to V

OH. Specification tWHRH1 defines

the word write suspend latency.

At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while word write is suspended are Read
Status Register and Word Write Resume. After
Word Write Resume command is written to the
flash memory, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear and RY/BY# will return to
V

OL. After the Word Write Resume command is

written, the device automatically outputs status
register data when read (see Fig. 6). V

PP must

remain at V

PPH1/2/3 (the same VPP level used for

word write) while in word write suspend mode. RP#
must also remain at V

IH or VHH (the same RP#

level used for word write). WP# must also remain
at V

IL or VIH (the same WP# level used for word

write).

4.9 Set Block and Permanent Lock­Bit Commands

The combination of the software command
sequence and hardware WP#, RP# pin provides
most flexible block lock (write protection) capability.
The word write/block erase operation is restricted
by the status of block lock-bit, WP# pin, RP# pin
and permanent lock-bit. The status of WP# pin,
RP# pin and permanent lock-bit restricts the set
block bit. When the permanent lock-bit has not
been set, and when WP# = V

IH or RP# = V HH, the

block lock bit can be set with the status of the RP#
pin. When RP# = V

HH, the permanent lock-bit can

be set with the permanent lock-bit set command.
After the permanent lock-bit has been set, the
write/erase operation to the block lock-bit can never
be accepted. Refer to Table 5 for the hardware
and the software write protection.

Set block lock-bit and permanent lock-bit are
executed by a two-cycle command sequence. The