Sharp LH28F800BVB-TTL90 Datasheet

PRODUCT SPECIFICATIONS

Integrated Circuits Group

LH28F800BVB-TTL90

Flash Memory

8M (1M × 8/512K × 16)

(Model No.: LHF80V07)

Spec No.: EL114067

Issue Date: August 27, 1999

SHARP

LHFSOVO7

@Handle this document carefully for it contains material protected by international copyright law.

Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.

l When using the products covered herein, please observe the conditions written herein and the

precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions.

(1) The products covered herein are designed and manufactured for the following application

areas. When using the products covered herein for the equipment listed in Paragraph (2),

even for the following application areas, be sure to observe the precautions given in

Paragraph (2). Never use the products for the equipment listed in Paragraph (3).

*Office electronics *Instrumentation and measuring equipment *Machine tools

*Audiovisual equipment *Home appliance *Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment which

demands high reliabilitv, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system.

*Control and safety devices for airplanes, trains, automobiles, and other

transportation equipment *Mainframe computers *Traffic control systems

l Gas leak detectors and automatic cutoff devices *Rescue and security equipment *Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands

extremely high performance in terms of functionality, reliability, or accuracy.

*Aerospace equipment l Communications equipment for trunk lines *Control equipment for the nuclear power industry l Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above three

Paragraphs to a sales representative of the company.

@Please direct all queries regarding the products covered herein to a sales representative of the

company.

Rev. 1.1

SliARP

LHF80V07

CONTENTS

PAGE

1 INTRODUCTION.. ...........................................................

1. I Features ........................................................................

1.2 Product Overview.. ......................................................

2 PRINCIPLES

2.1 Data Protection..

3 BUS OPERATION ...........................................................

3.1 Read.. ...........................................................................

3.2 Output Disable..

3.3 Standby

3.4 Deep Power-Down..

3.5 Read Identifier Codes Operation..

3.6 Write..

4 COMMAND

4.1 Read Array Command ................................................

4.2 Read Identifier Codes Command

4.3 Read Status Register Command..

4.4 Clear Status Register Command ................................. 12

4.5 Block Erase Command..

4.6 Word/Byte Write Command..

4.7 Block Erase Suspend Command

4.8 Word/Byte Write Suspend Command..

4.9 Considerations of Suspend.. ....................................... 14

4.10 Block Locking.. ........................................................ 14

4.10.1 V,,=V,, for Complete Protection..

4.10.2 WP#=V,, for Block Locking.. ............................

4.10.3 WP#=V,, for Block Unlocking.. ........................ 14

OF OPERATION..

...........................................................

......................................................................... 8

..................................................... 8

.............................................

DEFINITIONS..

.....................................

...............................

. ............................

................

.............................................

.: .........................

............................... 12

..................................... 13

................................ 13

...................... 14

....................

.8 .8

.9 .9

14 14

PAGE

5 DESIGN CONSIDERATIONS

5.1 Three-Line Output Control .......................................

5.2 RY/BY# and Block Erase and Word/Byte Write

Polling.. .................................................................... 20

5.3 Power Supply Decoupling ........................................

5.4 V,, Trace on Printed Circuit Boards ........................ 20

5.5 V,, . V,,, RP# Transitions.. ..................................... 21

5.6 Power-Up/Down Protection..

5.7 Power Dissipation..

6 ELECTRICAL SPECIFICATIONS ............................... 22

6.1 Absolute Maximum Ratings ..................................... 22

6.2 Operating Conditions

6.2.1 Capacitance.. ....................................................... 22

6.2.2 AC Input/Output Test Conditions

6.2.3 DC Characteristics ..............................................

6.2.4 AC Characteristics - Read-Only Operations.. ..... 26

6.2.5 AC Characteristics - Write Operations

6.2.6 Alternative CE#-Controlled Writes..

6.2.7 Reset Operations .................................................

6.2.8 Block Erase and Word/Byte Write Performance 34

7 PACKAGE AND PACKING SPECIFICATIONS ......... 35

................................................... 21

...................................... 20

....................................

................................................

....................... 23

............... 29

...................

2 1

3 1 33

Rev. 1.1

SHARIP

LH28F8OOBVB-TTL90

8M-BIT (1Mbit x 8 / 5 12Kbit x 16)

Smart3 Flash MEMORY

n Smart3 Technology

- 2.7V-3.6V Vcc

2.7V-3.6V or 11.4V-12.6V Vpp n User-Configurable x8 or x 16 Operation n High-Performance Access Time

- 90ns(2.7V-3.6V)

n Operating Temperature

- 0°C to +7O”C

n Optimized Array Blocking Architecture

Two 4K-word Boot Blocks

Six 4K-word Parameter Blocks

Fifteen 32K-word Main Blocks

Top Boot Location

n Extended Cycling Capability

100,000 Block Erase Cycles

n Enhanced Automated Suspend Options

Word/Byte Write Suspend to Read

Block Erase Suspend to Word/Byte Write

Block Erase Suspend to Read

LHF80V07

n Enhanced Data Protection Features

n Automated Word/Byte Write and Block Erase

n Low Power Management

n SRAM-Compatible Write Interface n Chip Size Packaging

n ETOXTM* Nonvolatile Flash Technology n CMOS Process (P-type silicon substrate)

n Not designed or rated as radiation hardened

Absolute Protection with Vpp=GND

Block Erase and Word/Byte Write Lockout during Power Transitions

Boot Blocks Protection with WP#=VIL

Command User Interface

- Status Register

Deep Power-Down Mode

Automatic Power Savings Mode Decreases ICC in Static Mode

- 48-Ball CSP

SHARP’s LH28F800BVB-TTL90 Flash memory with Smart3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F800BVB-TTL90 can operate at V,,=2.7V-3.6V and V,,=2.7V-3.6V Its low voltage operation capability realize battery life and suits for cellular phone application.

Its Boot. Parameter and Main-blocked architecture, flexible voltage and extended cycling provide for highly flexible :omponent suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either lirectly executed out of flash or downloaded to DRAM, the LH28F8OOBVB-TTL90 offers two levels of protection: absolute lrotection with V,, at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their :ode security needs.

Ihe LH28F800BVB-TTL90 is manufactured on SHARP’s 0.35um ETOXTM* process technology. It come in chip-size lackage: the 48-ball CSP ideal for board constrained applications.

“ETOX is a trademark of Intel Corporation

Rev. 1.1

SHARP

LHF8OVO7 3

1 INTRODUCTION

This datasheet contains LH28F800BVB-TI’L90 specifications. Section 1 provides a flash memory overview. Sections 2,3,4 and 5 describe the memory organization and functionality. Section 6 covers electrical specifications.

1.1 Features

Key enhancements of LH28F8OOBVB-TTL90 Smart3 Flash memory are:

*Smart3 Technology *Enhanced Suspend Capabilities *Boot Block Architecture

Please note following important differences:

VPPLK has been lowered to 1.5V to support 2.7V-3.6V block erase and word/byte write operations. The V,, voltage transitions to GND is recommended for

designs that switch V,, off during read operation.

*To take advantage of Smart3 technology, allow V,,

and V,, connection to 2.7V-3.6V.

1.2 Product Overview

The LH28F800BVB-TTL90 is a high-performance 8M-bit Smart3 Flash memory organized as lM-byte of 8 bits or 512K-word of 16 bits. The lM-byte/512K-word of data is uranged in two 8K-byte/4K-word boot blocks, six SKJytel4K-word parameter blocks and fifteen 64K-byte/32Kword main blocks which are individually erasable intystem. The memory map is shown in Figure 3.

Smart3 technology provides a choice of V,, and V,, :ombinations, as shown in Table 1, to meet system xrformance and power expectations. V,, at 2.7V-3.6V :liminates the need for a separate 12V converter, while

V,,=12V maximizes block erase and word/byte write performance. In addition to flexible erase and program voltages. the dedicated V,, pin gives complete data protection when VPplVPPLK.

Table 1. V,, and V,, Voltage Combinations Offered by

Smart3 Technoloav

V,, Voitage

2.7V-3.6V 1 2.7V-3.6V, 11.4V-12.6V 1

Internal V,, and V,, detection Circuitry automatically configures the device for optimized read and write operations.

A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and word/byte write operations.

A block erase operation erases one of the device’s 32Kword blocks typically within 0.51s (2.7V-3.6V V,,,

11.4V-12.6V V,,), 4K-word blocks typically within 0.3 1s (2.7V-3.6V V,,, 11.4V-12.6V V,,) independent of other blocks. Each block can be independently erased 100,000

times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block.

Writing memory data is performed in word/byte increments of the device’s 32K-word blocks typically within 12.6~~ (2.7V-3.6V V,,, 11.4V-12.6V V,,), 4Kword blocks typically within 24.5~~ (2.7V-3.6V V,,,

11.4V-12.6V V,,). Word/byte write suspend mode

enables the system to read data or execute code from any other flash memory array location.

LzJ

V,, Voltage

Rev. 1.1

SHARP

LHF8OVO7 4

The boot blocks can be locked for the WP# pin. Block erase or word/byte write for boot block must not be carried

out by WP# to Low and RP# to V,,.

The status register indicates when the WSM’s block erase or word/byte write operation is finished.

The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status

(versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase or word/byte write. RY/BY#-high Z indicates that the WSM is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in deep power-down mode.

The access time is 90ns (tAv temperature range (O’C to +70 43 range of 2.7V-3.6V.

v) over the commercial ) and V,, supply voltage

The Automatic Power Savings (APS) feature substar&& reduces active current when the device is in static modf (addresses not switching). In APS mode, the typical I,, current is 3 mA at 2.7V V,,.

When CE# and RP# pins are at V,-,, the I,, CM05 standby mode is enabled. When the RP# pin is at GND

deep power-down mode is enabled which minimize: power consumption and provides write protection during reset. A reset time (tpHQv) high until outputs are valid. Likewise, the device has i wake time (tpHEL ) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset ant the status register is cleared.

The device is available in 48-ball CSP (Chip Size Package). Pinout is shown in Figure 2.

is required from RP# switching

Rev. 1.1

SHARP

LHF8OVO7 5

DUO-DQls

A 0 A?

0 Al

D 0 Ao

F 0 CE#

OE#

DQ8

DQo

Figure 1. Block Diagram

DQ6

DQ5

Ql?

All

AIO

Al?

DQ7

.%‘I

AI?

Al5

A16

4%BALL CSP

PINOUT

8mm x 8mm

TOP VIEW

Figure 2. CSP #-Ball Pinout

Rev. 1.1

SHARP

Symbol

A-,

Ao-Al8

DQo-DQ,,

CE#

RP#

OE#

WE# INPUT

WP# INPUT

BYTE# INPUT

RY/BY#

VCC

Type

INPUT

INPUT/

OUTPUT

INPUT

OPEN

DRAIN

DUTPUT

SUPPLY

SUPPLY GND

LHF8OVO7

Table 2. Pin Descriptions

Name and Function

ADDRESS INPUTS: Addresses are internally latched during a write cycle.

A-1

Ao-Alo

All-*,, .

DATA INPUT/OUTPUTS: DQo-DQ-/:Inputs data and commands during CUI write cycles; outputs data during memory array,

status

deselected or outputs are disabled. Data is internally latched during a write cycle. DQs-DQ, j:Inputs data during CUI write cycles in xl6 mode; outputs data during memory array read cycles in x 16 mode; not used for status register and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled. or in x8 mode (Byte#=V,,J Data is intemallv latched during a write cvcle.

CHIP ENABLE: Activates the device’s control logic. input buffers, decoders and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels.

RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. With RP#=V,,, block erase or word/byte write can operate to all blocks without WP# state. Block erase or word/byte write with Vt,<RP#<V,B produce spurious results and should not be attempted.

OUTPUT ENABLE: Gates the device’s outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and atray blocks. Addresses and data are latched on

the rising edge of the WE# uulse. WRITE PROTECT: Master control for boot blocks locking. When V,. locked boot blocks cannot

be erased and Droerammed. BYTE ENABLE: BYTES V,, places device in x8 mode. All data is then input or output on DQ,,.

and DQ8-t5 float. BYTE# V,, places the device in x16 mode , and turns off the A-, input buffer. READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an

internal operation (block erase or word/byte write). RY/BY#-high Z indicates that the WSM is ready for new commands, block erase is suspended. and word/byte write is inactive, word/byte write is suspended, or the device is in deep power-down mode.

BLOCK ERASE AND WORD/BYTE WRITE POWER SUPPLY: For erasing array blocks or writing words/bytes. With V,,IV,,,,. memory contents cannot be altered. Block erase and word/byte write with an invalid V,, (see DC Characteristics) produce spurious results and should not be attempted.

DEVICE POWER SUPPLY: Do not float any power pins. With V&V,,,, all write attempts to the flash memory are inhibited. Device operations at invalid V,, voltage (see DC Characteristics) oroduce sourious results and should not be attemuted.

GROUND: Do not float any ground pins. NO CONNECT: Lead is not internal connected; it may be driven or floated.

: Byte Select Address. Not used in x16 mode. : Row Address. Selects 1 of 2048 word lines. . Column Address. Selects 1 of 16 bit lines.

Rev. I.1

SHARP

LHF80V07 7

2 PRINCIPLES OF OPERATION

The LH28F800BVB-TTL90 Smart3 Flash memory includes an on-chip WSM to manage block erase and word/byte write functions. It allows for: 100% TTL-level control inputs. fixed power supplies during block erasure and word/byte write, and minimal processor overhead with RAM-like interface timings.

After initial device power-up or return from deep powerdown mode (see Bus Operations). the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations.

Status register and identifier codes can be accessed through the CUI independent of the V,, voltage. High voltage on VP, enables successful block erasure and word/byte writing. All functions associated with altering memory contents-block erase, word/byte write, status and identifier codes-are accessed via the CUI and verified through the status register.

Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase and word/byte write. The internal algorithms are regulated by the WSM. including pulse repetition, internal verification and margining of data. Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data. accesses the identifier codes or outputs status register data.

Interface software that initiates and polls progress of block erase and word/byte write can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads

Ire again possible via the Read Array command. Block :rase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. Word/byte write suspend allows system ;oftware to suspend a word/byte write to read data from ury other flash memory array location.

tA18-&1 Top Boot

7FFFF

7FOO0

7EFFF

7EOOO

7DFFF

7DOOil

7CFFF

7coOO 7BFFF

7BOOQ

7AFFF

7.&m 79FFF

79000

78FFF

78OOa

77FFF

7oOw

6FFFF

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

-1oooo

3FFFF

38000

37FFF

3moo

ZFFFF

28000

27FFF

20000

IFFFF

18000 I

17FFF

1OQOO

OFFFF

08000

07FFF

00000

4K-word Boot Block 0

4K-word Boot Block 1 4K-word Parameter Block 4K-word Parameter Block 1 4K-word Parameter Block 4K-word Parameter Block 3 4K-word Parameter Block 4 4K-word Parameter Block

32K-word Main Block 0 32K-word Main Block 32K-word Main Block 2 32K-word Main Block 3 32K-word Main Block 4 32K-word Main Block 5

32K-word Main Block 6

32K-word Main Block

32K-word Main Block 8

32K-word Main Block 9

32K-word Main Block

32K-word Main Block 11

32K-word Main Block 12

32K-word Main Block 13

32K-word Main Block 14

Figure 3. Memory Map

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LHF8OVO7

2.1 Data Protection

Depending on the application, the system designer may choose to make the V,, power supply switchable (available only when memory block erases or word/byte writes are required) or hardwired to VPPHIR. The device accommodates either design practice and encourages optimization of the processor-memory interface.

When VPPIVPPLK. The CUI, with two-step block erase or word/byte write command sequences, provides protection from unwanted operations even when high voltage is applied to V,,. All write functions are disabled when V,, is below the write lockout voltage V,,, or when RP# is at V,,. The device’s boot blocks locking capability for WP# provides additional protection from inadvertent code or data alteration by block erase and word/byte write operations. Refer to Table 6 for write protection alternatives.

memory contents cannot be altered.

3 BUS OPERATION

The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

3.1 Read

[nformation can be read from any block, identifier codes Jr status register independent of the V,, voltage. RP# can 5e at either V,, or V,,.

The first task is to write the appropriate read mode :ommand (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up x after exit from deep power-down mode. the device automatically resets to read array mode. Six control pins dictate the data flow in and out of the component: CE#, 3E#, WE#, RP#, WP# and BYTE#. CE# and OE# must be Iriven active to obtain data at the outputs. CE# is the device selection control, and when active enables the ;elected memory device. OE# is the data output

DQorDQlj) control and when active drives the selected nemory data onto the I/O bus. WE# must be at V,, and iP# must be at V,, or V,,. L Figure 11 12 illustrates read , :ycle.

3.2 Output Disable

With OE# at a logic-high level (V,,), the device outputs are disabled. Output pins (DQ,-DQ,,) are placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VrH) places the device in standby mode which substantially reduces device power consumption. DQO-DQ,, outputs are placed in a highimpedance state independent of OE#. If deselected during block erase or word/byte write. the device continues functioning, and consuming active power until the operation completes.

3.4 Deep Power-Down

RP# at V, initiates the deep power-down mode. In read modes, RP#-low deselects the memory. places

output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of

loons. Time tpHQV down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H.

During block erase or word/byte write modes? RP#-low will abort the operation. RY/BY# remains low until the

reset operation is complete. Memory contents being

altered are no longer valid; the data may be partially

erased or written. Time tpHwL is required after RP# goes to logic-high (V,,) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase or word/byte write modes. If a CPU reset occurs with no flash memory reset. proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

is required after return from power-

Rev. 1.1

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LHF8OVO7 9

.5 Read Identifier Codes Operation 3.6 Write

he read identifier codes operation manufacturer code and device code (see Figure 4). Using le manufacturer and device codes, the system CPU can ltomatically match the device with its proper algorithms.

Device Code

Manufacturer Code

Figure 4. Device Identifier Code Memory Map

outputs

the

Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection ant clearing of the status register. When V,-=2.7V-3.6V ant VPt,=VPPH1,2, the CUI additionally controls block erasure and word/byte write.

The Block Erase command requires appropriate commanc data and an address within the block to be erased. The Word/Byte Write command requires the command and address of the location to be written.

The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 13 and 14 illustrate WE# and CE# controlled write operations.

4 COMMAND DEFINITIONS

When the V,, voltage IV,,,,. Read operations from the

status register, identifier codes, or blocks are enabled. Placing VP,,,,* on V,, enables successful block erase and word/byte write operations.

Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands.

Rev. 1.1

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LHF8OV07

Table 3.1. Bus Operations(BYTE#=Vu.,)(l,z)

Mode

Read

Output Disable Standby

Deep Power-Down

Read Identifier Codes

Write

Notes RP# CE# OE# WE# Address V,,

4,lO

6,7,8

‘I, Or

VU,

‘1, Or

‘HH

‘1, Or

vnH

VI,

‘1, Or

vIiH

VIEI Or

‘HH

VI, VI, ‘1,

VI, VI,

‘1,

X X X

‘1,

X X

VI, VI, ‘1,

VI, vIH VI,

X X

See

Figure 4

X X

X X High Z X X High Z X

X High Z High Z X

Table 3.2. Bus Operations(BYTE#=VIL)(1,2)

Mode

Read

Output Disable

Standby Deep Power-Down

Read Identifier Codes Write

Notes

4,lO

8.9

fj 7 8

> >

RP# CE# OE#

vIH Or

VHH

vIH Or

VHH

‘1, Or

vHH

VI,

vIH Or

‘HH

VIHor

vHH

VI, VI, ‘1,

VIL ‘1, ‘IH

‘1,

X X X X

VI, VI, ‘1,

VIL ‘1, VIL

WE# Address

X X

X X X HighZ HighZ X

See

Figure 4

X X

DQ,, DQ,-,, RY/BY#(3)-

Dour

X High Z High Z X X High Z High Z High Z X Note 5 High Z High Z

NOTES:

1. Refer to DC Characteristics. When V,,5V,,,,,

2. X can be VI, or VI, for control pins and addresses, and V,, or VPPHIjz

memory contents can be read, but not altered.

for V,,. See DC Characteristics for V,,, and

V,,,,,, voltages.

3. RY/BY# is V,, when the WSM is executing internal block erase or word/byte write algorithms, It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or deep power-down mode.

4. RP# at GNDk0.2V ensures the lowest deep power-down current.

5. See Section 4.2 for read identifier code data.

6. Command writes involving block erase or word/byte write are reliably executed when VPP=VPPH1/2 and V,,=2.7V-3.6V. Block erase or word/byte write with Vm<RP#<VHH produce spurious results and should not be attempted.

7. Refer to Table 4 for valid DIN during a write operation.

8. Never hold OE# low and WE# low at the same timing.

9. A-, set to VI, or VI, in byte mode (BYTE#=V,,).

lo. m# set to vIL or VI,.

DQ,,,5 RY/BY#c3)

DOUT

Note 5 High Z

DIN

High Z X

DIN

X X

Rev. 1.1

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LHF80V07 11

Table 4. Command Definitions(7)

NOTES:

1. BUS operations are defined in Table 3.1 and Table 3.2.

2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. A_, set to V,, or V,, in Byte Mode (BYTE#=V,,).

BA=Address within the block being erased. The each block can select by the address pin A,, through A,, combination. WA=Address of memory location to be written.

3. SRD=Data read from status register. See Table 7 for a description of the status register bits.

WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID=Data read from identifier codes.

4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 foi

read identifier code data.

5. If the block is boot block, WP# must be at V, or RP# must be at V,, to enable block erase or word/byte write

operations. Attempts to issue a block erase or word/byte write to a boot block while WP# is V,, or RP# is V,,.

5. Either 40H or 1OH are recognized by the WSM as the word/byte write setup.

7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be

used.

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Sharp LH28F800BVB-TTL90 Datasheet

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