Page 1
SERVICE MANUAL
CODE: 00ZERA57VOSME
ER-A570 OPTION
SRN (IN-LINE) INTERFACE
MODEL ER-A6IN
RS-232 INTERFACE
MODEL ER-A5RS
CONTROL ROM
MODEL ER-A57R1
(For "V" version)
I. SRN (IN-LINE) SYSTEM FOR ER-A570 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
II. RS-232 SYSTEM FOR ER-A570 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
III. TEST FUNCTION FOR ER-A6IN AND ER-A5RS . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
IV. HARDWARE DESCRIPTION FOR ER-A6IN AND ER-A5RS . . . . . . . . . . . . . . . . . 4-1
PARTS GUIDE
CONTENTS
SHARP CORPORATION
This document has been published to be used for
after sales service only.
The contents are subject to change without notice.
Parts marked with "! " is important for maintaining the safety of the set. Be sure to replace these parts with specified
ones for maintaining the safety and performance of the set.
Page 2
●Precautions
1. Downloading the data from the ER-02FD in the inline system
To download the data from the ER-02FD onto the ECR in the i nline system, the following procedure
must be observed.
1) Download the data from the ER-02FD onto the ECR using the SRV #998.
2) Execute the SRV RESET operation.
3) Execute either the INLINE RAM CLEAR operation (#899) or the INLINE SET UP 1 JOB operation
(#895).
4) Check the SRV #970 to see if the ECR memory capacity exceeds the packaged RAM memory
capacity. If it does, add an optional RAM and follow the same procedure all over again from step 1).
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(Danish) ADVARSEL !
Lithiumbatteri – Eksplosionsfare ved fejlagtig håndtering.
Udskiftning må kun ske med batteri
af samme fabrikat og type.
Levér det brugte batteri tilbage til leverandoren.
(English) Caution !
Danger of explosion if battery is incorrectly replaced.
Replace only with the same or equivalent type
recommended by the equipment manufacturer.
Discard used batteries according to manufacturer’s instructions.
(Finnish) V AROITUS
Paristo voi räjähtää, jos se on virheellisesti asennettu.
Vaihda paristo ainoastaan laitevalmistajan suosittelemaan
tyyppiin. Hävitä käytetty paristo valmistajan ohjeiden
mukaisesti.
(French) ATTENTION
Il y a danger d’explosion s’ il y a remplacement incorrect
de la batterie. Remplacer uniquement avec une batterie du
même type ou d’un type recommandé par le constructeur.
Mettre au rébut les batteries usagées conformément aux
instructions du fabricant.
(Swedish) V ARNING
Explosionsfare vid felaktigt batteribyte.
Använd samma batterityp eller en ekvivalent
typ som rekommenderas av apparattillverkaren.
Kassera använt batteri enligt fabrikantens
instruktion.
CAUTION FOR BATTERY REPLACEMENT
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I. SRN (IN-LINE) SYSTEM FOR ER-A570
ER-A6IN
MODEL ER-A57R1 (For ER-A570)
(OPTIONS FOR ER-A570 )
CHAPTER 1. ER-A570 SRN (IN-LINE) SYSTEM CONFIGURATION . . . . . . . . . . 1-2
CHAPTER 2. HARDWARE REQUIREMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
CHAPTER 3. TRANSMISSION SYSTEM SPECIFICATIONS . . . . . . . . . . . . . . . . 1-3
CHAPTER 4. FILE/DATA ALLOCATION IN THE IN-LINE SYSTEM . . . . . . . . . . . 1-6
CHAPTER 5. PROGRAM DATA UPDATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
CHAPTER 6. SRV-MODE PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
CHAPTER 7. PGM2 MODE PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
CHAPTER 8. TROUBLESHOOTING JOBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
CHAPTER 9. READING (X) AND RESETTING (Z) REPORTS . . . . . . . . . . . . . . 1-17
CHAPTER 10. SOFTWARE INSTALLATION PRO CEDURE FO R
IN-LINE SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
CONTENTS
1 1
Page 5
CHAPTER 1. ER-A570 SRN (IN-LI NE) SYSTEM CONFIGURATION
The ER-A570 in-line system conforms to the SHARP Retail Network
that consists of a master and a maximum of 15 satellites (inclued the
one backup master).
Fig. 1-1
Drawer (max.3 units)
ER-A5R S
Modem/NCU
HOST
ER-A57R 1
Sharp
Retail
Network
ER-A570
ER-01RA/02 RA
ER-A570
ER-01RA/
ER-02RA
ER-A6IN
ER-A57R1
ER-A6IN
Master
Backup master
ER-01MB/02MB
ER-A57R 1
ER-A570
ER-01RA/
ER-02RA
ER-A6IN
Satellites
ER-01MB/02MB
ER-01M B/02MB
ER-03DW
ER-03RP or
ER-04RP
Kitc hi n prin ter
NOTE:
Master : 1 u nit
Satellite: Max. 15 units
ER-03RP/04R P: M ax. 9 uni ts
Satell ite+ER-03RP/04RP: Max. 15 units
CHAPTER 2. HARDWARE REQUIREMENTS
1.Master System
The following optional units are required to complete the master
system configuration.
The master may require additional RAM for allocati ng the IRC fil es.
1) ER-A6IN: SRN I/F control board
2) ER-01RA: Option RAM chip (32KB)
ER-02RA: Option RAM chip (128KB)
ER-01MB: Option RAM board (Max. 512K bytes)
ER-02MB: Option RAM board (1M bytes)
3) ER-A57R1: Option device control ROM (1 chip)
• The ROM chip (ER-A57R1) is installed on the main PWB of ER-
A570.
2. Satellite system (inclued the backup
master)
The following optional units are required to complete the Satellite
systems configuration.
The satellite may require additional RAM for allocat ing the IRC fi les .
1) ER-A6IN: SRN I/F control board
2) ER-01RA: Option RAM chip (32KB)
ER-02RA: Option RAM chip (128KB)
ER-01MB: Option RAM board (Max. 512K bytes)
ER-02MB: Option RAM board (1M bytes)
3) ER-A57R1: Option device control ROM (1 chip)
• The ROM chip (ER-A57R1) is installed on the main PWB of ER-
A570.
1 2
Page 6
3. Components
NO MANE PA RTS CODE Q’ty
1 PWB UNIT CPWBX7317RC01 1
2 PWB BRACKET LANGT7466RCZ Z 1
3 CONNECTOR BRACKET LANGT7510RCZ Z 1
4 SCREW (FOR HOLDING OF THE PWB AND PWB B RACKET) LX –BZ6665RCZZ 2
5
SCREW (FOR : PWB BRACKET AND PWB BRACKET, PWB BRACKET AND MAIN CHASSIS,
GND WIRE.)
LX–BZ6774R CZZ
5
6 WIRING TIE LBNDJ2004SCZ Z 1
7 SPACE R PSPAN7039XCZZ 1
8 FERRITE CORE (FOR INTERNAL CABLE) RCORF6666 RCZZ 1
9 INTERNAL CABLE QCNW–6856RCZ Z 1
10 BNC-T CONNECTOR QCNC–6811RC 0C 1
CHAPTER 3. TRANSMISSION
SYSTEM SPECIFICATIONS
1. Transmission Method
1) Carrier sense multiple access with collision detect (CSMA/CD)
2) Single channel, half duplex
3) High level data link controller (HDLC)
2. Transmission Medium
1) Topol ogy : Common Bus S ystem
2) Coaxial cable RG-58/u
3. Transmission Speed
480KBPS/1MBPS (Selectable) ... SRV mode JOB#922.
4. Data Transfer Method
Packet-data transfer method
Data side of 1 paket is MAX. 270 Byte.
5.Maximum Length of Transmission
Cable
1000m (3281 ft) . . . trunk cables + branch cables; however, branch
cable length is 10m (5m ✕ 2) for each terminal.
6. Max Terminals
16 Terminals max. (15 satellites, 1 master)
7. Physical Organization
The branch cable is not included in the standard accessories of the
ER-A6IN. Please order with the following code.
PA RTS CODE PRICE RANK DESCRIPTION
QCNW-6835RCZZ BM Branch cable
Fig. 3-1
Fig. 3-2 physical organization
5m (16.4ft)
QCNW-6835RCZZ
Satellite
*Master
R R
Tetminator
50
Ω
Trunk ca bles
Branch
cables
(5m x 2)
16.4ft.
x 2
Cable con nec t or
JJ cone ctor
Satellite Satellite Satellite
*NOTE: The master can be located anywhere within the SRN (IRC) network conf igurat ion.
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8. Packet F ormat
F
8 Bits
1 Opening flag (8 Bits) (01 111110) (7E)
DA
8 Bits
2 Destination address (00-FEH)
(SRN Terminal Number)
SA
8 Bits
3 Source address (00-FEH)
TYPE
8 Bits
4 Packet type (DA TA/ACK/RA CK /NRDY )
CH NO
8 Bits
5 Channel No. (01H = CH1; 02H = CH2)
DLS
8 Bits
6 Circuit status: Buffer full, RE-trans m it, Unable
7 Dummy
BCL
8 Bits
8 Number of bytes at the data unit
BCH
8 Bits
DATA
max.
270
bytes.
9 DATA
Number of data bytes (270 Bytes)
CRC
8 Bits
Φ CRC check code
CRC
8 Bits
F
8 Bits
Γ Closing flag (8 Bits) (01 111110) (7E)
Fig. 3-3 Packet format
1 Opening flag (7E)
The open flag (7E) is sent at the beginning of each packet. As the
SRN control circuit (receiving side) receives the flag, it will start
the receiving operation.
NOTE: The packet begins with the open flag (8 Bits) and ends
with a closing flag (8 Bits).
2 Destination address (00H – FEH)
The destination address indicates where the packet is addressed
(receiving unit) too. The terminal number of each unit is converted
into a hexadecimal number to be used for the destination address.
3 Source Address (00H – FEH )
The source address indicates the sending unit (transmit unit). The
terminal number of each unit is converted into a hexadecimal
number to be used for the source address.
4 Types of packets
There are four types of packets each are used to indicate the type
of packet to be transferred.
00: DATA packet
(summary and preset data)
01: ACK packet
The acknowledging packet that is sent to the transmitting
side from the receiving side to indicate that the packet was
received properly.
02: RACK packet
The acknowledging packet that will be sent to the receiving
side to indicate that the ACK packet has been properly
received by the sending side.
03: NRDY packet
The acknowledge packet that is sent to the sending side to
indicate that it is not ready to receive data.
5 Channel No.
Indicates that channel of the packet. (Channel 1 or Channel 2)
6 Circuit status
In the case of the NRDY packet, it indicates why the NRDY packet
was issued.
1) Unable to handle received data because the receiving side is
in the BUSY state.
2) Unable to handle received data because the receiving buffer is
full.
7 Number of data bytes
Indicates the number of bytes of data, which is a data, packet
status that will be converted into hexadecimal numbers before
transmission. Maximum number of bytes is 270.
8 Data
Transfer data is contained in this field. Size of data is limited to a
maximum of 270 bytes. It can only exi st in the data pac ket.
9 CRC check code
This check code is used to detect any errors in the transmit data.
A CRC code is generated from the sending side to be sent to the
receiving side.
At the receiving side, the CRC check code is generated on the
basis of the same formula as the sending side to verify it against
the CRC check code receive.
Φ Closing flag (7E)
The closing flag is sent at the end of the packet. When the IRC
control circuit at the receiving side receives the flag, it terminates
the operation.
9. Type of packet
Two types of packet formats are available for the SHARP RETAIL
NETWORK. One is the data packet (the content of data is judged by
the host level). The other is the control packet which is responded to
by the controller level and has three types of packets: ACK packet,
RACK packet and NRDY (NOT READY) packet.
(1) DATA packet: is used for sending and receiving data. Its con-
tents are judged at the host level.
(2) ACK packet: is a response sent from the sink station to the
source station by the link level (of DATA packet) when the DATA
packet is properly received.
(3) NRDY (NOT READY) packet is a response packet of the link
level. It is used in case it is unable to receive in the host level or
no space is available in its receive buffer despite the the error
check CRC of the DA TA packet is normal.
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Page 8
Fig. 3-4 Types of pac kets
10. Transmission Procedure
1 Normal sequence
2 Abnormal sequence-1
(when there is a single data error)
3 Abnormal sequence-2
(when there are six successive data errors)
Communication is disabled due to full retry counts . . . "PW-OFF"
(power off) will be printed on the master unit.
4 Abnormal sequence-3 (when ACK is i n error)
5 Abnormal sequence-4 (when RACK is in error)
Full ACK retry counts. If RACK were not detected after five retries
to send ACK, it assumes RACK to be in error, and so the receiv i n g
operation terminates normally.
6 Abnormal sequence-5
(receiving side not enabled to receive data)
11. Terminal Number Assi gnme nt
when the IRC option is installed, an IRC terminal number must also
be supplied. This number is in the range of 1 to 254. The number is
specified in the PGM 2 mode at installation time. It is necessary to
specify an number for each device connected to the IRC including the
master. It should be noted that the IRC terminal number and the
register number are not related. Section 10 of this manual indicates
how this number is specified.
• IRC termi nal number (3 digit s max.): *000 ∼ 254
*000: OFF line machine
• Register number (4 digit s max .): *0 ∼ 9999
*0: can not be used in the IRC operation.
F
DATA
packet
DA
SA
0
CH NO
DLS
BCL
BCH
DATA
CRC
CRC
F
F
ACK
packet
DA
SA
1
CH NO
DLS
0
0
CRC
CRC
F
PACK
packet
NRDY
(Not ready)
packet
F
DA
SA
1
CH NO
DLS
0
0
CRC
CRC
F
F
DA
SA
1
CH NO
DLS
0
0
CRC
CRC
F
Control packet
Data
ACK
RACK
[Seque nce] [Receiving side]
Data
X
Data
ACK
RACK
(Retry)
NOTE: X
Indicat es an erro r .
15ms
(No AC K)
Data
X
Data
(Retry-1)
15ms (No ACK)
X
Data
X
15ms
(No ACK)(Retry-5)
(No ACK)
ACKX
6ms
(No AC K)
ACK
Data
RACK
ACK-1
6ms
ACK-2
Data
RACK X
ACK-5
Data
NRDY
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CHAPTER 4. FILE/DATA ALLOCATION IN THE IN-LINE SYSTEM
(in the ER-A570, the shaded section ( )is not used.)
Fig. 4-1
∗ 1 ; In case of system report job disable on back-up master,
consolidation and receive files need not be created in back-up
master.
∗ 2 ; The clerk totalizer file only need to have one block s.
∗ 3 ; The clerk consolidation/receive/save files need not be created
in case of floating clerk system.
∗ 4 ; The sign on/off clerk file need not be created in case of
individual clerk system.
CHAPTER 5. PROGRAM DATA
UPDATING
1. General
There are two ways of updating the preset data for the ER-A570
in-line system.
1) To download the reset file of the master to a satellite after clearing
preset file of the slave.
This mode can be used at the time the machine is instal lat ion.
Fig. 5-1
2) To download the preset file of the master to the preset file of a
slave without clearing the slave"s preset file. (Downloading file
with a job number in 5000)
This mode can be used at the time of correcting preset data.
Data process on the satellite to which the master preset file is
downloaded
(a) When a preset file whose job number is 4000s is
downloaded, the contents of the corresponding file in the
satellite is zero cleared before saving the data received from
the master.
(b) When a preset file whose job number is 5000s is
downloaded, the contents of the corresponding file in the
satellite is replaced by the preset file sent from the mas t er.
Preset data
Preset data
Master Satellite
SRN
DEPT
Preset
totalizer
consoli dation
receive
save
TRAN
SACTION
Preset
totalizer
consoli dation
receive
save
PLU
Preset
totalizer
consoli dation
receive
save
SET
PLU
Preset
CLERK
Preset
totalizer
consoli dation
receive
save
HOURLY
Totalizer
consoli dation
receive
save
DAILY
NET
EAN/
UPC
Preset
totalizer
DYNAMIC
EAN/UPC
T.LOG
Loggin g da t a
CUST OMER
Totalizer
CASHIER
Preset
totalizer
consoli dati on
receive
save
SIGN ON/OFF
CLERK
RCV BUFFER
Preset
edit buffer
RCV.
GLU
BUFFER
GLU
FILE
B.T.
BUFFER
RESET
CLERK
Totalize r
receive
consoli dati on
RESET
CASHIER
LINK
PLU
Totalize r
consoli dati on
receive
save
Preset
totalizer
KITCHEN
PRINTER
GLU
BUFFER
Totalize r
receive
consoli dati on
DEPT
Preset
totalizer
save
TRAN
SACTION
PLU
SET
PLU
Preset
CLERK
HOURLY
Totalizer
save
DAILY
NET
EAN/
UPC
Preset
DYNAMIC
EAN/UPC
T.LOG
Loggin g da t a
CASHIER
Preset
totalizer
save
B.T.
BUFFER
RESET
CLERK
Totalizer
RESET
CASHIER
LINK
PLU
Totalizer
Preset
GLU
BUFFER
Totalizer
Preset
totalizer
save
Preset
totalizer
save
Preset
totalizer
save
Pr eset
edit buffer
KITCHEN
PRINTER
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2. Down-Loading Job List
List of Down load jobs
Mode Job Item Note
SRV 800 SRV parameter Including the machine
parameter relating to
inline operations.
("#902, #920 d" is not
downloaded.)
PGM2 secret code
preset
845 Training text CLK No.
850 Free Key layout
PGM 4100 Dept preset with clearing function
4119 Direct Dept/PLU key
4200 PLU/LINK/SET preset with clearing function
4300 Transaction preset with clearing function
4220 LINK PLU preset with clearing functi on
4221 SET PLU preset with clearing function
4400 Clerk preset
4600 Other preset
4610 Date, time
4614 Logo text
4644 Message text
4654 Guidance text
4700 TAX preset
4800 ONLINE preset
4950 IRC KP preset
4900 PGM preset relating to
inline operations
4999 All PGM preset
5100 Dept preset without clearing function
5200 PLU/LINK/SET preset without clearing function
5220 LINK PLU preset without clearing func t ion
5221 SET PLU preset without clearing function
5300 Transaction preset without clearing function
without clearing function
without clearing function
#4200 and #5200 don’t include stock data.
#4600 Other preset : Optional feature preset, VP preset, Hourly
report, Stack report, Secret code PGM1,
X1/Z1, X2/Z2, Auto key, PLU Level range.
#4400 exists in only clerk individual system.
#4200 include link PLU and set PLU presets.
3. Key operation
1) Down-loading of PGM-mode program data on
DEPT/PLU
(a) Down-loading to all the satellites in the system
NK2: Register No.
(b) Down-loading to the satellite specified
NK1: Register No.
NK2: Start code
NK3: End code
2) Down-loading of other program data
(a) Down-loading to all the satellites in the system
(b) Down-loading to the satellite specified
NK1: Register No.
4. Others
1) If a transmission error occurs, the machine number of a satellite in
which the error has occured is printed In that case, the manager
retry function becomes av ailable.
2) After transmission termination, the master prints the receipt/jour-
nal to that effect.
3) Broadcast communication
SRV mode down load job and PGM mode #4XXX (with clear job)
job is used by broadcast communication.
Broadcast communication met hod:
The master is communicated to all sat ell it es at a time.
The download of broardcast communication is as follows
a) Master downloads to all satellites.
(Broadcast communication)
<DISPLAY: SENDING>
b) All satellites receives the data.
c) Master checks communication error to each satellite.
(Normal cumminocation)
<DISPLAY : each register number>
NOTE: Setting of SRV mode programming JOB #920-C
"BROADCAST COMMUNICATION"
• When the ER-03RP/04RP is in the inline system, set up in
the following two methods*
1) Set JOB #920-C "BROADCAST COMMUNICATION" to
"NOTHING."
2) When performing broadcast downloading (#4XXX), turn
off the power of the ER-03RP/04RP, or turn off/on the
power of the ER-03RP/04RP after execution of
downloading.
(JOB#)
NK2
NK3
1 item
TL
ALL
X X
(JOB#)
TL
NK1
ST NK2
1 item
NK3
X X
(JOB#) TL
X
(JOB#) TL
NK1
ST
X
1 7
Page 11
CHAPTER 6. SRV-MODE PROGRAMMING
M: Master
S: Satellite
(JOB#)
TL
ABCD
X
0
No. Job# M/S Item Key sequence
1 #902 MRS = 0000 M/S 902-A: 1. Choice of inline
2 #918 MRS = 0000 M/S 918-A: 1. Printing of text of a tied PLU in set
PLU
2. Direct non tendering finalization after
previous tender entry
3. Output of set PLU to KP
M/S 918-B: 1. Red color printing on KP when PLU’s
unit price is zero
M/S 918-C: 1. Printing of Z counter on Z1/Z2 report
2. Comulating orders in KP
3. Printing the DEPT./PLU text on KP in
double size character
M/S 918-D: 1. Tip paid includes cash tip
2. Clearing of tip totalizer at clerk Z1
report
3. Printing of tip totalizer on the clerk
report
1. Inline 902-A
No 0
Ye s 1
1. Printing of
text of a
tied PLU in
set PLU
2. Direct non
tendering
finalization
after
previous
tender
entry
3. Output of
set PLU to
KP
918-A
Yes
Disable
By tied PLU 0
Set PLU’s KP 1
Enable
By tied PLU 2
Set PLU’s KP 3
No
Disable
By tied PLU 4
Set PLU’s KP 5
Enable
By tied PLU 6
Set PLU’s KP 7
1. Red color printing on KP when
PLU’s unit price is zero
918-B
No 0
Ye s 2
1. Printing of
Z counter
on Z1/Z2
report
2. Comulating
orders in KP
3. Printing
the
DEPT./PLU
text on KP
in double
size
character
918-C
Yes
Yes
No 0
Yes 1
No
No 2
Yes 3
No
Yes
No 4
Yes 5
No
No 6
Yes 7
1. Tip paid
includes
cash tip
2. Clearing
of tip
totalizer
at clerk
Z1 report
3. Printing
of tip
totalizer
on the
clerk
report
918-D
Yes
No
No 0
Yes 1
Yes
No 2
Yes 3
No
No
No 4
Yes 5
Yes
No 6
Yes 7
1 8
Page 12
No. Job# M/S Item Key sequence
3 #920 MRS = 0000 S 920-A: 1. Buck up master func tionS
M/S 920-B: 1. System report and down load job is
executed in the buck up master
2. The GLU finalization is executed in
the setellite
3. The clerk system
S 922-C: 1. Broad cast communication
2. PGM-mode programming at the
satellite
M/S 920-D: 1. Machine assignment
4 #922 MRS = 0008 M/S 922-A, B Not used. (Fixed at "00".)
922-C, D: 1. SRN transmission speed and
carrier-off waiting time
5 #923 MRS = 0000 M/S 923-A, B, C, D: Not used. (Fixed at "0000")
6 #924 MRS = 0000 M/S 924-A: 1. Report printing when consolidation
daily and periodic cashier reading or
resetting
2. PLU save file
1. Buck up master function 920-A
Not 0
Exit 1
1. System
report and
down load
job is
excuted in
the back
up master
2. The GLU
finalization
is
executed
in the
satellite
3. The clerk
system
920B
Disable
Enable
Centralized 0
Individual 1
Disable
Centralized 2
Individual 3
Enable
Enable
Centralized 4
Individual 5
Disable
Centralized 6
Individual 7
1. Broadcast
communication
2. PGM mode
programming at the
satellite
920-C
Exist
Disable 0
Enable 1
Nothing
Disable 4
Enable 5
1.Machine assignment 920-D
Standalone 0
Satellite 1
Master 2
Backup master 3
1. Transmission
speed
2. Carrier-off
waiting time
922-C,D
480K BPS
12.8 msec 00
3.2 msec 01
6.4 msec 02
9.6 msec 04
1M BPS
6.4 msec 08
1.6 msec 09
3.2 msec 10
4.8 msec 12
1. Report printing when
consolidation daily and
periodic cashier
reading or resetting is
taken.
2. PLU
save file
924-A
Printing of report on
individual register
Not 0
Exist 1
Printing of both i.e.
reports on individual
machines and
consolidation report on
the entire system
Not 4
Exist 5
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Page 13
No. Job# M/S Item Key sequence
6 #924 MRS = 0000 M/S 924-B: 1. Save file except for PLU
2. Programming whether or not to lock
REG mode entries after individual
daily total resetting
1 Locking after clerk resetting
2 Locking after term clerk resetting
924-C: 1. Programming whether or not to lock
REG mode entries after individual
daily total resetting. When the system
has no save file
1 Locking after hourly resetting
2 Locking after general resetting
924-D: 1. Programming whether or not to lock
REG mode entries after individual
periodic total resetting. When the
system has no save file
1 Locking after daily net resetting
2 Locking after general resetting
7 #925 MRS = 0000 M/S 925-A: 1. Selection of the method of daily total
general consolidation resetting at the
master
Method-1: Those data that has individually
been reset and the current sales
data are reset together
Method-2: Only those data that has individu-
ally been reset is reset
2. Clearing of the individual resetting
memory at the time of consolidation
daily total general resetting
Individual resetting memory=IRM
3. Execution of Job #199 when
consolidation daily total general
resetting has not been taken.
925-B: 1. Any entry operation is inhibited until
Job #199 is executed after consolidation daily total general resetting has
been taken.
2. Various individal resetting.
925-C: 1. Report printing when consolidation
daily and periodic total general
reading or resetting is taken.
1. Save file
except for
PLU
2. Locking
after clerk
resetting
3. Locking
after term
clerk
resetting
924-B
Not
Yes
Yes 0
No 1
No
Yes 2
No 3
Exit
Yes
Yes 4
No 5
No
Yes 6
No 7
1. Locking after hourly
resetting
2. Locking after general
resetting
924-C
Yes
Yes 0
No 1
No
Yes 2
No 3
1. Locking after hourly
resetting
2. Locking after general
resetting
924-D
Yes
Yes 0
No 1
No
Yes 2
No 3
1. Selection of
the method
of the daily
total gene ral
consolidation
resetting at
the master
2. Clearing of
the IRM
3. Execution of
Job#199
925-A
Method-1
Yes
Disable 0
Enable 1
No
Disable 2
Enable 3
Method-2
Yes
Disable 4
Enable 5
No
Disable 6
Enable 7
1. Any entry
operation is
inhibited until
job#199
2. Vari ous
individual
resetting
925-B
Yes
Disable 0
Enable 1
No
Disable 2
Enable 3
1. Report printing 925-C
Both i. e. report on individual
machines and Consolidation report
on the entire system.
0
Consolidation report on the entire
system
1
Report on individual register 2
1 10
Page 14
No. Job# M/S Item Key sequence
7 #925 MRS = 0000 M/S 925-D: 1. PLU stock control system
2. Resetting in the open store state.
<<Detailed descriptions of the parameter for Job #925>>
925-A 1 Method of daily general resetting of the enti re sy s tem at the mas t er:
It is specified whether only those data that has individually been reset or that data and the
current sales data should be reset when resetting of the entire sys t em is tak e.
Note here that if the machine is programmed to disable individual resetting (by B of
SRV-mode programming Job #925), not only individual resetting but also resetting of the
entire system cannot be achieved unless "Those data that has individually been reset and
the current sales data are reset together" has been selected.
2 Automatic clearing of the individual resetting memory at the time of consolidation daily
total general resetting No/Yes
The machine can be programmed to clear the individual resetting memory when general
Z1 resetting of the entire system is taken. If the memory is not cleared data is
accumulated each time individual resetting is taken until job #99 is executed.
3 Execution of Job #99 when consolidation daily total general resetting has not been taken
Enable/Disable:
Job #99 can be executed even if general Z1 resetting of the entire syst em is not tak en.
925-B 4 Any entry operation is inhibited until Job #99 is executed after consolidation or individual
daily total general resetting has been taken No/Yes:
This parameter enables the master to restrict the resetting job at satellites.
5 Individual resetting Enable/Disable:
The master alone can be made capable of resetting by selecting "Disable".
When selecting "Enable", or "Disable", however, the selection of the resetting method
mentioned
1 above should well be noted.
925-C 6 Type of printing of daily total and periodic total general X/Z reports:
The following three types are available:
a) Printing of only X/Z reports on individual machines
b) Printing of a consolidation X/Z report only
c) Printing of X/Z reports on individual machines, followed by the printing of a
consolidation X/Z report
Note: This programming 1 - 4 is valid for the system that has the save file.
Reading of SRV -mode program data
925-D 7 PLU stock control in the inline system
a) Stock control in inline system is available in two types: individual and centralized
systems.
b) Centralized stock control system
Program data only stock is only stored in the master.
Stock data in each satellite mus t be zero before a stock entry is made.
When a consolidaton report is taken, stock data in respective satellites are
consolidated and is add to stock data in the master.
Then the sum is printed.
Stock data in each satelli te is reset to z ero at this time.
Notice) In this system, stock counter in each satellite is always negative.
So, Entry which makes the PLU stock counter negative must be Allowed
unconditionally. (SRV. JOB#906-A)
c) Individual control system
Program data on stock is stored in the master and stellites, respectively.
When a consolidation report is taken, stock data in the master and satellites is
consolidated and printed.
The consolidation does not affect the stock data in the master.
1. PLU stock
control
system
2. Resetting in
the open
store state
925-D
Centralized
Disable 0
Enable 1
Individual
Disable 2
Enable 3
1 11
Page 15
931
937
TL
XXXX
X
No. Job# M/S Item Key sequence
8 #926 MRS=0004 M/S 926-A: 1. Sending "last void data" on KP
2. Sending "past void data" on KP
M/S 926-B: 1. Program reset in PGM2 mode
2. Sending "refund data" on KP
M/S 926-C: Not used (Fixed at "0")
926-D: 1. Dept./PLU text printing
2. Check VP
9 #931 MRS=0000
#937 MRS=0000
M/S 931: CONSOLIDATION Z1 COUNTER
937: CONSOLIDATION Z2 COUNTER
XXXX: Inital value for the counter.
10 #897 M/S Inline system in which kitchen printers alone are
connected.
• Function
a) In this inline system any inline job (consoli-
dation, down-loading, UP-loading, etc) is inhibited.
b) SRV parameter JOB#922 is set to "0008" pro-
gramming of the terminal number of the master.
K.P. preset file and K.P. edit buffer is created.
The above jobs, etc are performed.
c) The above system requires the following se-
lection in programming JOB#920-D. Register
is standalone. =0
11 #898 M/S Inline resetting
• Func ti on
This operation clears only the work memory
for inline operations.
The program memory for inline operations
re-mained uncharged even after the resetting
here is performed.
Inline communications can also be achieved.
897
X
TL
898
X
TL
1. Sending "last
void data" on
KP
2. Sending "past
void data" onKP926-A
Yes
Yes 0
No 1
No
Yes 2
No 3
1. Program
reset in
PGM2
mode
2. Sending
"refund
data" on KP
926-B
Disable
Yes 0
No 1
Enable
Yes 2
No 3
1. Dept./PLU
text printing
2. Check VP
format
926-D
Normal
Normal 0
Euro check 1
French check 2
German check 3
Double
Normal 4
Euro check 5
French check 6
German check 7
1 12
Page 16
No. Job# M/S Item Key sequence
12 #899 M/S Clearing the memories for inline operations.
• Function
This operation clears all the inline program
data memory and work memory.
After carrying out this clearing operation, any
inline communication is inhibited until the
necessary data for inline operations are
re-programmed.
This function automatically create the inline
files by following SR V pres et.
MASTER MACHINE : (SRV #920 D=2)
Consolidation file and the receive file is
created.
When clerk file is centraized, SIGN ON/OFF
CLERK file is created.
BACKUP MASTER MACHINE : (SRV #920
D=3)
RECEIVE GLU BUFFER is creat ed.
When clerk file is centraized, SIGN ON/OFF
CLERK file is created.
When system report/downloading job is
possible on backup master, consolidation file
and the receive file is created.
All machine :
When the system has the save file, the save
file is created.
File area is shifted to secure the work memory
for inline operation.
The "in use" flag of the clerk program data file
is cleared. (at the master)
All records in the clerk program data file are
erased.
(at the satellite)
13 #895 M/S Set ip 1 job operation Refer to CHAPTER 10.
899
X
TL
1 13
Page 17
CHAPTER 7. PGM2 MODE PROGRAMMING
No. Job# M/S Item Key sequence
1. #3610 M/S
• Terminal number
NK: Terminal No. = 0 ~ 254
2. #3611 M
• Mas ter li st (Generation)
NK1: Terminal No. = 1 ~ 254
NK2: Register No. = 1 ~ 999999
3. #3612 M
• Mas ter li st (Delect ion)
NK: Register No. = 1 ~ 999999
4. #3616 M
• Terminal number of the quest
check file buck-up master.
NK: Machine No. = 1 ~ 999999
NK = 0: When the back up master does not exist in the inline system.
MRS = 0
5. #3631 M
• Decide whether to enable or
disable the manager retry
function when a transmission
error occurs
NK:0 = Manager retry function ENABLE
1 = Manager retry function DISABLE MRS = 0
6. #3650 M/S
• Terminal number of K.P.
K.P.=Kitchine printer
NK1: K.P. No. = 1 ~ 9
NK2: Terminal No. = 0 ~ 254
∗NK2 = 0: When the K.P. delet ion
7. #3651 M/S
• Data trans mi ss ion of K .P.
NK1: K.P. No. = 1~9
NK2:
8. #3653 M/S
• Second K .P. No.
NK1: K.P. No. = 1 ~ 9
NK2: Second K.P. No. = 1 ~ 9
∗NK2 = 0: When the non second K.P .
3610
TL
NK
X
0
3611
ST
NK1
X
NK2
X
TL
3612 STNK
X
TL
3616
TL
NK
X
0
3631
TL
NK
X
0
3650
ST
NK1
X
NK2
X
TL
3651
ST
NK1
X
NK2
X
TL
3653
ST
NK1
X
NK2
X
TL
Data transmission NK2
Enable 0
Disable 1
1 14
Page 18
No. Job# M/S Item Key sequence
9. #3654 M/S
• K.P. name
NK 1: K.P. No. = 1~9
TEXT: Max. 12character
10. #3655 M/S
• Pri nt format for K.P.
11. #3610 M/S
• Inline preset reading
12. #3650 M/S
• Ki tchen print er preset readin g
3654
ST
NK1
X
TEXT
X
TL
Space
3655 ABC
X
TL
0000
3610
X
TL
3650
X
TL
A: PLU/DEPT code A C: Amount C
Print 0 Print 0
Skip 1 Skip 1
B: Unit price B
Print 0
Skip 1
1 15
Page 19
CHAPTER 8. TROUBLE SHOOTING J OBS
M : Master
S : Satellite
BM : Backup master
No. JOB# ITEM MODE S/M KEY SEQUENCE
1 #5810 Master declarat ion PGM2 BM/M
2 #5820 Recover declarat ion PGM2 BM/M
3 #5940 Clerk preset file in use flag foreed to clear PGM2 M
4 #5990 All item sales data mem ory manual clear PGM2 M/S
5 #5994 Clerk sales data memory manual clear PGM2 M/S
NK : Clerk No.
6 #5996 Hourly sales data memory manual clear PGM2 M/S
7 #5997 Daily net sales data memory manual clear PGM2 M/S
8 #5700 Sign on clerk report PGM2 M/S
5810
X
TL
5820
X
TL
5940
X
TL
5990
X
TL
5994
X
TL
NK
5996
X
TL
5997
X
TL
5700
X
TL
1 16
Page 20
CHAPTER 9. READING (X) AND
RESETTING (Z) REPORTS
(1) Job #Ynm: Y = 1 when the master is in the X1/Z1 mode.
Y = 2 when the master is in the X2/Z2 mode.
(2) Master consolidation report command entry sequence
(a) To specify a range
NK1 : Machine number
NK2 : START number
NK3 : END number
(b) To specify a department or group
NK1 : Machine number
NK2 : DEPT number
(c) To specify nothing
NK1 : Machine number
(3) Individual report command entry sequence
The same key operation as the standalone is required for entry
of an individual report JOB#.
(4) Syetem sales report for master/backup master
MODE ∗1
OP X/Z X1/Z1 X2/Z2 ∗3 DATA FOR
REPORT NAME X Z X1 Z1 X2 Z2 JOB# READING NOTE
GENERAL ΦΦΦΦ 1 x 00 —
DEPT/GROUP ΦΦ1 x 10 —
IND. GROUP ΦΦ 1 x 12 GROUP No
GROUP TOTAL ΦΦ 1 x 13 —
PLU BY RANGE ΦΦΦΦ1 x 20 PLU CODE ∗2
PLU BY DEPT ΦΦΦΦ1 x 21 DPT CODE
PLU IND. GR. ΦΦ 1 x 22 GROUP N o
PLU GR. TL ΦΦ1 x 23 —
PLU STOCK Φ 1 x 24 PLU CODE ∗2
PLU ZERO SALES ΦΦ1 x 27 ALL
PLU ZERO SALES
BY DEPT
ΦΦ1 x 27 DPT CODE
PLU MINIMUM
STOCK
Φ 1 x 28 ALL
TRANSACTION ΦΦ 1 x 30 —
TL-ID Φ 1 x 31 —
COMMISSION
SALES
ΦΦ1 x 32 —
TAX ΦΦ1 x 32 —
CHIFF Φ 1 x 34 —
ALL CLERK ΦΦΦΦ 1 x 40 —
IND. CLERK ΦΦΦΦΦΦ1 x 41 ∗4
HOURLY (ALL) ΦΦ 1 x 60
HOURLY (RANGE) Φ 1 x 60 ∗2
DAILY NET ΦΦ1 x 70
GLU ΦΦ 1 x 80 ∗2
GLU BY CLERK ΦΦ 1 x 81
BALANCE ΦΦ1 x 82
STACKED REP ΦΦΦΦ
1 x 90 –
1 x 91
Reset clear ΦΦ1 x 99
∗1 X1 : Daily X report Z1 : Daily Z report
X2 : Preriodic X report Z2 : Periodic Z report
∗2 The time interval range, or PLU code range can be specified by
entering the start and end numbers according to the following
procedure. When specifying a single time interval, PLU code,
the start number has only to be entered.
Stop of printing reports: These system reports do not execute this
specification.
∗3 When 1 is entered in the forth digit of a job code, Inline system
reports are printed.
Example: System daily general report; job code 1100
System periodic general report; job code 1200
∗4 In case of floating clerk system, this daily report can be printed
at any satellite.
(The periodic report can not be printed at any satellite.)
XXXX XXXX
Start No. End No.
X
Ynm
X
NK1
ST
NK2
NK3
TL
Enter system
Machine number
Only 1 item
X
X
Ynm
NK1
ST
NK2
TL
Entire system
Machine number
X
Z
X
Ynm
NK1
ST
TL
Entire system
Machine number
X
Z
X
1 17
Page 21
(5) Individual report jobs for the master/backup master/satellite
MODE ∗1
OP X/Z X1/Z1 X2/Z2 ∗3 DATA FOR
REPORT NAME X Z X1 Z1 X2 Z2 JOB# READING NOTE
GENERAL ΦΦΦΦ 00 —
DEPT/GROUP ΦΦ 10 —
IND. GROUP ΦΦ 12 GROUP No
GROUP TOTAL ΦΦ 13 —
PLU BY RANGE ΦΦΦΦ 20 PLU CODE ∗2
PLU BY DEPT ΦΦΦΦ 21 DPT CODE
PLU IND. GR. ΦΦ 22 GROUP No
PLU GR. TL ΦΦ 23 —
PLU STOCK Φ 24 PLU CODE ∗2
PLU ZERO SALES ΦΦ 27 ALL
PLU ZERO SALES
BY DEPT
ΦΦ 27 DPT CODE
PLU MINIMUM
STOCK
Φ 28 ALL
TRANSACTION ΦΦ 30 —
TL-ID Φ 31 —
COMMISSION
SALES
ΦΦ 32 —
TAX ΦΦ 33 —
CHIFF Φ 34 —
ALL CLERK ΦΦΦΦ 40 — ∗4
IND. CLERK ΦΦΦΦΦΦ 41 — ∗4
HOURLY (ALL) ΦΦ 60
HOURLY (RANGE) Φ 60 *2
DAILY NET ΦΦ 70
GLU ΦΦ 80 ∗2
GLU BY CLERK ΦΦ 81
BALANCE ΦΦ 82
STACKED REP ΦΦΦΦ90 – 91
∗1 X1 : Daily X report Z1 : Daily Z report
X2 : Preriodic X report Z2 : Periodic Z report
∗2 The time interval range, or PLU code range can be specified by
entering the start and end numbers according to the following
procedure. When specifying a single time interval, PLU code,
the start number has only to be entered.
∗3 When 2 is enterd in the third digit of a job code, periodic reports
are printed.
Example: Daily general report; job code 100
Periodic general report; job code 200
∗4 In case of clerk centrized, this report can not be printed at mas-
ter/backup master/satellites.
XXXX XXXX
Start No. End No.
X
1 18
Page 22
CHAPTER 10. SOFTWARE INST ALLATION PROCEDURE FOR IN-LINE SYSTEM
1. SATELLITE
SRV
1) 902 →
• → ⊗ → 1XXX → TL ; INLINE YES
2) 920 →
• → ⊗ → 1 → TL ; SATELLITE MACHINE.
3) 899 →
• → ⊗ → TL ; INLINE RAM CLEAR.
PGM2
4) 2612 →
• → ⊗ → M-No. → TL ; OWN MACHINE NO.
5) 3610 →
• → ⊗ → T-No. → TL ; OWN TERMINAL NO.
2. MASTER
SRV
6) 902 →
• → ⊗ → 1XXX → TL ; INLINE YES
7) 920 →
• → ⊗ → 2 → TL ; MASTER MACHINE.
8) Programs the other necessary SRV JOBs (#924,925)
9) 899 →
• → ⊗ → TL ; INLINE RAM CLEAR
PGM
10) 2612 →
• → ⊗ → M-No. → TL ; OWN MACHINE NO.
11) 3610 →
• → ⊗ → T-No. → TL ; OWN TERMINAL NO.
12) ; MACHINE MASTER LIST
13) Programs the other necessary PGM JOBs.
14) 4900 →
• → ⊗ → TL ; DOWN LOADING (IN-LINE PA RAMETER DATA)
(ALL PRESET DATA)
SRV
15) 800 →
• → ⊗ → TL ; DOWN LOADING (SRV PARAMETER)
16) 850 →
• → ⊗ → TL ; DOWN LOADING (KEYBOARD)
PGM
17) 4999 →
• → ⊗ → TL ; DOWN LOADING (ALL PGM PRESETS)
3. Set-up 1 job operation
1) Satellite (Jobs #902, #920, #899, and #3610 are auto-matically programmed.) mus t do PGM JOB #2612.
2)
Master (Jobs #902, #920, #899, #3610, #3611, and #4900 are automatically programmed.) must do PGM JOB#2612.
3)
Back-up master (Jobs #902, #920, #899 and #3610 are auto-matically programmed. ) ,mas t do PGM JOB #2612.
4)
Standalone (Jobs #902, #920 are automatically programmed.) must do PGM JOB#2612.
895 →
• → ⊗ → TL
3611
T-No. M-No.
TL
ST
X X
895
⊗ ⊗
1
Terminal No.
of the satellite
it self
TL
895
X
ST
2
X
Terminal No.
of the satellite
it self
TL
Terminal No.
X
Machine No. ST
895
⊗ ⊗
3
Terminal No.
of the satellite
it self
TL
1 19
Page 23
II. RS-232 SYSTEM FOR ER-A570
ER-A5RS
MODEL ER-A57R1 (For ER-A570)
(OPTION FOR ER-A570)
CHAPTER 1 . GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
CHAPTER 2 . COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
CHAPTER 3. SPECIFICATIONS OF RS-232 INTERFACE. . . . . . . . . . . . . . . . . . 2-2
CHAPTER 4. BLOCK DIAGRAM AND SYSTEM CONFIGURATION . . . . . . . . . . 2-3
CHAPTER 5. SIGNAL CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
CHAPTER 6. RS-232 PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
CHAPTER 7. CONTROL SIGNAL SEQUENCE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
CHAPTER 8. DATA BLOCK FORMAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
CHAPTER 9. RS-232 APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
.
CONTENTS
2 1
Page 24
■ WHAT IS AN RS-232 INTERFACE?
•
EIA (Electronics Industries Association) standard RS-232 is associated with the transfer of binary serial data, control signals and
timing signals between modems and data terminals.
• The RS-232 interface is one of the devices generally used for the
exchange of information between a computer and a peripheral
device.
• This interface (ER-A5RS) was designed to conform to the EIA
standard, but in particular it was designed for connection between
the ER-A570 and a data processing machine.
• It becomes necessary to set communication specifications of the
ER-A5RS (e.g. baud rate) matched to those of the data processing
machine, when the ER-A5RS is connected with a data processing
machine that is equipped with the RS-232 interface.
• The Dip switch on the ER-A5RS interface circuit board must be
used to choose the specifications .
• Refer to Section 3 "RS-232 Interface Specifications" for details of
communication specific at ions .
CHAPTER 1. GENERAL
This option (ER-A57R1 and ER-A5RS) is the RS-232 interface option
for the ER-A570 cash register. It enables the ER-A570 to perform
on-line data communications.
When this option is used for on-line data communications, the ERA570 can be connected to a host computer. Also, their connection
can be made via modems.
When this option is used together with a multiplexer (to be procured
in the market), it allows the host computer to be connected to more
than one ER-A570.
CHAPTER 2. COMPONENTS
ER-A5RS
NO NAME PARTS CODE Q’ty
1
PWB UNIT
CPWBS7292RC01
1
2
BRACKET
LANGT7466RCZZ
1
3
SCREW (FOR PWB AND
BRACKET)
LX–BZ6665RCZZ
2
4
SCREW (FOR HOLDING OF
THE PWB BRACKET, AND
BRACKET TO BRACKET)
LX–BZ6774RCZZ
3
5
SCREW (FOR HOLDING OF
THE RS-232 CABLE CORE)
XHBSD30P08000
2
6
WIRING TIE
LBNDJ2004SCZZ
1
7
CLAMP
(FOR RS-232 CABLE)
LHLDW6814R C ZZ
2
8
SPACER
PSPAN7039XCZZ
1
9
FERRITE CORE
(FOR EXTERNAL CABLE)
RCORF6658RCZZ
2
CHAPTER 3. SPECIFICATIONS OF
RS-232 INTERFACE
1. Online interface
a) Interface : RS-232
b) Duplex type : Half-duplex / Full-duplex
c) Line configuration : Direct connection/Modem connection
d) Data rate : 19200, 9600, 4800, 2400, 1200, 600 and
300 bps
(Programable)
e) Synchronizing mode : Asynchronous
f) Parity check : Vertical parity check (odd)
g) Code : ASCII
h) Bit sequence : LSB first
i) Data format : 1 start bit + 7 data bits + 1 parity +
1 stop bit
j) Protocol : Polling/selecting (Simple procedure)
k) Transmission line :
Cable : Shielded cable
Connector
(ECR side)
: D-sub 9 pin (female type) connector
Inch pitch (4-40 UNC) lock screw
Connector cover : Shielded cover
The table shows the relationship between the data rate and the recommended cable length.
Data rate Recommended cable length
19,200 bps 3.75 meters
9,600 bps 7.5 meters
4,800 bps 15 meters
2,400 bps 30 meters
1,200 bps 60 meters
Data-bit
Parity-bit Stop-bit
b1 b2 b3 b4 b5 b6 b7 P
Start-bit
2 2
Page 25
CHAPTER 4. BLOCK DIAGRAM
AND SYSTEM CONFIGURATION
1. System Configuration
1) On-line data communication
On-line data communication is allowed only when the ER-A570 is a
stand-alone machine or an in-line master. The protocol is the simple
procedure. (The on-line option is not usable if the ER-A570 is an
in-line satellite.)
1 Direct connectio n
a) One-to-one connection
2 Connection via modems
a) One-to-one connection
2) On-line data communication and in-line system
connection
∗ The ER-A6IN is required for the inline (SRN) system.
Satellite
Host computer
ER-A570
The ER-A57R1 and ER-A5RS are Installed in ER-A570.
(The same applies to the sample connections shown
below.)
MODEM NCU
Satellite
Host computer
NCU MODEM
To be procured in the market
ER-A570
MODEM NCU MODEMNCU
OR
in-line
system
In-line master
In-line master
In-line backup
master
In-line satellite
In-line satellite
ER-A570
ER-A570
ER-A570
ER-A570
2 3
Page 26
CHAPTER 5. SIGNAL CONNECTION
DIAGRAM
1. Connection between the master (Host)
and Satellite
SD : TRANSMITTED DATA
RD : RECEIVED DATA
DTR: DATA TERMINAL READY
DSR: DATA SET READY
RTS : REQUEST TO SEND
DCD: DATA CARRIER DETECTOR
CTS : CLEAR TO SEND
FG : FRAME GROUND
SD
2
SD
RD
CTS
RD
3
6
5
3
2
6
8
HOST
75
SG
RTS
4
DCD
8
DTR
20
DSR
7
1
4
SATELLITE
CTS
SG
RTS
DCD
DTR
DSR
1
FG
FRAME GROUND is connected
to the shield of the cable.
25PI N D- SU B 9PI N D- SUB
SD SD
RD
SG
RD
3
2
4
6
7
1
8
5
2
3
20
6
4
8
5
7
RTS
DCD
DTR
DSR
CTS
CI
22 9
SG
RTS
DCD
DTR
DSR
CTS
CI
FG
1
FRAME GROUND is connected
to the shield of the cable.
MODEM
TERMINAL
25PI N D- SU B 9PI N D- SUB
2 4
Page 27
2. Connection between the terminal and
MODEM
SD : TRANSMITTED DATA
RD : RECEIVED DATA
DTR: DATA TERMINAL READY
DSR: DATA SET READY
RTS : REQUEST TO SEND
DCD: DATA CARRIER DETECTOR
CTS : CLEAR TO SEND
CI : CALLING INDICATOR
FG : FRAME GROUND
ACK
EOT
( 1 ) Inquines of the satellite.
( 4 ) Receives ACK.
( 5 ) Sends the text.block.
( 7 ) Resends the text block if NAK is received.
Resends the text block up to two times.
Sends EOT and terminates the operation
with error if NAK is still received after t he
second resending of text block.
( 9 ) Sends the next text if ACK is received and
sends EOT and terminates the operation if
data transfer is finaiized.
( 2 ) Receives ENQ.
Check the terminal No.
to see if it is its own.
( 3 ) Sends ACK.
( 6 ) Receives text.
Checks the check sum,text
data,etc. And goes to (8)
if there is no error in them.
( 8 ) Sends ACK.
( 10 ) Terminates the operation if EOT
is received.
ENQ
Host Satellite
Dummy
(3bytes)
Terminal No.
(6bytes)
Start code Text (parameter) End code
Text (FDS)
Text (DATA)
Three types of
text block formats
are available
NCK
ACK
( 8 )' Sends NAK if any error
occurs.
2 5
Page 28
CHAPTER 6. RS-232 PROTOCOL
1. Basic protocol specification
1) Data transmission from the host to a satellite
ACK
EOT
( 1 ) Inquines of the satellite.
( 4 ) Receives ACK.
( 5 ) Sends the text.block.
( 7 ) Resends the text block if NAK is received.
Resends the text block up to two times.
Sends EOT and terminates the operation
with error if NAK is still received after the
second resending of text block.
( 9 ) Sends the next tex t if ACK is rece ive d and
sends EOT and waits fo r ENQ.
( 2 ) Receives ENQ.
Checks the terminal No.
to see if it is its own.
( 3 ) Sends ACK.
( 6 ) Receives text.
Checks the check sum,text
data,etc. And goes to (8)
if there is no error in them.
( 8 ) Sends ACK.
( 10 ) Terminates the operation if EOT
is received.
ENQ
Host Satellite
Dummy
(3bytes)
Terminal No.
(6bytes)
Start code Text (parameter) End code
Text (DATA)
NAK
ACK
( 8 )' Sends NAK if any error
occurs.
ENQ
ACK
Continued on the
next page
2 6
Page 29
2) Data transmission from satellite to the host
( 13 ) Receives text.
Checks the check sum, text lingth, text data, etc.
And goes to (15) if there is no error in them.
Sends NAK if any error occurs.
( 15 ) Sends ACK.
( 17 ) Terminates the operation if EOT is received.
( 12 ) Sends text corresponding
to the job code.
( 14 ) Resends text block if NAK is received.
Resends text up to two times,and
performs error handling if NAK is still
received after the second resending
of text block.
( 16 ) Sinds the next text if ACK is received,
and sends EOT and terminates the
operation if data transfer is finalized.
Host Satellite
EOT
Continued from the
preceding page.
Start code Text (parameter) End code
Text (DATA)
Two types of
text block
formats are
available.
NAK
(When an error
occurs)
ACK
Note : For the description of
each data block see section
4 (Text block formats)
2 7
Page 30
2. Transmission control procedure matrix
1) Down-loading matrix for the host
STATE Initial After sending ID ENQ After sending text
EVENT 0 1 2
ENQ — — —
ACK —
Sends text and goes to 2. Sends text and goes to 2.
Sends EOT and then goes to 0.
(Normal end)
NAK — —
Resends the text and then goes to 2.
If the host has resent the text two times, it sends EOT and
goes to 0.
(ERROR END)
EOT — —
The host goes to 0.
(ERROR END)
TEXT — — —
TIME-UP —
Resends ID ENQ and then goes to 1.
If the host has resent ID ENQ two times,it sends EOT and
goes to 0.
(ERROR END)
Resends the text and then goes to 2.
If the host has resent the text two times,it sends EOT and
goes to 0.
(ERROR END)
KEY ENTRY Sends ID ENQ and goes to 1. — —
Time-up: One second after sending of ID ENQ.
Four seconds after sending of text.
Page 31
2) Up-loading matrix for the host
STATE Initial After sending ID ENQ After sending text
EVENT 0 1 2
ENQ — — —
ACK — Sends text and goes to 2. Sends EOT and goes to 3.
NAK — —
Resends the text and then goes to 2.
If the host has resent the text two times, it goes to 0.
(ERROR END)
EOT — —
The host goes to 0.
(ERROR END)
TEXT — — —
TIME-UP —
Resends ID ENQ and then goes to 1.
If the host has resent ID ENQ two times, it goes to 0.
(ERROR END)
Resends the text and then goes to 2.
If the host has resent the text two times, it goes to 0.
(ERROR END)
KEY ENTRY Sends ID ENQ and goes to 1. — —
Time-up: One second after sending of ID ENQ.
Four seconds after sending of text.
STATE After sending EOT After sending ACK After sending NAK
EVENT 3 4 5
ENQ
Sends ACK and goes to 4. After the host has received ENQ, resends ACK and goes to
4.
After the host has received TEXT, ignores the ENQ.
—
ACK — — —
NAK — — —
EOT
The host goes to 0
(ERROR END)
After the host has received TEXT, goes to 0.
(Normal end)
After the host has received ENQ, goes to 0.(ERROR END)
The host goes to 0.
(ERROR END)
TEXT —
The host checks the text block, if the block is correct, the
host sends ACK and goes to 4.
If it is not correct, the host sends NAK and goes to 5.
If transmission cannot be continued, the host sends EOT
and goes to 0.
The host checks the checks the text block, if the block is
correct, the host sends ACK and goes to 4.
If it is not correct, the host sends NAK and goes to 5.
If transmission cannot be continued, the host sends EOT
and goes to 0.
(ERROR END)
TIME-UP
Resends EOT and goes to 3.
If the host has resent the EOT two times, it goes to 0.
(ERROR END)
The host goes to 0.
(ERROR END)
Time-up is 7 seconds
The host goes to 0.
(ERROR END)
Time-up is 7 seconds
KEY ENTRY — — —
Time-up: Two second after sending of EOT.
Page 32
3) Down-loading matrix for the sattelite
STATE Initial After sending ACK After sending NAK
EVENT 0 1 2
ID-ENQ
Satellite checks the terminal No.:If it is correct, satellite
sends ACK and goes to 1.
If it is not correct, Satellite ignores the ID-ENQ.
Satellite checks the terminal No.:If it is correct, satellite
sends ACK and goes to 1.
If it is not correct, Satellite ignores the ID-ENQ.
—
ACK — — —
NAK — — —
EOT —
After satellite has received TE XT , goes to 0.
(Normal end)
Before satellite has received TE X T, ignores the EO T
Satellite goes to 0.
(ERROR END)
TEXT —
Satellite checks the text block, if the block is correct,
Satellite sends ACK and goes to 1.
If it is not correct, satellite sends NAK and goes to 2.
If transmission cannot be continued, satellite sends EOT
and goes to 0.
(ERROR END)
Satellite checks the text block, if the block is correct,
Satellite sends ACK and goes to 1.
If it is not correct, satellite sends NAK and goes to 2.
If transmission cannot be continued, satellite sends EOT
and goes to 0.
(ERROR END)
TIME-UP —
Satellite sends EOT, and goes to 0.
(ERROR END)
Time-up is 7 secondsThe host goes to 0.
The host goes to 0.
(ERROR END)
Time-up is 7 seconds
Page 33
4) Up-loading matrix for the satellite
STATE Initial After receiving ID-ENQ and sending ACK. After sending NAK
EVENT 0 1 2
ID-ENQ
Satellite checks the terminal No.:If it is correct, satellite
sends ACK and goes to 1.
If it is not correct, satellite ignores the ID-ENQ.
Satellite checks the terminal No.:If it is correct, satellite
sends ACK and goes to 1.
If it is not correct, satellite ignores the ID-ENQ.
—
ACK — — —
NAK — — —
EOT — —
Satellite goes to 0.
(ERROR END)
TEXT —
Satellite checks the text block, if the block is correct,
satellite sends ACK and goes to 3.
If it is not correct, Satellite sends NAK and goes to 2.
If transmission cannot be continued, satellite sends EOT
and goes to 0.
(ERROR END)
Satellite checks the text block, if the block is correct,
Satellite sends ACK and goes to 3.
If it is not correct, Satellite sends NAK and goes to 2.
If transmission cannot be continued, satellite sends EOT
and goes to 0.
(ERROR END)
TIME-UP —
Satellite goes to 0.
(ERROR END)
Time-up is 7 seconds
Satellite goes to 0.
(ERROR END)
Time-up is 7 seconds
STATE After receiving text and sending ACK After sending ENQ After sending TEXT
EVENT 3 4 5
ID-ENQ — — —
ACK —
Satellite sends the text and goes to 5. Satellite sends the text and goes to 5, or sends the EOT
and goes to 0.
(Normal END)
NAK — —
Resends the text and then goes to 5.
If satellite has resent the text two times, sends EOT and
goes to 0.
(ERROR END)
EOT
Satellite sends ENQ and goes to 4. Resends the ENQ and then goes to 4.
If Satellite has resent the ENQ two times, sends EOT and
goes to 0.
(ERROR END)
Satellite goes to 0.
(ERROR END)
TEXT
Satellite checks the text block, if the block is correct,
satellite sends ACK and goes to 3.
If it is not correct, satellite sends NAK and goes to 2.
If transmission cannot be continued, satellite sends EOT
and goes to 0.
(ERROR END)
——
TIME-UP The host goes to 0.
(ERROR END)
Time-up is 7 seconds
Resends the ENQ and then goes to 4.
If satellite has resent the ENQ two times, sends EOT and
goes to 0.
(ERROR END)
Resends the text and then goes to 5.
If satellite has resent the text two times, sends EOT and
goes to 0.
(ERROR END)
Time-up: Four seconds after sending of text.
Two second after sending of ENQ.
Page 34
CHAPTER 7. CONTROL SIGNAL SEQUENCE
1. Online transmission
1) Half duplex transmission 2) Full duplex transmission
*Note: In the direct connect mode, same as full duplex control, but
the CI signal is not controlled.
3) Line connection sequence flow
DATASD
DTEDCE
DATARD
RTS
CTS
DSR
DCD
DTR
CI
< 100ms
< 500ms
DATASD
DTEDCE
DATARD
RTS
CTS
DSR
DCD
DTR
CI
< 100ms
< 500ms
*
*Note : In the direct connect mode, same as full duplex control, but the
CI signal is not controlled.
STARTED BY P.C
INITIAL
CI SENSE ?
CI ON ?
DTR ON
DSR ON ?
FULL DUPLEX ?
RTS ON
LINE ESTABLISHED
NO
NO
NO
NO
NO NO
YES YES
CI SENSE ? TIME OUT ?
YES
YES
YES
ERROR : NO LINE
DTR OFF
Note : The CI signal can be changed over when
so set in the PGM mode, and effective
at ECR side.
30sec
2 12
Page 35
4) Transmission sequence flow
LINE ESTABLISHED
FULL DUPLEX ?
DCD OFF ? TIME OUT ?
RTS ON
DSR ON ?
FULL DUPLEX ?
DCD ON ?
CTS ON ?
TIME OUT ?
TIME OUT ?
YES
YES
YES
NO NO
5 sec
YES
YES
YES
YES
YES
NO
30 sec
NO
YES 7 sec
TXRDY ?
SEND 1 CHARACTER
MORE TO
SEND ?
FULL DUPLEX ?
WAIT 100ms
FULL
DUPLEX ?
RTS OFF
LINE ESTABLISHED
DTR OFF
RTS OFF
TRANSMIT ERROR
NO
YES
YES
YES
YES
LINE ESTABLISHED
RTS OFF
2 13
Page 36
5) Receiving sequence flow
LINE ESTABLISHED
DSR ON ?
DCD ON ?
RXRDY ?
READ 1 CHARACTER
EOT ?
ENQ ?
ACK ?
HALF
DUPLEX ?
TIME OUT ?
TIME OUT ?
SEND TEXT
LINE ESTABLISHED
DTR OFF
RTS OFF
RECEIVE ERROR
AFTER
RECEIVE
ER-OFF
COMMAND
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
NO
YES
YES
YES
YES
ID. ENQ
∞
ACK or
NAK 4 sec
TEXT 7 sec
END CODE
NAK ?
BUFFER FULL ?
LINE ESTABL
DTR OFF
RTS OFF
DSR OFF
INITIAL
YES
YES
YES
YES
YES
NO
30sec
2 14
Page 37
CHAPTER 8. DATA BLOCK FORMAT
1. Basic format
Start code : This code may not be provided.
Null is impermissible.
End code : This code may not be provided.
Null or any same code as the start code is
not permissible.
When master reset is performed, the default is assumed:
Start code = 02h
End code = 0Dh
Block consecutive No. : This number starts with 30h and cycles
like this: 30h, 31h — 39h, 30h, 31h (Ring
counter system)
Check sum : 2 bytes hex number
Low-order 8-bit data of the complement of
2 for the sum of text data.
RAM data: : Even number of data that is obtained by
dividing one byte of RAM data into high-
order 4 bits and low-order 4 bits and con-
verting them to ASCII codes shown in the
code conversion table.
Code conversion table .
Print code (high-order or low-order 4 bits) Line image
Bit image Hexadecimal ASCII
0000 0 30h
0001 1 31h
0010 2 32h
0011 3 33h
0100 4 34h
0101 5 35h
0110 6 36h
0111 7 37h
1000 8 38h
1001 9 39h
1010 A 41h
1011 B 42h
1100 C 43h
1101 D 44h
1110 E 45h
1111 F 46h
CHAPTER 9. RS-232 applic ation
1. RS-232 preset
1) SRV programming
[JOB#945] MRS = 0000
The assignment of RS-232 channel by each devic es .
945-A: Channel No. for ONLINE = 0 to 7.
945-B: Not used. (Fixed at "0")
945-C: Not used. (Fixed at "0")
945-D: Not used. (Fixed at "0")
∗ When channel No. is zero, system is nothing.
∗ Do not select the same channel number with two or more devices.
∗ Use the switches on the I/F board to set the channel No. for the I/F
board connector. (Refer to the RS-232 channel setting in IV.
HARDWARE DESCRIPT IO N F OR ER-A5RS.)
2) PGM programming
Job# PGM-MODE programming for online operation
6110 Programming of the terminal number
6111 Programming of the modem control
6112 Programming of the transmission data rate (Bau
rate)
6113 Programming of the start and end code.
6110 Online Preset reading
[JOB#6110] MRS = 000001
Programming of the terminal number
NK: Terminal No. = 0 to 999999
TL
945
ABCD
0
X
TL6110
NK
0
X
1) ID-ENQ :
10bytes
ENQ code (05h)
Terminal No. 000001-999999 (6 bytes)
EOT is set as dummy cahracters. (3 bytes)
2) ACK :
1 byte 06h
3) NAK :
1 byte 15h
4) EOT :
1 byte 04h
5) ENQ :
1 byte 05h
6) TEXT :
Data ASCII (max. 250 bytes)
Block consecutive No.
Start code
End code
Check sum
Example
Memory image
Line image
02 5A F0
123
30h 32h 35h 41h 46h 30h
Transmission sequence
123
2 15
Page 38
[JOB#6111] MRS = 00
Porgramming of the modem control
6111-A: 1. Sensing of the CI signal Yes/No
1. Sensing of the CI signal 6111-A
No 0
Yes 1
6111-B: 1. Duplex type
1. Duplex type 6111-B
Full duplex system 0
Half duplex system 1
[JOB#6112] MRS = 5
Programming of the transmission bau rate
6112-A: Transmission bau rate
Transmission bau rate 6112-A
300 bps 0
600 bps 1
1200 bps 2
2400 bps 3
4800 bps 4
9600 bps 5
19200 bps 6
[JOB#6113] MRS = 002013
Programming of the start and end code
XXX: Start code = 02H (STX)
YYY: End code = 0DH (CR)
[JOB#6110]
Online preset reading
TL
6111 AB
0
X
TL
6112 A
0
X
TL
6113 XXXYYY
0
X
TL
6110
X
2 16
Page 39
III. TEST FUNCTION FOR ER-A6IN AND ER-A5RS
CHAPTER 1. General
This test program, is contained in the ER-A57R1 (option ROM), has
been developed for the purpose of confirming the operations of the
I/F board check conducted by the ER-A5RS and ER-A6IN mounted in
the ER-A570.
CHAPTER 2. Structure (RS-232 test
& inline test)
1 RS-232 test (RS-232 port test conducted by ER-A5RS
The following structure is required to execute RS-232 test program.
• ER-A570
• ER-A 5RS (I/F PWB Unit)
• Loopback connec tor for test ing (UK OG -6705 RCZZ)
• ER-A 57R1 (opti on cont rol ROM )
Diagram of the loopback connector
2 Inline test
The following structure is required to execute the inline test program.
• ER-A570
• ER-A6IN (inline I/F PWB unit)
• ER-A 57R1 (opti on cont rol ROM )
• Branc h li ne (main li ne) cabl e (for trans mi s sion test )
• Termi nator (50Ω)
CHAPTER 3. Activation
This test program can be activated by inputting 3-digit number → TL
with the mode switch in the "SRV" positi on.
CHAPTER 4. Test Job & Code
1 RS-232 I/F check
JOB & CODE Contents
500 Channel check
501 RS-232 channel 1 check
502 RS-232 channel 2 check
503 RS-232 channel 3 check
504 RS-232 channel 4 check
505 RS-232 channel 5 check
506 RS-232 channel 6 check
507 RS-232 channel 7 check
2 Inline I/F check
JOB & CODE Contents
600 IRC TEST 1
601 IRC TEST 2
602 IRC TEST 3
603
IRC TEST 4: DATA transmission test
(SATELLITE setting)
604
IRC TEST 5: DATA transmission test
(MASTER setting)
CHAPTER 5. Cautions
• Opti ons shoul d be install ed with the power s uppl y turned off.
• When setting the RS232C channels, avoid setting two or more
ports to the same channel. The ER-A570 allows installation of
max. two units of the ER-A5RS. In this case also, avoid setting two
ports of the ER-A5RS to the same channel. If not, the hardware
may be damaged.
• Concerning the inspection items whose display formats are not
presented in this test function, nothing appears on the display
screen. (blank display)
CHAPTER 6. RS-232 Test
1. Channel check
1 Activation
The program is activated by JOB#500
SRV mode: 500 →
TL
2 Contents to be tested
Information about connected RS-232 channel is printed.
Πριν τιν γ
διγιτ 21201918171615
321
ΧΗ7 ΧΗ6 ΧΗ5 ΧΗ4 ΧΗ3 ΧΗ2 ΧΗ1 500
CHn =0 : Presence of channel
1 : Ansence of channel
3 Confirmed content
Printed contents and the setting of channel changeover switch on
PWB are compared and confirmed.
ER-A5RS: 2PCS
UKOG-6705RCZZ:
ER-A570
+ ER-A57R1
1CD2RD3TD4ER5
GND6DR7RS8CS9CI
3 1
Page 40
4 Release
The program is terminated after the above contents are printed.
RS-232 channel setting (SW OFF: 1, SW ON: 0)
∗ Refer to the silk print on the I/F board.
ER-A5RS CN2 ER-A5RS CN1
SW1
Channel
SW1
Channel
654 321
0 0 0 Invalid 0 0 0 Invalid
0 0 1 Channel 1 0 0 1 Channel 1
0 1 0 Channel 2 0 1 0 Channel 2
0 1 1 Channel 3 0 1 1 Channel 3
1 0 0 Channel 4 1 0 0 Channel 4
1 0 1 Channel 5 1 0 1 Channel 5
1 1 0 Channel 6 1 1 0 Channel 6
1 1 1 Channel 7 1 1 1 Channel 7
2. RS-232 Channel 1 ~ 7 check
1 Activation
The program is activated by JOB#501~507.
SRV mode: 501 →
TL : Channel 1
502 →
TL : Channel 2
503 →
TL : Channel 3
504 →
TL : Channel 4
505 →
TL : Channel 5
506 →
TL : Channel 6
507 →
TL : Channel 7
2 Contents to be tested
If the channel specified by JOB#CODE is not set, the machine
performs the mis-operation processing. When the channel is set,
the machine conducts the loop check concerning the channel
specified by JOB#CODE by using the loopback connector.
The following three items are checked:
1 Control signal check
2 Data transfer check
3 Timer check (RS-232 onboard timer)
Check 1 Control signal check (
ERn-DRn•CIn, RSn-CDn•CSn loop
check)
OUTPUT INPUT
ERn RSn DRn CIn CDn CSn
OFF OFF OFF OFF OFF OFF
OFF ON OFF OFF ON ON
ON OFF ON ON OFF OFF
ON ON ON ON ON ON
The read check about the above INPUT items and interrupt check of
CS, CI and C D are perf ormed.
Read check:
ER and RS are switched over in the order as
shown in the above table to confirm the logic of
DR, CI, CD and CS.If the read logic is different
from the one in the table, error print-outs occur.
Interrupt check: Allows the interruption of either of
CS, CI and CD
one by one. (The mask is released.)
The interruption does not take place when each
signal is turned on. Or if the interruption occurs
when a signal is turned off, error print-outs occur.
Each of the above checks should be made in four cycles.
Note)
ERn control selector jumper switch on the I/F board must be
switched to the software control side.
Check 2 Data transfer check (SDn-RDn loop check)
In this check, transfer 256-byte loopback data of $00 ~
$FF.
Note) The above check should be made with the baud rate set at
9600BPS.
Check 3 Timer check
Before making check 2 , set the corresponding timer at
10ms for RCVDT activation, and check to see that:
1)
TRQ1 is not generated during the execution of check
2 .
2)
TRQ1 is generated in 10msec. after check 2 is fin-
ished.
3 Contents to be checked
If an error occurs during the above checks, following error printouts occur. Even if an error occurs during check 1 , the test is
continued after the corresponding error print-out has occurred, but
if an error occurs during the execution of check 2 or 3 , the test
is terminated after the corresponding error print-out has occurred.
Note that when check 1 , 2 or 3 terminates, the termination
print-out occurs irrespective of any errors that have occurred during the check. (The program terminates normally only when no
error print-out has occurred.)
ERROR ERROR PRINT Contents
1 E1-ER DR
ERn-DRn ERR
2 E2-ER CI
ERn-CIn ERR
3 E3-RS CD
RSn-CDn ERR
4 E4-RS CS
RSn-CSn ERR
5 E5-CI INT Interruption error of
CIn
6 E6-CD INT Interruption error of
CDn
7 E7-CS INT Interruption error of
CSn
8 E8-TXEMP TXEMPn error
9 E9-TXEMP I Interruption error of TXEMPn
10 E10-TXRDY TXRDYn error
11 E11-TXRDY I Interruption error of TXRDYn
12
E12-RCVRDY RCVRDYn error
(Reception is impossible. TRQ1 has
occurred during execution of check
2 .)
13 E13-RCVRDY I Interruption error of RCV RDY
14
E14-SD RD SDn-RDn ERR
(Data error)
15
E15-SD RD SDn-RDn ERR
(Data error, Flaming error)
16
E16-TIMER TIMERn error
(
TMRQn cannot be set after
termination of check 2 .)
17 E17-TIMER I Interruption error of TRQ1
Errors that may occur during check 1 (control signal check): E1 ~ E7
Errors that may occur during check 2 (data transfer check): E8 ~
E15
Errors that may occur during check 3 (timer check): E12, E16 and
E17
4 Cancellation
The program automatically terminates when a check is finis hed.
Termination print-out:
50n n : 1 ~ 7
3 2
Page 41
CHAPTER 7. INLINE CHECK
1. IRC TEST 1
1 Getting started
Get started with JOB #600.
2 Test content
The ROM and the RAM on the ER-A6IN are checked as well as
an interruption by CTC and carrier sense are checked. Also the
ADLC functions and send/receive DMA are checked by means of
the self loop function of ADLC (MC6854). In addition, the other
signals are checked.
3 Check content
The end print is checked.
First the status of the number of resending is printed by the SRN
handler command (Diag 2), then diag 0, 1, and 5 commands are
executed. If any error occurs, an error print is made to show the
error status.
α Print of the number of resending by diag 2 command
DATA RETRY CNT. = XXX
ACK RETRY CNT. = YYY
(Νοτε) ΞΞΞ ανδ ΨΨΨ αρε ιν
δεχιµ αλ νυµβερσ. (000∼255)
β Error print by diag 0 command
Error status (0: Normal or not checked yet, 1: Abnormal)
E0-XXXXXXXX
(b7b6b5b4b3b2b1b0)
b0: RAM check error
b1: ROM sum check error
b2: CTC, CH2, or CH3 interruption (Timer interruption) is not
effective.
b3: Interruption with the carrier OFF is not effective, or the
mirror image with the carrier OFF shows the carrier ON.
b4: Transmission complete interruption (DMAC TC UP inter-
ruption) is not effective.
b5: A corrosion is generated.
b6: An expected interruption is made.
b7: An error occurs. (Always 1 in when in error print)
(Note)
• When a RAM error occurs, the other checks are not per-
formed.
• When a ROM sum check error occurs, the other checks
except for the RAM error check are not performed.
χ Error print by diag 1 command
Error status (0: Normal, 1: Abnormal)
E0-XXXXXXXX
(b7b6b5b4b3b2b1b0)
b0: Transmission complete interruption (DMAC TC UP inter-
ruption) is not effective.
b1: An underrun error occurs.
b2: An overrun error occurs.
b3: Abnormal data number transmitted by DMA
b4: Abnormal data number received by DMA
b5: Data transmitted by DMA are difference from data re-
ceived by DMA.
b6: n unexpected interruption is made.
b7: An error occurs. (Always 1 when in error print)
δ Error print by diag 5 command
The table below shows the names of the signals to be checked
and their directions.
Signal name Direction
Power failure notice Host → Controller
Power ON initializing Host → Controller
Power ON continuation Host → Controller
Power failure process end Host ← Controller
CH1 received data present Host ← Controller
CH2 received data present Host ← Controller
E5-XXXXXXXX H>C
(b7b6b5b4b3b2b1b0)
Check that the target bits in two kinds of status (ST1 and ST2)
obtained by diag 5 command are "0" for ST1 and "1" for ST2.
(The other bits should be masked.) In the other cases, the
error occurring bit is shown as "1" and the error print is made
in the above format. If the target bit is "0," it is normal.
ST1: Sense in the controller in non-active state of a signal in
the direction of host → controller.
ST2: Sense in the controller in active state of a signal in the
direction of host → controller.
B7: 0 (Not used.)
B6: Power failure notice
B5: 0 (Not used.)
B4: 0 (Not used.)
B3: 0 (Not used.)
B2: 0 (Not used.)
B1: Power ON continuation
B0: Power ON initializing
Similarly to the above procedure, the signals in the direction
from the controller to the host obtained by diag 5 command
are checked. If the target bit is "1," it shows defective operation, If "0," it is normal.
The error print in that case is made as shown below:
E5-XXXXXXXX C>H
(b7b6b5b4b3b2b1b0)
B7: 0 (Not used.)
B6: 0 (N0t used.)
B5: 0 (Not used.)
B4: CH2 received data present
B3: CH1 received data present
B1: 0 (Not used.)
B0: 0 (Not used.)
4 End
The end print is made and the operation is terminated automatically.
600
SRV mode: 600 TL
3 3
Page 42
2. IRC test 2 (FLAG send)
1 Getting started
Get started with JOB #601.
2 Content
FLAG (7EH) is continuously transmitted. The following display is
given during the execution. (Exec uti on of diag com mand 3 )
∆ΟΤ−∆ΙΣΠΛΑΨ: IRC FLAG CK SRV.
3Test check content
The FLAG to be transmitted is checked by the hardware.
601
4 Cancellation
To cancel this test, perform the SRV reset .
3. IRC test 3 (DATA send)
1 Getting started
Get started with JOB #602.
2 Test content
Data of 256 byte in 00 - 0FFH are formed as one packet, and the
packets are continuously transmitted in the packet interval of 12.8
msec at 480 kbps. (Execution of diag command 4)
∆ΟΤ−∆ΙΣΠΛΑΨ: IRC DATA CK SRV.
3Check content
The data to be transmitted are checked by the hardware.
602
4 Cancellation
To cancel this test, perform the SRV reset .
4. IRC test 4, 5 (Data transmission test)
This test is intended to perform data transmission test in an actually
configured system. The system to be tested is composed of one set
of master machine (set by JOB #604) and max. 15 sets of slave
machines (set by JOB #603).
Note for starting the test:
• When testing a set in which the IRC setting has been already
made, be sure to cancel the inline setting in the following procedure before performing this test.
To cancel the inline setting:
XXX: Set as required.
• When testing an already configured system, cancel the inline set-
ting of the set which are not to be tested in the above procedure or
disconnect their signal lines. (Disconnect the inner cable and the
joint connector.) If the test is executed without cancelling the inline
setting of a set which is not to be tested, the data in the set may be
destroyed.
• Cancel the inline setting of all the sets in the system before per-
forming the transmission test (JOB #603, JOB #604) setting. Perform the satellite machine setting (JOB #603) before performing
the master machine setting (JOB #604).
Note for terminating the test:
• After terminating the test of all the sets used in the test (by the
program resetting), perform setting of each set .
• For the set whose inline setting was cancelled before the test
because its IRC setting had been made, perform the inline setting
in the following procedure. This test will not affect the other settings.
To set the inline setting YES:
1 Satellite machine set ting (J O B #603)
Starting
∆ΟΤ−∆ΙΣΠΛΑΨ: SL: 000 SRV.
Test terminal No. input and test start
(XXX: 000 - 254)
XXX: Test slave machine terminal No.
∆ΟΤ−∆ΙΣΠΛΑΨ: SL:XXX SRV.
SRV mode: 602
TL
SRV mode: 601
TL
SRV mode: 902
TL
X
0XXX
SRV mode: 902
TL
X
1XXX
SRV mode: 603
TL
XXX
TL
3 4
Page 43
With the above procedure, setting and starting of the satellite
machine to be tested are finished, and the master machine is
ready for starting.
Data transmission with the master is performed and the sequence
number of received data is displayed on the displ ay .
When using two or more satellite machines for testing, perform
the above procedure for every satellite machine to be tested. In
this case, avoid repetition of the terminal number.
2 Master machine setting (JOB #604)
The master machine setting should be performed after the completion of the satellite machine setting. If the master machine is
started before starting the satellite machine, an transmission error
may occur.
STARting
∆ΟΤ−∆ΙΣΠΛΑΨ: MA000:SL000 SRV.
Test terminal No. input and test start
If there are two or more satellite machines, repeat
the procedure.
(XXX, YYY: 000 ~ 254)
XXX : Terminal No. of the master machine to be
tested
YYY : Terminal No. of the satellite machine to be
tested
Note: Do not use the same terminal No. to any of
the master and the satellite machines .
∆ΟΤ−∆ΙΣΠΛΑΨ: MAXXX:SLYYY SRV.
With the above procedure, data transmission is started with the
satellite machine in standby state.
When data transmission is started, the sequence No, of transmitted data is displayed on the 7SEG DISPLAY of the master and the
satellite machines.
∆ΟΤ−∆ΙΣΠΛΑΨ: ZZZZ
3Test content
a. A sequence No. of 2 byte and the format below composed of
0AAH data of 254 byte are transmitted from the master to the
satellite.
The sequence No. is displayed on the 7SEG DISPLAY of the
master.
b. The satellite returns the received data back to the master.
The sequence No. of the received data is displayed on the
7SEG DISPLAY of the satel lite.
c. The master receives the data and then checks the sequence
No. and 0AAH data.
If there are two or more satellite machines, steps a and b are
repeated. If all data sent from the satellite are normal, the
master increments the sequence No.
The above steps a through c are repeated.
Test data format (1 packet: 256 byte)
ZZZZ : Sequence No. 2 byte (Integral number 4 digits)
AA : Transmitted data (0AAH) x 254 byte
4 Error display
When an error occurs during the data transmission test, the following display is given and the error print is made.
To cancel the error, perform the program resetting (power
OFF/ON in the SRV mode).
Error display:
∆ΟΤ−∆ΙΣΠΛΑΨ: IRC ERR=XX SRV.
XX: Error code
Error print
(Satellite side)
E-XX 603
(Master side)
E-XX YYY 604
ΨΨΨ: ΣΑτε λλιτε τερµ ιναλ Νο.
ωηε ν αν ερρο ρ οχχυρσ.
XX= 01: Abnormal command (except during transmitting)
02: No received data
03: Reception size YES
Received data remained
04: The remote station not ready (in transmitting)
The remote station is not ready for reception and returns back "NRDY."
05: Receiving side buffer full
The controller receiving buffer in the remote station is
full.
06: Resend error (in transmitting)
Retry over (5 times) without reply
07: Collision error (in transmitti ng)
When data transmitting collision occurs, retry over (16
times) after random time (0 - 255 ms).
08: Line busy time out
Transmission is not made because of transmission
between the other remote stations, and data transmitting wait time is out.
09: Reception size over (in receiving)
The reception buffer size is insuffic ient .
0A: Hhard error
Abnormal interface (no SRN interface or abnormal
SRN controller)
SRV mode: 604
TL
XXXSTYYY
TL
ZZZZ: Sequence No. 0000 9999
ZZ1ZZ2AA3AA4AA
5
AA
254AA255AA256
(BYTE)
3 5
Page 44
IV. HARDWARE DESCRIPTION FOR ER-A6IN
AND ER-A5RS
CHAPTER1. ER-A6IN
1. Block Diagram
Fig. 1 SRN controller board block diagram
Fig. 1 shows the block diagram of the controller board of the SHARP
RETAIL NETWORK. The Controller is connected to the system bus of
the host system as one of I/O. Inside of the controller consists of Z-80
CPU, transmission link controller, DMA control circuit, ROM, RAM,
modulator, demodulator, carrier detection circuit, collision detect
circuit and so on.
Data communications with the host system is performed by the
handshaking by byte. The controller side functions with DMA (Direct
Memory Access) and is capable of data transmission without waiting
for the host system side.
∗ OPC1 is used only as a bus buffer. (In order to provide compatibil-
ity between the host CPU in the ECR side and H8/510.)
2. CPU Description (Z-80)
For details on the CPU, see the Cash Register Basic Manual.
Pin Connections (C-MOS Version used)
Pin Signal name
Input/
Output
Description
1 A11 Out Address Bus A11
2 A12 Out Address Bus A12
3 A13 Out Address Bus A13
4 A14 Out Address Bus A14
5 A15 Out Address Bus A15
6 φ In CLK4 (MHz)
7 D4 I/O Data Bus D4
8 D3 I/O Data Bus D3
9 D5 I/O Data Bus D5
10 D6 I/O Data Bus D6
Pin Signal name
Input/
Output
Description
11 VCC — +5V
12 D2 I/O Data Bus D2
13 D7 I/O Data Bus D7
14 D0 I/O Data Bus D0
15 D1 I/O Data Bus D1
16
INT In Interrupt
17
NMI In Non Maskable Interrupt
18
HAL T Out HALT
19
MREQ Out Memory Request
20
IOREQ Out I/O Request
21
RD Out Read
22
WR Out Write
23
BUSAK Out Bus acknowledge
24
WAIT In WAIT
25
BUSRQ In Bus Request
26
RES In Reset
27
M1 Out M1 cycle
28
RFSH Out Refresh
29 GND — GND
30 A0 Out Address Bus A0
31 A1 Out Address Bus A1
32 A2 Out Address Bus A2
33 A3 Out Address Bus A3
34 A4 Out Address Bus A4
35 A5 Out Address Bus A5
36 A6 Out Address Bus A6
37 A7 Out Address Bus A7
38 A8 Out Address Bus A8
39 A9 Out Address Bus A9
40 A10 Out Address Bus A10
3. Description of MB62H149
1) Outline
The MB62H149 is a semi-custom LSI chip for the peripheral circuits
in the SRN (SHARP Retail Network), its main function is to
communicate data with the host CPU and control the peripheral
circuits and transmission control circuits of the Sub CPU (Z-80). Fig.
2. shows the general configuration of the functions:
Fig. 2
DATA BUS
CONTROL BUS
BUS BUFFER
DB
CONT
EXTERNAL
CABLE
HOST SYSTEM
BUS
RAM
DMA
CONTROLLER
CARRIER
DETECTION
COLLISION
DETECTION
CPU: Z80
ROM
CLOCK
CIRCUIT
MODULATOR
TRANSMISSION
LINK
CONTROLLER
DEMODULATOR
OPC1
MB62H149
Line
TRANSMISSION
CONTROL
CIRCUIT
PERIPHERAL
CIRCUIT
DATA HAND
SHAKING
CIRCUIT
TIMER
COUNTER
SUB-CPU
(Z-80)
DMAC
ADLC
HOST CPU
4 1
Page 45
2) Internal functions
(1) Data handsh ak ing circuit
Is used because data processing speeds vary and the timing of the
HOST CPU and SUB CPU do not synchronize, the MB62H149 is
used for data handshaking. When the data handshaking portion is
broken down, the system consists of a Write Signal from the HOST
CPU to the MB62H149, Read Signal from the MB62H149 of the SUB
CPU, Write Signal from the SUB CPU to the MB62H149 and Read
Signal from the MB62H149 of the HOST CPU, all of which from two
blocks as shown.
Fig. 3
Fig. 4
(2) Peripheral circuit
The peripheral circuit consists of an I/O address generation unit on
the SUB CPU, block dividing circuit, and the wait signal control unit.
Fig. 5
(a) I/O address generation circuit
A total of 11 I/O addresses are generated by A0, A1, A4, A5 and
RD and WR signals.
(b) CPU and DMAC wait signal control unit
Clocks into the CPU (Z-80), SUB CPU and its peripheral LSI,
DMAC and CTC are operated respectively on 4 MHz.
While, the ADLC (MC68B54) (Advanced Data Link Control) is
operated by the E (Enable clock) of 2 MHz according to restrictions in terms of the hardware of the LSI.
It is necessary to synchronize the timing of the write and read in
the ADLC.
To control synchronization, timing, and input, the wait signal
goes into the CPU for CPU access and into the DMAC for DMA
access. This block is a circui t to generate suc h wait signal .
(c) Clock dividing circuit
This block divides the blocks according to the CLK supplied from
outside to generate the clock for CPU, DMAC and CTC and the
E and transmission clock rate (480 KBPS or 1 MBPS selectable)
for the ADLC.
(3) Transmission control circuit
The transmission control circuit is divided into the modem unit, carrier
detect unit, collision detect unit.
Fig. 6
(a) Modem circuit
The transmission data input from the ADLC are PE modulated
(phase encoding modulation), the circuit to be output to the
transmission driver and the reception data input from the transmission receiver are demodulated and produced at the A DLC.
(b) Collision detect circuit
The data transmitted from the home station is received and
detects a collision on the transmission line by means of an exclusive OR gate.
(c) Carrier detect circuit
This circuit detects whether data is flowing on the transmission
line. It consists of a circuit which immediately senses a no data
status on the line. When data is not on the line the circuit
functions to sense an elapse of the fixed time rate. The
immediate sensing circuit is used for response testing and the
delayed sensing circuit is used for data tes ti ng.
The fixed time rate is selectable according to the transmission
speed as shown below via SRV -mode programm ing. Job #922.
Transmission speed Delay time
1 MBPS 1.6m sec, 3.2m sec, 4.8m sec, 6.4m sec.
480 KBPS 3.2m sec, 6.4m sec, 9.6m sec, 12.8m sec.
HOST CPU
DATA BUS
(8bit)
HOST CPU address
and RD, WR
SUB CPU
DATA BUS
(8bit)
HOST CPU · SUB CPU
& DMAC control
HOST CPU
address
decode
SUB CPU
write register
(HOST CPU
read register)
HOST CPU
write register
(SUB CPU
read register)
SUB CPU
write & HOST
CPU read control
unit (DMA &
CPU access)
HOST CPU
write & SUB
CPU read
control unit
(DMA & CPU
access)
CLK (16 MHz)
I/O address
Wait signal
SUB CPU address
& RD, WR
SUB CPU address
decoding unit
CPU & DMAC wait
signal control unit
Clock dividing
circuit
System clock
(4 MHz)
HOST CPU
MB62H149
SUB CPU
Write Read
(HOST CPU TO SUB CPU)
(FROM SUB CPU TO HOST CPU)HOST CPU MB62H149 SUB CPU
WriteRead
ADLC TDY
ADLC RDX
Collision detect
To transmission driver
From transmission receiver
Carrier detect 1
(for data)
Carrier detect 2
(for resronse)
MODEM un it
Collision
detect unit
Carrier
detect unit
4 2
Page 46
3) Terminal Name and Description (MB62H149)
Fig. 7
Pin
No.
Terminal
name
Host/
Sub
In/
Out
Description
1 CLK Sub In Clock in (16 MHz)
2 — — — N.U.
3
IORQ Sub In I/O request
4
MREQ Sub In Memory request
5
RDS Sub In Read from sub
6
WRS Sub In Write from sub
7
INTS Sub Out Interrupt to sub
8 φ Sub Out Clock out
9 TM0 Sub In Timer 0
10 TM1 Sub Out Timer 1
11
MRD Sub Out Memory read
12 VSS — — GND
13
WAIT Sub Out Wait signal
14 A15 Sub Out Address bus for DMA
16 A9 Sub Out
17 A8 Sub Out
18 A5 Sub In
19 A4 Sub In
20 A1 Sub In
21 A0 Sub In
22 DAK01 Sub In DMA acknowledge 0+1
23 — — — N.U.
24
MWR0 Sub Out Memory write
25 D7 Sub I/O Data bus
26 D6 Sub I/O
27 D5 Sub I/O
28 D4 Sub I/O
29 D3 Sub I/O
30 D2 Sub I/O
31 D1 Sub I/O
32 D0 Sub I/O
33 VDD — — +5V
34 — — — N.U.
35
RES Host In Reset
Pin
No.
Terminal
name
Host/
Sub
In/
Out
Description
36
IO/WR Sub I/O I/O write
37
IO/RD Sub I/O I/O read
38 AEN Sub In Address enable from DMAC
39 AST Sub In Address strobe from DMAC
40 TCS Sub In Terminal c ount
41 DAK23 Sub In DMA acknowledge 2+3
42
DRQRS Sub Out DMA request read to sub
43
DRQWS Sub Out DMA request write to sub
44
RDH Host In Read from Host
45
WRH Host In write from Host
46
INTH Host Out Interrupt to host
47
DAK Host In DMA acknowledge from host
48 TCH Host In Terminal count from host
49
DRQWH Host Out DMA request read to host
50
DRQWH Host Out DMA request write to host
51
CS Host In Chip select from host
52 VSS — — GND
53 — — — N.U.
54 DB0 Host I/O Data bus
55 DB1 Host I/O Data bus
56 DB2 Host I/O Data bus
57 DB3 Host I/O Data bus
58 DB4 Host I/O Data bus
59 DB5 Host I/O Data bus
60 DB6 Host I/O Data bus
61 DB7 Host I/O Data bus
62 AB0 Host In Address bus from host
63 — — — N.U.
64 AB1 Host In Address bus from host
65 COL Sub In Collision detect signal
66 RDI Sub I n Receive data from receiver
67 TDI Sub Out Transmmit data to driver
68
RTS Sub In Request to send
69 RXC Sub Out Receive clock to ADLC
70 RXD Sub Out Receive data to ADLC
71 TXC Sub Out Transmmit clock
72 TXD Sub In Transmmit data
73 VDD — — +5V
74 E Sub In Enable clock to ADLC
75
IRQ Sub In Interrupt request from ADLC
76
LCS Sub Out Link controller chip select
77 — — — N.U.
78 RS1 Sub Out Register select 1
79 RS0 Sub Out Register select 0
80 MSK Sub Out Mask signal
14
17.9 ±
0.4
20
23.9 ±
0.6
0.8 ±
0.15
0.35 ±
0.1
INDEX
LEAD
NO
1
24
25
40
41
64
65
80
4 3
Page 47
4) Pin Assingment and timing Charts
Pin function will be described for the host and sub system.
(1) Host pin description
1 DB0—DB7 (data bus) Input/Output, 3-state
Pins 54—61
These lines (data bus) are use for hardware flag assignments :
8-bit data write, hardware flag recognition, and 8-bit data read
from the host.
2
RDH (Read from host), Input
Pin 44
An active low signal which is used when the host reads the
hardware flag and 8-bit data through the data bus.
3
WRH (Write from sub), Input
Pin 45
An active low signal which is used when the host writes the
hardware flag and 8-bit data through the data bus.
4
CS (Chip select from host), Input
Pin 51
An active low signal which is used when the host reads or writes
the hardware flag and 8-bit data through the data bus.
5 AB0, AB1(Address bus from host), Input
Pin 62, 64
An input signal used to select the register when the host reads
or writes the hardware flag and 8-bit data through the data bus.
6
DAK (DMA Acknowledge from host), Input
Pin 47
Not used (+5v)
7
DRQRH (DMA Request read to haos), Output
Pin 49
Not used
8
DRQWH (DMA request write to host), Output
Pin 50
Not used
9 TCH (Terminal count from hos t), Input
Pin 48
Not used
Φ
INTH (Interrupt to host), Output
Pin 46
An active low signal which is used to inform the interrupt signal
that the controller has the information to read or write.
Γ
RES (Reset), Input
Pin 35
Asynchronous reset signal from the host which is used to reset
registers within the controller.
• HO S T read timing.
Fig. 8
• HOST write timing.
Fig. 9
(2) Sub system pin description
1 D0 – D7 (Data bus) Input Output (3-state)
Pin 32 – 25
These lines (data bus) are used for hardware flag assignments :
8 bit data write, hardware flag recognition, and 8-bit data read
from the subsystem.
2
IORQ (I/O request), Input
Pin 3
An active low memory request input from the subsystem (Z-80A)
which is used to create I/O control signals in conjunciton with
RDS, WRS, A0, A1, A4 and A5.
3
MREQ (Memory request), Input
Pin 4
An active low memory request input from the subsystem (Z-80A)
which is used to create I/O control signals in conjunction with
RDS and WRS.
4
RDS (Read from sub), Input
Pin 5
Data read signal received from the subsystem (Z-80A) wihch is
used to create I/O and memory data read control signal.
CS
AB0, AB1
RDH
DB0-DB7
TAR
TRWS
TRA
TRDE TRDF
CS
AB0, AB1
WRH
DB0-DB7
TAW
TWWS
TWA
TDW TWD
4 4
Page 48
5 WRS (Write from sub), Input
Pin 6
Data write signal received from the subsystem (Z-80A) which is
used to create I/O and memory data write control signal.
6
MRD (Memory read), Output
Pin 11
Memory data read control signal sent to the subsystem
(memory) which is created with MREQ and RDS.
7
MWRO (Memory write), Output
Pin 24
Memory data write control signal sent to the subsystem
(memory) which is created with MREQ and RDS.
8
IO/WR (I/O write), Input/Output (3-state)
Pin 36
I/O data write control signal sent to the subsystem (peripheral
I/O) which is created with IORQ And WRS .
During the DMA mode, it is received from the DMAC to create
the memory to I/O data transfer control signal.
9
IO/RD (I/O read), Input/Output (3-state)
Pin 37
I/O data read control signal sent to the subsysystem (peripheral
I/O) which is created with IORQ and WRS. During the DMA
mode, it is received from the DMAC to create the I/O to memory
data transfer control signal.
Φ AO, A1, A4, A5 (Address bus from sub CPU), In
Pin 21, 20, 19, 18
An input signal used to create the selection signal which the sub
reads the hardware flag and subsystem (peripheral I/O) 8-bit
data through the data bus.
Γ A8, A9, A10, A15 (Address bus for DMA), Output (3-state)
Pin 17, 16, 15, 14
Used to create the memory address information on the basis of
the information from the DMAC during the DMA cycle. The
output has 3-stats and retains a high impedance except during
the DMA cycl e.
Η AEN (Address enable from DMAC), In
Pin 38
An input from the DMAC which is used to enable the DMAC to
control by isolating the system address bus from the CPU
(Z-80A) during the DMA cycl e.
That is, A8, A9, A10, and A15 are set to output condition from
their high impedance state.
Ι AST (Address strobe from DMAC), In
Pin 39
An input from the DMAC which is used to latch the information
from the DMAC Sent on the data bus with AST In the DMAC
cycle to create A8, A9, A10, and A15 addres s inform ation.
ϑ DAK01 (DMA acknowledge 0+1), Input
Pin 22
The subsystem uses four DMA channels; one each for
transmitting and receiving of data (DAK0, DAK1), and for read
and write of received data (DAK2, DAK3), DAK01 is a logical OR
of DAK0 with DAK1 which is used for DMA control of
transmission data.
Κ DAK23 (DMA acknowledge 2+3), Input
Pin 41
This signal is a logical OR of DAK2 and DAK3 and is used for
DMA control of trans m iss i on data.
Λ
DRQRS (DMA request read to sub CPU), Output
Pin 42
An active low DMA request to the sub CPU to read data which is
normally connected to the DMA controller of the sub.
Μ
DRQWS A request to write to sub CPU), Outut
Pin 43
An active low DMA request to the sub CPU to write data which is
normally connected to the DMA controller of the sub CPU.
Ν TCS (T erm inal count from sub), Input
Pin 40
An active high signal which the subsystem uses to inform that
the current DMA cycl e is the final cycl e.
Ο
INTS (Interrupt to sub), Input
Pin 17
An interrupt which the controller uses to inform the sub that it
has data to be read or written. This output is a half duty
oscillation signal when activ e.
Π
WAIT (Wai t signal), Out put
Pin 13
This signal is used to provide synchronization for the DMAC and
the sub CPU with the link controller (ADLC) when transferring
data with the link controller (ADLC), that is, to wrtie a command
to the ADLC, to read status, and to write or read transmit or
receive data. This line is normally an input to the DMAC and sub
CPU WAIT (ready) line.
Θ CLK (Clock input), Input
Pin 1
Basic frequency input which is used to derive system clock,
transmit/receive clock, and internal sync clock, [16MHz]
Ρφ (clock out), Output
Pin 8
A system clock output which the basic oscillation is divided by
four, Since the basic frequency is normally at 16MHz, the
system clock output is a 4MHz.
Σ TXC (Transmit clock), Output (for SRN)
Pin 71
As the basic frequency is divided 1/16 or 1/32, it is supplied as
the transmit clock for the SRN system.
Choice of 1/16 and 1/32 is dependent on the sub CPU.
Τ TXD (Transmit data from ADLC), Input (for S RN )
Pin 72
Transmit data from the link controll er (A DLC).
Υ TDI (Transmit data to driver), Output (for SRN)
Pin 67
Transmit data which TXD is phase encoded with the transmit
clock which is an input to the line driver of the SRN.
ς RDI (Receiver data from receiver), Input (for SRN)
Pin 66
Phase encoded data from the other end via the line receiver of
the SRN.
Ω RXD (Receive data to ADLC), Input (for SRN)
Pin 70
Receive data (RXD) output as the phase encoded data from the
other end received via the receiver are demodulated within the
controller to separate it into the receive data (RXD) and receive
clock, which is normally an input to the link controller (ADLC).
Ξ RXC (Receive clock to A DLC), Out put (f or S RN )
Pin 69
An output of the receive clock (RXC) which is normally supplied
to the link controller (ADLC).
4 5
Page 49
Ψ RTS (Request to send), Input (for SRN)
Pin 68
An input from the link controller (ADLC) which becomes active
low during transmission. The controller uses it for controlling the
collision detect circuit and modem circ uit.
Ζ
LCS (Link controller chip select), Output
Pin 76
A chip select signal for the link controller (ADLC) in which the
sub CPU synchronizes with the DMCA.
[
IRQ (Interrupt request from ADLC), I nput
Pin 75
An Interrupt request from the link controller (ADLC).
∴ E (Enable clock to ADLC), Input
Pin 74
Link controller (ADLC) enable clock which the sub CPU
synchronizes with the DMAC for data read to write.
] RS0 (Register select 0), Outpt
Pin 79
Command and status register select signal for the link controller
(ADLC).
⊥ RS1 (Register select 1), Output
Pin 78
Command and status register select for the link controller
(ADLC) which is used in conjunction with RS0 above.
_ MSK (Mask signal), Output
Pin 80
Used to mask the signal to avoid DMA looping, except for other
than the data transmit/receive DMA request signal (input from
the link controller (ADLC), normally).
COL (Collision detect signal), Input
Pin 65
To avoid collision on the line, the data sent, from this side are
compared with the data on the line. In other words, when the
data sent are equal to the on line, no collision is assumed
existing. If not equal, an occurrence of data collision is assumed.
This line is, therefore, the input of the data sent from this side.
α TM0 (Timer 0), Input
Pin 9
A clock of a given interval (100 msec) sent from the subsystem’s
timer and counter. It is used to create the carrier off wait signal
and back-off timer within the controller.
β TM1 (Timer 1), Output
Pin 10
Back-off timer output is a clock pulse ten times the TM0
frequency (T1=10xT0), where T1 is TM 1 clock and T0 is a TM0
clock.
• Sub CP U read timi ng chart
Fig. 10
• Sub CPU write timing
Fig. 11
• Sub DMA memory write timing
Fig. 12
• MRD timing
Fig. 13
• MWR ti min g
Fig. 14
TAI TIA
TRWK
TRDG TRDH
A0, A1, A4, A5
IORQ
RDS
D0-D7
TAI
TIA
TWWK
TDWK TWDK
A0, A1, A4, A5
IORQ
WRS
D0-D7
TAEL
TSTL TST T
TAK TAK
TDQ
TDCL TDCT
TWAG
TWAH
TLCG TLCH
TMWG
TMWH
TEOG
TEOH
AEN
AST
IO/RD
WAIT
LCS
MWR
E
DAK01
DAK23
* LC S O r e m a i n h i gh l ev e l
for DK2, 3
Φ
TMRG TMRH
MREQ
RDS
MRD
TMWG TMWH
MREQ
WRS
MWR
4 6
Page 50
• CLK
Fig. 15
• A8, A9, A10, A15 t imings
Fig. 16
• MS K , RS O timings
Fig. 17
• TX C, T DI t im ings
Fig. 18
• RXC, RXD timings
Fig. 19
• Colli s ion generati on tim e
Fig. 20
4.Description of the DMA controller
(DMAC; µPD8257-2)
The µPD8257 DMAC is a signal-chip, programmable DMA controller
designed to control DMA transfers between the I/O devices and
memory. The foll owing outl ines the DM AC operati ons :
1) DMA Opretion
Data transfer between I/O devices and memory is normally done via
the CPU (see Fig. 21).
Fig. 21
The memory contents are temporarily stored in the CPU’s
internal register before being written into an I/O device at the next
step.
In contrast, the DMA controller allows data to be directly transferred
between memory and I/O devices without the CPU (See Fi g. 22).
Fig. 22
The DMAC (8257) permits data transfers only between memory and
I/O devices. (Some type of DMACs allow data transfer between
memories).
CLK
TC
TWH TWL
Φ
AEN
AST
D0-D7
A8, A9, A10, A15
TSDG TSDH
TADG
Φ
TTCG
TDMG
TTCH
TDMH
TTRG
TTRH
DAK01
TCH
MSK
LCS
RS0
RS1
: Duringtransfer
: Transf er and
Φ
TCTG
TCTH
TTDG
TCIG TCIH
TTDG
TXC
TXD
TDI
TCOL TCOL
RDI
COL
CPU
Memory
I/O device
DMAC
Memory
I/O device
Data
Control signalControl signal
RXWS RXWL
TRXY
TRXL TRXH
TRDSU TRDH
RDI
RXC
RXD
4 7
Page 51
2) Actual DMAC Operations
Fig. 23
Transfer from memory to I/O device
1 When the CPU wants to start a DMA cycle, it sets the number of
bytes to be transferred and the first address of the tansfer memory
area into the registers within the DMAC. The applicable I/O device
issues a DMA Request (DRQ) to the DMAC.
2 Receving the DRQ signal, the DMAC issues a
BUSRQ (Bus Re-
quest) to the CPU to request for bus access control.
3 Upon receipt of the
BUSRQ, the CPU floats both data and ad-
dress buses and returns a
BUSAK to the DMA as soon as it
completes the current instruction execut ion cycle.
Bus access control is now passed to the DMAC.
4 The DMAC creates as memory Chip Select signal from the ad-
dress bus, and outputs the transfer data address and RD signal to
place the transfer data onto the data bus. At this point the DMAC
issues a DAK (DMA Acknowledge) to the I/O device to let to the
I/O device read the memory data on the data bus. The above
sequence is repeated until a single DMA cycle is completed.
* On this board, DMA transfer is performed between the ADLC and
memory, and between memory and MB62H149.
The DAK01 (pin 37) and DAK23 (pin 41) of the MB62H149 are the
results of the logical OR of DAK0 with DAK1 and DAK2 with DAK3
of the DMAC, respectively. The DMAC’s DAK is controlled by the
MB62H149.
Fig. 24
DAK01 is used for the DMA cycle for data transfer, while DAK23 is
used for data transfer with the host processor.
CPU
(Z-80)
Memory
I/O device
DMAC
(8257)
Address bus
Data bus
BUSAK
BUSRQ
DAK
DRQ
External
device
3
2
4
1
4
DAK0
DAK1
DAK2
DAK3
DAK01
DAK23
8257
DMAC
25
24
14
15
22
41
MB62H149
4 8
Page 52
3) DMAC (8257-2) Pin Functions
Pin No. Signal name/in-out/Des c ript ion
1
I/OR (I/O Read) – Active Low Input/output (3 state )
This pin functions as an input when is Slave mode. Application of a Low level to this pin reads the 8-bit status register
value or the upper/lower byte of the 16-bit DMA address register or 16-bit TC regsiter. When in the Master mode this pin
serves as a control output, which allows the device to recei ve data from an I/O devi ce during the DMA write cycle.
2
I/OW (I/O Write) – Act ive Low i nput/ output (3 state)
This pin function as an input when in Slave mode. Application of a Low level to this pin enables the data to be loaded
into the 8-bit mode set register or the upper/lower byte of the 16-bit DMA address register or TC register. When in the
Master mode this pin serves as a control output , which all ows the device to write data into an I/O device.
3
MEMR (Memory Read) – Active Low output (3 state)
This pin is used to enable to be read from the addressed memory location during DMA read cycle. It is set to a high
impedance when in the Slave mode.
4
MEMW (Memory Write) – Act ive Low out put (3 s tate)
This pin is used to enable data to be writen in to the addressed memory location during DMA write cycle. It is set to high
impedance when in the Slave mode.
5 MARK (Mark) – Output
This pin is used to indicate to the selected I/O device that the current DMA cycle is the 128th cycle as counted from the
preceding MARK.
A MARK always occurs at every 128 cycles as counted from the end of a data block. It occurs at every 128 cycle as
counted from the beginning of a data block only if the total number (n) of DMA cycles is an integral multiple of 128 (and
the value (n-1) is loaded in the TC register).
6 READY (Ready) – Input
If the low-speed memory used requires an extended memory cycle, appliyng an asynchronous Low level signal to this
pin causes the DMAC to place wait cycles on its internal state to extend the memory read/write cycle.
7 HLDA (Hold Acknowledge) – Input
This pin accepts an BUSAK signal returned from the CPU (Z-80) when the CPU acknowledges a hold request. The
signal indicates that the DMAC (µPD8257) has acquired bus access control. Once this signal is returned, the bus
outputs of the CPU are set to high impedance.
8 ADDSTB (Address Strobe) – Output
This pin is normally connected to the STB Input of the µPD8212 as a strobe, which is used to write the upper byte of
memory address from the data bus into the µPD8212 .
9 AEN (Address Enable) – Output
This pin is used to set the address and control bus outputs of the Z-80 CPU to high impedance if needed. It may also be
used to disable the system address bus by using the enable input of the address bus driver within the system. This is to
disable any response from non-DMA devices during the DMA cycle.
It may also be used to disconnect the µPD8257’s data bus from the system data bus, so that no special timing restriction
be required for the sytem bus when the µPD8257 wants to transfer the upper byte of DMA address through its data bus.
When the µPD8257 is used for I/O device configuration (in contrast to memory map configuration), this AEN output is
disabled so that an I/O device is not selected when a DMA address is pleaced on the address bus. An I/O device must
be selected bye the DMA ack nowledge output to the four channels.
10 HRQ (Hold Request) – Output
This pin is used to request system bus access control. It is connected to the BUSRQ input of the Z-80 when only one
chip of µPD8257 is used in the system. When two or more chips are used, an additional priority encoder is required to
assign priority to the multiple HRQ signal lines.
11
CS (Chip Select) – Active Low input
When in the Slave mode, this pin enables the I/O Read or I/O Write input of the µPD8257 when the device is to be read
or written, respectively. When in the Master mode, the
CS is automatically disabled to prevent the device itself from
being selected during DMA operati on.
12 CLK (Clock) – Input
Clock in (4MHz)
13 RESET (Reset) – Input
This pin normally accepts an asynchronous Reset output from the CPU. The Reset signal resets all control signals and
places the device into the Slave mode. Once a Reset signal is received, the µPD8257 aborts its current operation
regardless of the device status and enters the Idle set (SI ).
25, 24, 14, 15
DACK0-DACK3 (DMA Acknowledge) – Act ive Low output
These pins indicate to the I/O devices attached to the respectiv e channels that the DMA cycle has been acknowledged.
19 – 16 DRQ0-DRQ3 (DMA Request) – Input
These Pins are independent, asynchronous DMA request channels used for I/O devices to request DMA cycle to the
µPD8257. DRQ3 has the lowest priority, while DRQ0 has the highest, as long as the Rotary Priority mode is not
selected. DRQn input is kept high until a
DACKn is received. During the Multi DMA Cycle mode (Burst mode), DRQn is
kept high until the
DACKn for the last cycle is received.
4 9
Page 53
Pin No. Signal name/in-out/Des c ript ion
30 – 26
23 22, 21
DO-D7 (Data Bus) – Input/output (3 state)
When the µPD8257 is programmed by the CPU (Z-80), the data bus accepts the upper/Lower byte of DMA address and
TC register value output from the CPU, or 8-bit data to be loaded into the Mode Set register (Slave mode). When the
CPU wants to read the value of the DMA address register, TC register, or status register, the data bus is used to transfer
the pertinent data value to the CPU (Slave mode).
During the DMA cycle (when the µPD8257 is bus master), the data bus is used to transfer the upper byte of memory
address from a DMA address register to the µPD8212. This address byte is transferred at the beginning of a DMA cycle.
The data bus is subsequently used to transfer memory data in the remaining portion of the DMA cycle.
32 – 35 A0-A3 (Address Bus) – Input/output (3 state)
When in the Slave mode, these pins serve as inputs to select a register to be read or written. Hen in the Master mode,
these pins output the lower 4 bits of 16-bit memory address.
37 – 40 A4-A7 (Address Bus) – Output (3 state)
When in the Master mode, these pins output bits 4-7 of the 16-bit memory address. Hen in the Slave mode, these pins
are ser to high impedance.
36 TC (Terminal Count) – Output
The TC output Indicates to the currently selected I/O device that the current DMA cycle is the last cycle of the data block.
If the TC stop bit of the Mode Set register is set, the selected channel will be automatically disabled at the end of the
DMA cycle.
The TC signal is output when bit 14 of the TC register on the selected channel is reset to zero. The value (n-1) must be
loaded in the lower 14 bits of the TC register, where "n" is the number of DMA cycles to be executed.
5. Oscillator Circuit
The LSI system clocks and transfer clocks for the ER-52TR system
are obtained by dividing a single master clock. The mas ter cl oc k (16.0
MHz) is applied to the CLK pin (pin 1) of the MB62H149, where it is
divided into system clocks for the individual LSI chips. The resulting
clocks of φ(4MHz) and TXC (1 or 0.5 MHz) appear at pins 8 and 71,,
respectively.
Fig. 25
6.Serial/Parallel Conversion for Data
Transmission
1) General
Since a serial synchronous transmission scheme is used for SRN
communications, serial/parallel conversion is equired on the sen
d/receive data. The serial/parallel converter circuit uses an MC68B54
Advanced Data Link Controller (ADLC). The ADLC converts D0-D7
parallel data into serial data in synchronicity with the TXC signal (pin
5), and converts serial data (RXD) into parallel in synchronicity with
the RXC signal (pin 4).
01
X1
16.0 [MHz]
CLK
TXC
Φ
To ADLC (1 or 0.48 [MHz})
System CLK (4 [MHz])
EID2
MB62H149
4 10
Page 54
Pin No. Symbol Pin name and function
Input/
Output
1 VSS Ground pin –
2
RTS This pin indicates that send data exists in the TxFIF0. If CR2b7 is set to one, this output is set to Low.
This pin is set to High when a Close flag has been transmitted after a frame is completed, an Abort is
transmitted, CR2b7 is reset in the Mark Idle state (RTS remains at Low if CR2b7 is reset to zero in any
state other than the Mark Idle state), or the
RESET input is held at Low.
(Requeset Data Input)
Out
3 RXD Receiver Data input to accept rec eiv ed data.
(Receiver Data Input)
In
4 RXC Receiver Clock input to accept a synchronizati on si gnal for the rec eiv ed data input .
(Receiver Clock Input)
In
5 TXC Transmi tt er Cloc k input, used to s ync hroniz e the trans m it data output.
When in the Loop mode (including Test mode), the signal at this pin must be in-phase with the RxC.
(Transmitter Clock Input)
In
6 TXD TRansmit Data output.
(Transmit Data output)
Out
7
IRQ Interrupt Request output. This pin is set Low if an interrupt occurred and the corresponding Enable bit
is set. It is set High when the cause of the interrupt is removed or the Enable bit is reset.
(Interrupt Request Output)
Out
8
RESET RESET input. If a Low signal is applied to this pin, the RxReset (CR1b6) and TxReset (CR1b7) are set
to one, which resets the Rx and Tx circuits, respectively. The TxAbort (CR4b5),
RTS (CR2b7), Loop
Mode (CR3b5), and
Loop on Line/DTR (CR367) are reset to zero.
All initial status conditions are reset. The
RTS and LOC/DTR output pins are set to High when the
corresponding control registers are reset, and the TxD output is plac ed in Mark Idl e s tat e.
While the
RESET inputs is kept at Low, none of the control register bits mentioned above can be
updated. If the RESET input is set to High, the reset condition continues until CR1b6 and CR1b7 are
reset to zeros by software.
(RESET Input)
In
9
CS Chip Select input. Read/write access to the device is enabled only if this input is Low and the Enable
input is High.
(Chip Select Input)
In
10
11
RS0
RS1
Register Select inputs. These inputs are used with the R/W input (CR1b0) to address a register within
the device for read/write access.
(Register Select Input)
In
12 R/W Read/Write Control input used to indecate tha direction of the data flow.
The Data I/O buffer is placed in the Output mode if this input is High; it is placed in Input mode if this
Low.
(Read/Write Control Input)
In
13 E Enable Clock input used to time the CS, RS0, RS1, and R/W inputs. Data read/write access to the
device is enabled only if this input is kept high.
This pin is also used for data transfer through the RxFI FO of T xFI FO .
(Enable Clock Input)
In
14 VCC This pin accepts a +5V power supply.
(Voltage Source)
I/O
15 ∼22 D7 – D0 Bidirectional data bus used to transfer data with the system. It is a three-state bus except during Read
access.
(Data Bus)
I/O
23 RDSR Receive Data Service Request output. This pin reflects the value of ST1b0. A high state of this pin
indicates that the RxFIFO is in request for serv i ce.
When the RxFIFO is read, the RDSR outputs is reset to Low. (The RxFIFO here refers to the one
(CR2b1 = 0) or two (CR2b1 = 1) nearest to the data bus.)
When in the Preferred Status mode (CR2b0 = 1) , this pin is kept Low as long as the other status
condition exists.
(Receive Data Service Request Output)
Out
24 TDSR Transmitter Data Service Request output. This pin outputs the value of ST1b6 in any mode other than
the FC mode (CR2b3 = 1). A high state of this pin indicates that the TxFIFO requests service. When
data is written into the TxFIFO, the RDSR is reset to Low. (The TxFIFO here refers to the one (CR2b1
= 0) or two (CR2b1 = 1) nearest to the data bus.)
This pin is kept Low when the
RESET pin is at an active Low. CTS pin is High, or CR1b7 is High.
When in the Preferred Status mode (CR2b0 = 1), this pin is also kept High if the Tx-Underrun condition
exists.
(Transmitter Data Service Request Output)
Out
25
FD Flag Detect output. This pin remains Low for a one-bit time interval (while Receiver Clock = RxC) after
the last flag bit is detected.
(Flag Detect Output)
Out
4 11
Page 55
Pin No. Symbol Pin name and function
Input/
Output
26
LOC/DTR Loop On Line Control/Data Terminal Ready output. This pin functions as the DTR in any mode other
than Loop mode (CR3b5 = 0). It is set Low if CR3b7 is set to one, and is set High when the same bit is
set to zero.
When in the Loop mode (CR3b5 = 1), this pin functions as the
LOC, which is used to control the
external loop interface hardware between On Loop and Off Loop.
If CR3b7 is set to zero, this pin is set High when RxD = 01111111 is detected, causing the hardware to
go into the On Loop. If CR3b7 is set to zero, this pin is set High when RxD = 11111111 is detected,
causing the hardware to return to the Off Loop.
If the
RESET input is set Low, CR3b5 is set to zero (Non-Loop Mode), which sets CR3b7 to zero. As a
result, this pin issues a High level signal.
(Loop On Line Control/Data Terminal Ready Output)
Out
28
CTS Clear to Send input. Setting this pin to High disables ST1b6 and related IRQ.
If SR1b4 is set and this pin is enabled, an IRQ is issued. Low-to-High transition at the CTS input is set
in SR1b4, which is cleared by CR2b6 or CR1b7.
(Clear to Send Input)
In
27
DCD Loop On Line Control/Data Terminal Ready output. Setting this pin to High resets the Receiver register
and sets SR2b5, which causes an IRQ to be issued if enabled. Low-to-High transition at the DCD input
is set in ST2b5, which cleared by CR2b5 or CR1b6.
(Loop On Line Control/Data Terminal Ready Output)
In
4 12
Page 56
3) Pin Configuration (top view)
Fig. 26
7. Modulator/Demodulatro circuit
Phase encoding (PE) modulation is used for SRN communications.
The PE modulation has a changing point in the signal at the center of
the bit, the timing signal is regenerated from this signal, making the
modulation and demodulation simpler by providing continuous signals
for the DC conponents.
Fig. 27 PE Modulation
Serial send data applied from the ADLC to TXD (pin 72) of the
MB62H149 and the TXC synchronization signal is subject to PE
modulation. The resulting signal is output through TDI (pin 67) of the
MB62H149 to the transmission driver.
Received data is applied from the receiver to RDI (pin 66) of the
MB62H149, where it is demodulated into serial receive data and
synchronization clock. They are output to the ADLC through RXS (pin
70) and RXC (pin 69), respectively.
The modulator and demodulator are located within the MB62H149.
8. Transmitter and Receiver Circuits
1) Transmitter
The modulated send data output through TDI (pin 67) of the
MB62H149 is controlled by the
RTS (Request to Send) signal
transferred from the ADLC during transm is si on.
The TDI is NAND’ed with
RTS, so that data transmission is disabled
when the
RTS is high.
RTS is Low state during transmission and T rans i stor Q2 is turned ON.
When transmitting data "1", the output at pin 12 of the NAND gate
(IC7) is set Low. (the
RTS is Low) Since pin 11
of the following transistor (IC7) is set Low, it is turned off.
When hte
RTS is set Low , transi stor Q1 turned on through an invert e r,
which applies a bese current to Q2, turnit it on. When Q2 and pins 10
and 9 of IC7 are turned on, the output transistors IC7 (pins 6 and 5)
are turned on. Since the output trasistors are common-emitter circuit,
data "1" is obtained at LINE.
Fig. 28
2) Receiver
The receiver provides the following two func tions :
1) Data reception
2) Collision detection
Fig. 16-29
1 Data reception
The 75115 is a dual-channel receiver containing two comparators.
One of the comparators is used to detect received data (RDI). The
data received from the line is applied to the negative input (pin 5)
of the comparator. The received data is also amplified by Q3,
integrated by R15 and C32, and voltage-divided by R17 and VR1
before being applied to the positive input (pin 7) of the same
comparator, This assures reliable identification of "0" and "1"
levels even if the received data signal is distorted due to a lond
line length.
Note: If Transistor Q1 is replaced for servicing, the VR1 requires
readjustment. See the section for adjustment.
CTS
DCD
DTR/LOC
FD
TDSR
RDSR
D0
D1
D2
D3
D4
D5
D6
D7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
RTS
RXD
RXC
TXC
TXD
IRQ
RESET
CS
RS0
RS1
R/W
E
VCC
Data
NRZ
PE
011001 10
+12V
+5V
Transmitter
LINE
GND
COL
RDI
14
15
13
9
11
R23
1.2K
Q3
R15
3.9K
R16
1K
C32
3300P
R17
1.5K
VR1
2
1
7
8
+5V
12K
RTS
75115
34
R28
15K
+12V
Transm it data
20K
SN75450BN
LINE
GND
R1
15
R10
220
4
5
6
IC7
+12V
R20
820
R3
1K
R22
560
Q14
74HC04
1
13
12
7
SN75450 BN
RTS
TDI
11
10
9
R24
220
R25
470
+5V
IC7
RTS
TDI
Q2
4 13
Page 57
2 Collision detection
The other comparator in the 75115 is used for coll is i on detec tion.
The SRN communication uses only a single transmission line, and
the transmission line is connected to each terminal. Only one pair
of terminals can communicate with each other over the transmission line at a time. If the transmission line is busy, other terminals
must wait to transmit until the line becomes available. The line
busy condition is monitored by the collision detector. The line
signal is applied to the positive input (pin 9) of the comparator,
while the local send signal is applied to the negative input (pin 11)
of the same comparator, so that correct transmission can be monitored by comparing the line signal with the transmission signal. If
two terminals attempt transmiss i on at the same tim e, data collision
will occur on te line, which results in the line signal being different
from the local transmission signal. Detecting this difference, the
collision detector outputs a COL signal to indic at e it to the CPU.
9. Collision detect circuit
The access system employs the carrier sense multiple access with
collision detect (CSMA/CD) with a BUS type topology. The access
system has no control station on the network and checks the space
area condition of the circuit according to the prosece is available.
Collision is detected sometimes due to the delay on the circuit or the
simulataneous data sending, but the collision is detected immediately
by the collision detect circuit and prevents the deterioration of the
transmission efficiency by ptoviding the backoff process (binary
exponential backoff). The carrier sence is detected by the two stages
of the dta packet and response packet to prevent the collision of the
response packet. This permits higher efficiency for heavy loads.
Collision detect circuit is located within the MB62H149 custom LSI.
10. Carrier detect circuit
This circuit detects whether data is flowing on the transmission line. It
consists of a circuit which immediately senses a no data status on the
line.
Fig. 30
When data is not on the line the circuit functions to sense an elapse
of the fixed time rate the immediate sensing circuit is used for
response testing and the delayed sensing circuit is used for data
testing.
This circuit is located within MB62H149 custom LSI.
1 1 . ADJUSTMENT FOR SRN
(IN-LINE) INTERFACE BOARD
If transistor Q3 in the transmitter/receiver section has been replaced
or if the SRN level requires readjustment, the following alignment is
required:
1) Tools and Instruments Required
1 Oscilloscope (50MHz or better). . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 ER-A570 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 ER-A57R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2) Dummy Network Specifications
Fig. 1 Dummy network
The oscillator should be connected to the points indicated by ⊕ and
∃ .
⊕: Connect the positive side of the oscillator.
∃
: Connect the negative side of the oscillator .
3) Connections
Fig. 2
1 Attach the expansion PWB (CKO G–6708RCZ Z) to the mai n PWB.
2 Attach the ER-A6IN to the expansion PWB. (Place a base under
the ER-A6IN to stabilize it.)
3 Attach the BNC connector (QCNW–6856RCZZ) to the ER-A6I N.
4) Alignment Procedure
1 When Using an Oscillator
a) Checking the 1MHz os ci ll at or output
Using an oscilloscope c heck the 1MHz oscillator’s output waveform.
Fig. 3 1MHz oscillator output wavef orm
NOTE: The oscillator used should have an output impedance of
50Ω.
MB62H149
75115
65 COL 15
LINE
R1 100 Ω J (1/4W carbon)
R2 150
Ω
J (1/4W carbon)
C1 0.01µ F (mylar firm)
C1
R1
R2
Main PWB
Expansion PWB
(CKOG-6708RCZZ)
ER-A6IN
Base
BNC connector
(QCNW-6856RCZZ)
5V
0V
0.5µ S 0.5µ S
4 14
Page 58
b) Connecting the oscillator and its adjustment
Connect a dummy network or branch-trunk network on to the output
of the ER-A6IN installed in the ER-A570, and connect the oscillator to
the dummy or branch-trunk network.
Fig. 4 Connection
∗ Waveform adjustment
Adjust VR1 until the signal waveform as shown in Fig. 5 is obtained
across TP (pin 1 of the 751 15) and GND pi n.
Turning VR1 clockwise extends the interv al of T1.
Fig. 5 Receiver regeneration waveform (with dummy network )
Fig. 6 Board location
2 When the Branch Trunk Network and Two
ECR’S are Available.
a) Connecting terminals
Both ends of the network must be terminated with a 50Ω terminator. If
only two active terminals are to be tested and left on the network,
disconnect all other terminals from the network. (In this case as well,
both ends of the trunk network must be terminated with 50Ω).
Fig. 7 Terminal connection
b) Receive level adjustment
i) Turn on both the objective terminal of receive level adjustment
(receiver terminal) and the terminal which sends the adjusting
signal (transmitter terminal).
ii) Run the diagnostic program JOB#603 on the transmitter terminal
to send a flag.
Key operations: MODE switch: SRV position
iii) Checking transmitter terminals’ output wavef orm
Using an oscilloscope, check the transmitter terminal’s output
signal waveform.
Fig. 8 Transmitter terminal’s output waveform
(at transmitter output)
At the receiver terminal, the transmitter terminal’s output
waveform is subject to attenuation and distortion due to the length
of the trunk cable (this depends on the characteristics of the cable
itself).
Fig. 9 Example of distorted signal waveform at the receiver terminal
(RG58/U 400m)
With the receiver terminal adjust VR1 (5kΩ) on the ER-A6IN board
until the waveform as shown in Fig. 10 is obtained at TP (pin 1 of the
75115). (For the location of VR1, see Fig. 6 Board location of this
subsection).
Clockwise rotation of VR1 extends the High level pulse width of the
signal at TP (pin 1 of the 75115).
Fig. 10 Waveform at TP (pin 1 of the 75115 IC in the receiver
terminal)
5)Other Checks (These Checks should be
done After the Receive Level Adjustment
is Completed).
1 Line driver bias control circuit
Make sure that the voltage at the Α -side lead of the R3 resistor
(150Ω, 3W) shown in Fig. 6 is properly switched.
Procedure:
i) Connect a terminating resistor or read network to the BNC con-
nector, QCNW-6856RCZZ (Fig. 2).
ii) Run the diagnostic program JOB#604, and make sure that the
voltage at point
Α (in Fig. 6) is switched as shown in Fig. 10.
Fig. 11 bias circuit switching waveform
Key operation:
iii) If the waveform as shown in Fig. 15 is not obtained, it is most
probable that transistor Q3 (2SA509) is defective.
2 For the other check items, refer to III. TEST FUNCTION.
C1R1
R2
OSC
SRN connector
VOH
VOL
T1 = 580 to 620ms
T2 = 380 to 420ms
T1 T2
MC68B54
F1
VR1
IRCCN
R3
A
GND PIN
TP
CPWBX7317RC01
Parts surface
ER-A670/A650
R50
Ω
R50
Ω
ER-A670/A650
601 TL
1µ S 1µ S
3.8V
0.8V
1µ S 1µ S
12V
0V
4.3ms
17ms
602 TL
4 15
Page 59
12. Circuit diagram
4
1
3
5
6
2
4
1
3
5
6
2
A
B
CD
E
FGH
I
A
B
CD
E
FGH
I
1
SRCS
2DMACS34
AB85AB76AB6
7TCH89
10
11
DB012DB1
13
DB2
14DB3
15
16
DB4
17
DB518DB619DB7
20
21AB0
22AB1
23AB2
24AB3
25AB4
26AB52728
29CS
30
80797877767574 AB19
73
AB20
72
AB21
71
AB2270AB2369DH7
68
DH6
67 DH5
66
DH4
65
64
DH363DH262DH1
61
DH0
60 AS
59
TRNRDY
58
RCVDT
57
RCVRDY56TRNEMP55BRK
54
ADSTB
53 XOUT5251
DRES
100
AB9
99
BREQ
98
AB11
97
AB12
96
95
94
AB17
93
AB13
92
91
1M
90
89
88
AB14
87
AB15
86
AB16
85
83
82 CTS
81 DCD
31
32DAK
33AH1
34RDH
35AH0
36UCS
37WRH
38SINT
39
40
41AENH
42SREST
43
AB10
44HRQ
45IORD
46IOWR
47
AB18
48CI
49RTS
50HLDAK
D0D1D2D3D4D5D6
D7
NC
C26
C25
C24
ASTB
X1
X2
GND
VCC
TRRQ
TRV
CS0
P0
VCC
GND
AEN
TXE
HLDRD
OPC1
IC16
RES
OPTCS
DB0~7
TCH
SRCS
DACK2
RSRQ
POFF
TRQ1
WRO
TRRQ
AB0~23
BREQ
RDO
R14
+5V
R45
DACK3
X2
R12
+5V
+5V
C56
SW
103 x 3
1
2
3
R48 TC
READY
R46
R11
RA2
AS
DAK
AH1
RDH
AH0
WRH
SINT
SREST
R39
10K
C48
330P
10K x 5
R49
R40
R41
R22
R43 10K
R44
10K
(BACK )
C22
103
R10
R9
DH0~DH7
10K
22
R4
10K
R5
10K
R22
10K
R6
R42
BACK
ER-A6IN 1/2
4 16
Page 60
4
1
3
5
6
2
4
1
3
5
6
2
A
B
CDE
F
G
H
I
A
B
CD
E
F
G
H
I
11292325141512
879
101328
12345
6
24
31
2014151617
8
9361
2
302928272623222113
VCC
GND
DACK2
DACK3
DRQ3
DRQ2
ASTB
AENTCIO/RD
IO/WRD0D1D2D3D4D5D6D7
RES
19
18751042524
MRO
323334353738394011126
DRQ0
DRQ1
HLDA
MARK
MLDRQ
MWR
DAK0
DAK1
MRD
A0A1A2A3A4A5A6
A7
CS
CLK
RDT
IC8
DMAC
HC00
10
3
1
2
+5V
DAK23
C11
10µ
16V
C46
0.1µ
TCS
C45
C44
C43
C42
C41
C40
C39
C38
D0D1D2D3D4D5D6
D7
21
4
MC04
12
12
13
11
14
VRAM
4
5
6
12
14
VRAM
HC00 HC00
RES
SREST
VCC
GND
BUSAR
BUSROD0D1D2D3D4D5D6D7
RFSH
27
16
18
4030313233343536373839
26
1719202122
M1
INT
HALT
A10
A0A1A2A3A4A5A6A7A8
A9
RES
NM1
MREQ
IOREQ
RD
WR
IC3
Z-80 CPU
µPD8257-2 TMPZ84C00P
141213
116252627
28
123
4
15
M1
INT
IEI
IEORDD0D1D2D3D4D5D6D7Φ
24
5721232022891618191710
VCC
GND
Z/T0
CLK2
CLK0
CLK3
CLK1
Z/T1
Z/T2
CE
CS0
CS1
RES
IOREQ
IC1
Z-80 CTC
TMP284C30P
26
2712814111213151617181922
A13
NC/A14
VPP/A15
VCC
GNDD0D1D2D3D4D5D6D7
OE
10
987654325242123
2
20
A0A1A2A3A4A5A6A7A8
A9
A10
A11
A12
CE
ROM
IC13
10
9876543
252421
27
22
1
A0A1A2A3A4A5A6A7A8A9A10WEOE
NC
20281411121315161718192623
2
CS1
VDD
GND
D0D1D2D3D4D5D6
D7
CS2
A11
A12
256 (512)
141282610119713
65342
VCC
VSS
CTS
LOC
RS0
RS1CSIRQETXD
TXC
RXD
RXC
RTS
23
2481225272221201918171615
RDSR
TDSR
RES
R/W
FDT
DCD
D0D1D2D3D4D5D6
D7
IC2
ADCL
10
4
4
10 11
98
HC04
HC04
5
4
6
HC00
BUSAR
BUSRQ
DAKS
A0A1A2A3A4A5A6
A7
BR4
+
C2
10µ/16V
C62
0.1µ
+5V
D0D1
D1D2
D2D4
D3D6
D5D0
D6D3
D7D5
D4
D7
+5V
RA1
40
TCS38AEN39AST42DRQRS43DRQWS41DACK23
44
RDH45WRH
337334NC53NC125251CS54
DB055DB156DB257DB358DB459DB560DB6
20A119A418A517A816A915
A1014A15
3
IOREQ
4
MREQ
5
RDS
6
WRS
7
INTS
24
MWR
80
MSK
79
RS078RS1
76
LCS
75
IRQ
74E72
TXD71TXC
70
RXD
32
D0
31
D1
30
D2
29
D3
28
D4
27
D5
26
D6
25
D7
11
MRQ
8
Φ
35
RES
37
IO/RD
22
DAK01
36
IO/WR
13
WATI
21
A0
61
DB7
47
DAK
48
TCH
49
DRQRH
50
DRQWH
46
INTH
64
AB1
62
AB0
65
CDL
66
RDI
67
TDI
1
CLK
9
TM0
10
TM1
68
RTS
69
RXC
IC5
M862H149
NC:
2PIN
23PIN
63PIN
77PIN
+5V
TCS
AEN
ASTB
DRQ2
DRQ3
DAK23
RDH
WRH
+
C6
0.1M
12V
RSCS
C7
10M/16V
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DH0~7
DAK
TCH
DRRH
DRWH
SINT
AH0
AH1
A1A4A5A8A9
A10
A15
IORQ
MRQ
RDS
WRS
INTS
MWR
RDS
RS0
RS1
LCS
IRQECTXD
TXC
RXD
+5V
C36
0.1µ
R34
C34
220P
RXC
RTS
TM1
TM0
CLK (16MHz)
RTS
MC68854
D0
D1
D2
D3
D4
D5
D6
D7
MRQ
Φ
A0
13 12
4
HC04
Φ
(4M)
100P x 8
Φ
(4MHz)
IO/WR
IO/RD
SRES
Φ
(4M)
WAIT
A11
A12
A13
A14
A15ΦVAIT
A11
A12
A13
A14
A15
RA4
Φ
3K-8
10K-12
R35
R36
R29
A10A0A1A2A3A4A5A6A7A8A9
RA3
C1
220P
RA4
MRQ
IORQ
RDS
WRS
C35
330P
R30
R32
12
+5V
+5V
+5V
+5V
D0D1D2D3D4D5D6
D7
RDS
Φ
9
8
9
10
DRQ0
9
11
12
13
DRQ1
TDSR
MSK
RDSR
C3
0.1µ/12V
A13
+
C13
10µ
16V
C14
0.1µ
TMI
INTS
D0D1D2D3D4D5D6
D7
A6A0A1
MRD
MWR
MWR
A0A1A2A3A4A5A6A7A8
A9
A10
A11
A12
A0A1A2A3A4A5A6A7A8A9A10
VRAM
C19
100P
C20
0.1µ
RAM
IC14
D0D1D2D3D4D5D6
D7
C49VRAM
8
A15 9
10
C47
1000P
HC00
SRES
HC08
HC08
9
3
2
1
4
+5V
+5V
9
TCS
DAKS
HC08
6
5
4
IO/WR
MRD
HC08
RDSR
TDSR
SRES
D0D1D2D3D4D5D6
D7
123
Q1
VSS
VCC
X1
C4
0.1µ
4
4
65
16.0MHz
HC04
RTS
TDI
15
2YS142YP132STB61RT102RT122RS11YS21YP
92A71A3
1STB
16
VCC
8
GND
4
1RS
51B11
2B
7
+5V
7
+5V
+5V
+5V
+5V
+12V
+
C9
47µ/35V
R20
820
R21
1K
R22
560
Q2
Q1
34
74HC04
R25
470
1
13
12
R24
220
R3
150
3W
11
10
9
SN75450BN
D5
D4
SN75450BN
R19
1K
C33
220P
F1
250mA
R16
1K
1
2
3
NU
NU
RTS
R18
560
SN75450BN
SN75450BN
D6
C8
0.1M
50V
R11S3W
D3
D1
D2
FB1
R2511/2W
BZ
LIN 1
GND 2
GND
FB2
Q3
R23
1.2K
C
R15
3.9KG
C32
3300P
VR1
20K
R17
1.5KG
R27
12K
R26
12K
C34
0.1µ
R28
15K
CQL
RTS
RDI
NUNUNU
IC6
7S115
GND (S)
10K-8
10K-5
10K x 5
10K
1SS353 x 2
1SS353 x 2
STPB54V
R31
R37
R38
2/2
4 17
Page 61
C
D
B
A
1
2
3
4
6
C
D
B
A
5
1
2
3
4
6
5
No. No.SIGNAL SIGNAL
1 36 GNDGND
2 37 GNDGND
3 38 GNDGND
439
(φ)
RDO
5 40 NU1WRO
6 41 +5VBREQ
7 42 +5VBACK
8 43 TRQ2A23
9 44 TRQ1A22
10 45 EXINT1A21
11 46 EXINT0A20
12 47 TRRQA19
13 48 RSRHA18
14 49 RFSHA17
15 50 IPLONA16
16 51 D7A15
17 52 D6A14
18 53 D5A13
19 54 D4A12
20 55 D3A11
21 56 D2A10
22 57 D1A9
23 58 D0A8
24 59 POFFA7
25 60 VRAMA6
26 61 A3A5
27 62 (+12V)A4
28 63 +24V+24V
29 64 +24V+24V
30 65 A2A1
31 66 RESA0
32 67 ASRESET
33 68 NU2OPTCS
34 69 GNDGNDP
35 70 GNDGNDP
No. No.SIGNAL SIGNAL
1
36
GNDGND
2
37
GNDGND
3
38
4
39
(φ)
RDO
5
40
NU1
WRO
6
41
+5V
BREQ
7
42
+5V
BACK
8
43
TRQ2
A23
9
44
TRQ1
A22
10
45
EXINT1
A21
11
46
EXINT0
A20
12
47
TRRQ
A19
13
48
RSRQ
A18
14
49
RFSH
A17
15
50
IPLON
A16
16
51
D7
A15
17
52
D6
A14
18
53
D5
A13
19
54
D4
A12
20
55
D3
A11
21
56
D2
A10
22
57
D1
A9
23
58
D0
A8
24
59
POFF
A7
25
60
VRAM
A6
26
61
A3
A5
27
62
(+12V)
A4
28
63
+24V
+24V
29
64
+24V
+24V
30
65
A2
A1
31
66
RESA0
32
67
AS
RESET
33
68
NU2
OPTCS
34
GND
GNDP
GND
GNDP
35
OPTCN2OPTCN1
ER-A6IN
No. SIGNAL
1
2
LIN
GND
IRCCN
4 18
Page 62
13. PWB layout
1 Parts side
4 19
Page 63
2 Solder side
4 20
Page 64
CHAPTER 2. ER-A5RS
1. General
The ER-A5RS is composed of the following blocks:
1) RS-232 receiver (75189A)
2) RS-232 driver (75188)
3) USART (MB89371A)
4) Gate array (OPC1: F256004PJ)
2. Block diagram
3. Description of main LSI
3-1. OPC1 (F256004PJ)
1) General description
The OPC1 is a gate array of integrated peripheral circuits of RS232/Simple IRC interface.
One chip of the OPC1 is equipped with four communication circuits.
(Three of them are for RS-232 only: UNIT 0 ~ 2, one is for selection
of simple IRC/RS-232: UNIT 3)
The ER-A5RS uses UNIT0 (RS-232 interface) and UNIT7 (RS-232
interface).
UNIT NO. Purpose ER-A5RS
UNIT0 RS-232 Used.
UNIT1 RS-232 Used.
UNIT2 RS-232 Not used.
UNIT3 RS-232/Simple IRC Not used.
Each UNIT of the OPC1 has the following functions :
1 Timer function
Used for the timer between characters in data reception.
2 Address decode
USART chip select output and own select.
3 Interruption control
RSRQ, TRRQ output using outputs from USART (TRNRDY,
TRNEMP, RCVRDY, BRK) and RS-232 control signals (
CI, CTS,
CD) as interruption factors.
(For the simple IRC, TRNEMP is excluded.)
∗
RSRQ:
TRRQ(Not used):
For RS-232
For simple IRC
4 Simple IRC send/receive control (UNIT3 only) : Not used
2) Pin configuration
CS1,CS2
A0~A5
R,W
RDO,WRO
DB0~7
OPTCS
INT ( )
D0~D7
RES
RES,POFF
CLOK
RSRQ,TRQ1
AB0,1
DCD1,2 CI1,2
RCVDT1,2 CTS1,2
USART
DSR1,2
RS-232
Reciever
DTR1,2 TRNDT1,2
CD1,2 CI1,2
RD1,2 CS1,2
DR1,2
ER1,2 SD1,2
RS-232
Driver
RS1,2
Power
supply
circuit
+12V
-12V
RTS1,2
OPC1
PX
+24V
INT ( ): TRNRDY1,2 RCVRDY1,2 TRNEMP1,2 BRK1,2
CS3
CS2
TRNEMP3
BRK3
TRANDY3
RCVRDY3
RXDATA0
TRCK
RES
OPTCS
D0
D1
D2
D3
GND
D4
D5
D6
D7
RSRQ
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TRNEMP2
CI3/P2I
TRNRDY2
RCVDT2
SL21
SL20
SL32
SL31X1X2
GND
VCC
CD2
CI2
CTS2
USICH
TRRQ
TRV
CTS0
CD0
SL00
SL01
SL02
SL10
SL11
100
99
98
97
96
95949392919089888786858483
828180
79
787776
A5
POFF
TRQ1
WRO
RDO
CS1
AB1RAB0
CS0
W
CD3/P0
VCC
GND
RCVDT3
TXE
CTS3/P1
RTS1
CI1
CD1
CTS1
CI0
RTS0
PX
2627282930313233343536
37383940414243
444546
47
484950
SL12
RCVRDY2
RCVDT1
RCVRDY1
TRNRDY1
BRK1
DB7
DB6
DB5
DB4
GND
DB3
DB2
DB1
DB0
TRNEMP1
TRNRDY0
RCVDT0
RCVRDY0
TRNEMP0
BRK0
SL30
XOUT
SL22
RES
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OPC1
F256004PJ
TRQ2
4 21
Page 65
3) Block diagram
D7
D6
D5
D4
D3
D2
D1
D0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data bus buffer
WRO
RDO
RES
W
R
RES
Read/write
control
A5
A4
A3
A2
A1
A0
SL00
CS0
Decorder
control
SL01
SL02
SL10
SL11
SL12
SL20
SL21
SL22
SL30
SL31
SL32
TRV
USICH
CS3
CS2
CS1
Chanel select control
CHSL
PX
TO/FROM USART
RXDATA0
TXE
X1X2XOUT
TBCK
Inline
cont
OCS
TCR0
Timer0 control
Timer0
RCVDT0
TCR1
Timer1 control
Timer1
RCVDT1
TCR2
Timer2 control
Timer2
RCVDT2
TCR3
Timer3 control
Timer3
RCVDT3
RTS CNT
RTS1
RTS0
POFF
RSRQ
TRRQ
TRQ1
TRQ2
Power
supply
cont.
RCVRDY3
RCVRDY2
RCVRDY1
RCVRDY0
TRNEMP3
TRNEMP2
TRNEMP1
TRNEMP0
Interrupt control
CI0
CI1
CI2
CI3/P2I
CD0
CD1
CD2
CD3/P0
CTS0
CTS1
CTS2
CTS3/P1
BRK0
BRK1
BRK3
TRNRDY0
TRNRDY1
TRNRDY2
TRNRDY3
AB1
AB0
4 22
Page 66
4) Pin description
OPC1 pin table The signals marked with "-" at the end are LOW active signals. Example: "CS1-" = "CS1"
No. Pin No. Pin name I/O Pin ER-A5RS Description
1 80 SL00 I ICU SL00 RS-232/UNIT0 channel select
2 79 SL01 I ICU SL01
3 78 SL02 I ICU SL02
4 77 SL10 I ICU SL10 RS-232/UNIT1 channel select
5 76 SL11 I ICU SL11
6 75 SL12 I ICU SL12
7 95 SL20 I ICU GND RS-232/UNIT2 channel select
8 96 SL21 I ICU GND
9 52 SL22 I ICU GND
10 54 SL30 I ICU GND RS-232/UNIT3 channel select
11 93 SL31 I ICU GND
12 94 SL32 I ICU GND
13 36 CS0- O O CS1- RS-232 USART chip select
14 32 CS1- O O CS215 2 CS2- O O NC
16 1 CS3- O O NC RS-232/INLINE USART chip select
17 81 CD0- I IS DCD1- RS-232 control signal CD- input
18 46 CD1- I IS DCD219 88 CD2- I IS GND
20 38 CD3-/P0- I IS GND RS-232 CD-/INLINE P021 82 CTS0- I IS CTS1- RS-232 control signal CTS- input
22 47 CTS1- I IS CTS223 86 CTS2- I IS GND
24 43 CTS3-/P1- I IS GND RS-232 CTS-/INLINE P125 48 CI0- I IS CI1- RS-232 control signal CI- input
26 45 CI1- I IS CI227 87 CI2- I IS GND
28 99 CI3-/P2I I IS GND RS-232 CI-/INLINE P2I
29 55 BRK0 I ISC BRK1 RS-232 USART BREAK signal
30 70 BRK1 I ISC BRK2
31 27 POFF- I IS POFF- POFF signal (LOW : P-OF F, HIGH: P-O N )
32 4 BRK3 I IS GND RS-232/INLINE USART BREAK signal
33 57 RCVRDY0 I ISC RCVRDY1 RS-232 USART RCVRDY signal
34 72 RCVRDY1 I ISC RCVRDY2
35 74 RCVRDY2 I ISC GND
36 6 RCVRDY3 I IS GND RS-232/INLINE USART RCVRDY signal
37 59 TRNRDY0 I ISC TRNRDY1 RS-232 USART TRNRDY signal
38 71 TRNRDY1 I ISC TRNRDY2
39 98 TRNRDY2 I ISC GND
40 5 TRNRDY3 I IS GND RS-232/INLINE USART TRNRDY signal
41 56 TRNEMP0 I ISC TRNEMP1 RS-232 USART TRNEMP signal
42 60 TRNEMP1 I ISC TRNEMP2
43 100 TRNEMP2 I ISC GND
44 3 TRNEMP3 I IS GND RS-232/INLINE USART TRNEMP signal
45 58 RCVDT0 I ISC RCVDT1 RS-232 RCVDT signal (LOW: TIMER START)
46 73 RCVDT1 I ISC RCVDT2
47 97 RCVDT2 I ISC GND
48 41 RCVDT3 I IS GND RS-232/INLINE RCVDT signal
49 20 RSRQ- O 3S RSRQ- RS-232 IRQ- signal
50 83 TRV- I ISC +5V INLINE YES/NO
51 7 RXDATA0 O O NC INLINE RXDA TA OUT
52 42 TXE O O NC INLINE TRNS ENABLE
53 84 TRRQ- O 3S NC INLINE IRQ- signal
54 28 TRQ1- O 3S
TRQ1 TIMER IRQ signal (RS-232)
4 23
Page 67
No. Pin No. Pin name I/O Pin ER-A5RS Description
55 29 TRQ2- O 3S NC TIMER IRQ signal (INLINE)
56 11 D0 I/O IOU D0 DATA BUS (MAIN)
57 12 D1 I/O IOU D1
58 13 D2 I/O IOU D2
59 14 D3 I/O IOU D3
60 16 D4 I/O IOU D4
61 17 D5 I/O IOU D5
62 18 D6 I/O IOU D6
63 19 D7 I/O IOU D7
64 61 DB0 I/O IOU DB0 DATA BUS (USART)
65 62 DB1 I/O IOU DB1
66 63 DB2 I/O IOU DB2
67 64 DB3 I/O IOU DB3
68 66 DB4 I/O IOU DB4
69 67 DB5 I/O IOU DB5
70 68 DB6 I/O IOU DB6
71 69 DB7 I/O IOU DB7
72 21 A0 I I A0 ADDRESS BUS (MAIN)
73 22 A1 I I A1
74 23 A2 I I A2
75 24 A3 I I A3
76 25 A4 I I A4
77 26 A5 I I A5
78 10 OPTCS- I I OPTCS- OPTION CHIP SELECT (from MAIN)
79 31 RDO- I I RDO- READ signal (from MAIN)
80 30 WRO- I I WRO- WRITE signal (from MAIN)
81 9 RES- I IS RES- RESET signal (from MAIN)
82 34 R- O O R- READ signal (To USART)
83 37 W- O O W- WRITE signal (To USART)
84 51 RES O O RES RESET signal (To USART)
85 92 X1 O X1 Oscillation c irc ui t
86 91 X2 I X2
87 53 XOUT O O XOUT Clock for USART
88 8 TRCK O O NC T/R clock for 1CH USART
89 35 AB0 O O AB0 Address bus for USART
90 33 AB1 O O AB1
91 85 USICH I ISC GND UNIT3 USART 1CH/2CH select
92 50 PX O PX Power source clock
93 39 VCC +5V
94 89 VCC +5V
95 15 GND GND
96 40 GND GND
97 65 GND GND
98 90 GND GND
99 49 RTS0- O O RTS1- RS-232 control signal RTS- output
100 44 RTS1- O O RTS2-
ICU : CMOS level input (internal pullup resistor)
O : Output
IS : TTL level input (internal schmit circuit)
ISC : CMOS level input (internal schmit circuit )
3S : Three state output
IOU : I/O port (internal pullup resistor)
4 24
Page 68
3-2. USART (MB89371A)
1) General
The MB89371A (Serial data transmitter/receiver, 2 units) is a versatile-use interface LSI for communication lines, which is equipped with
two sets of equivalent units of the MB89251A (serial data transmitter/receiver), the baud rate generating section, and the interruption
adjustment section.
It is positioned between the line Modem and the computer, and used
for serial/parallel conversion of data, data send/receive operation
check, and the synchronization mode selection according to the program assignment.
The transmitter section converts parallel data into serial data, and
adds the parity bit, the start bit, and the stop bit to them, and transmits them. In the synchronization mode, it transmits synchronization
characters during no transmission data period. In the advancement
synchronization mode, it allows selection of transmission clocks and
transmission baud rates.
The receiving section converts serial data into parallel data, and
checks parities to judge that data are properly transmitted.
In the synchronization mode, it detects synchronization characters
and makes synchronization of transmission/reception operations with
the transmitter side. In the advancement synchronization mode, it
allows selection of transmission clocks and reception baud rates.
The baud rate generating section generates clock pulse signals which
are used in transmission and reception and delivered through the
baud rate selecting section to the SDTR secti on.
It provides the loop back diagnostic function which crosses interface
lines of the Modem and loops transmission and reception signals,
facilitating the operation check .
Features
● Two independent channels of SDTR.
● Built-i n baud rate generator which all ows setting for each channel
● External clock available
● Internal cloc k output avai labl e.
● Maskable interruption generating circuit
● Two channels are assigned to different address spaces.
● Baud rate DC ~ 240K baud (with external cloc ks )
● Full duplex comm unic at ion
● Program assignm ent in s ync hroniz at ion mode
• Data bi t length: 5 - 8 bits
• Character synchronization system: Internal synchronization,
external synchronization
• Number of synchronized characters: Single character, double
characters
• Pari ty occurrence and check: parity valid/invalid
even parity, odd parity
● Operations in the sy nchroniz at ion mode
• Overrun error and parity error detection
• Trans mi t/rec eiv e buff er st ate ac k nowledgm ent
• Synchronization character detection
• Aut omat ic ins ert ion of sy nc hroniz at ion c harac ter
● Program assignment function in the advancement synchronization
mode
• Data bit lengt h: 5 ~ 8 bits
• St op bit lengt h: 1, 1
1
⁄2, 2 bits
• Baud rate: Transmission clock, reception clock x 1, x 1/16, x
1/64
• Pari ty occurrence and check: Parity valid, inv alid
Even parity, odd parity
● Operations in the adv anc ement synchronization mode
• Detec ti on of framing error, overrun error, parit y error
• Transmission/reception buffer state acknowledgment
• Break c haracters detection
● Error start bit detection
● IBM Bi-sync system operation allowed.
● Duplex buffer system in the transmission and the reception sec-
tions.
● Loop back diagnost ic functions
● I/O signal level TT L compati ble
● Compatible with standard microprocessor in connecting pins and
signal timing.
● Standard 42 pin plastic DIP, 48 pin plastic QFP
● +5V single power source
2) Pin configuration
3) Block diagram
1DB4
2DB5
3DB6
4DB7
5TRNCLK1
6W
7CS1
8RSLCT0
9R
10RCVRDY1
11RSLCT1
12CS2
48NC47 GND
46 RCVDT1
45
DB344DB2
43 OPEN
42
DB1
41
DB040VCC
39 RCVCLK1
38NC37
DTR1
36 RTS1
35 DSR1
34 RST
33 CLOCK
32 TRNDT1
31 TRNEMP1/ST1-1
30 CTS1
29 SYNC/BRK1
28 TRNRDY1
27 RCVCLK2
26 DTR2
25 RTS2
13
RCVDT2
14NC
15
TRNCLK2
16
RCVRDY2
17
TRNRDY2
18SYNC/BRK2
19
OPEN
20
CTS2
21
TRNEMP2/ST1-2
22TRNDT2
23
DSR2
24
NC
DB0~DB7
CS1,CS2
RSLCT0,RSLCT1
W,R
TRNRDY1
RCVRDY1
SYNC,BRK1
TRNEMP1
RST
TRNRDY2
RCVRDY2
SYNC/BRK2
TRNEMP2
CLOCK
SDTR1
TRNDT1
RTS1
DTR1
RCVDT1
CTS1
DSR1
TRNCLK1
RCVCLK1
SDTR2
TRNDT2
RTS2
DTR2
RCVDT2
CTS2
DSR2
TRNCLK2
RCVCLK2
Address
decoder
Mode setting
register 1
Baud rate
setting
register 1
Baud rate
generator
Mode setting
register 2
Baud rate
setting
register 2
Interruption
mask 1
Loop
back
control
1
Loop
back
control
2
Interruption
mask 2
Clock
control
1
Clock
control
2
VCC
GND
4 25
Page 69
4) Pin description
No. Pin No. Pin name I/O ER-A5RS
Data bus
1 1 DB4 I/O DB4
2 2 DB5 I/O DB5
3 3 DB6 I/O DB6
4 4 DB7 I/O DB7
5 41 DB0 I/O DB0
6 42 DB1 I/O DB1
7 44 DB2 I/O DB2
8 45 DB3 I/O DB3
9 46 RCVDT1 I RCVDT1
RS-232 reception data signal
10 13 RCVDT2 I RCVDT2
11 47 GND – GND
12 5 TRNCLK1- I GND
Data transmission clock
13 15 TRNCLK2- I GND
14 6 W- I W- Write signal
15 7 CS1- I CS1-
RS-232 chip select
16 12 CS2- I CS217 8 RSLCT0 I AB0
Address bus
18 11 RSLCT1 I AB1
19 9 R- I R- Read signal
20 10 RCVRDY1 O RCVRDY1
RS-232 data reception enable signal
21 16 RCVRDY2 O RCVRDY2
22 28 TRNRDY1 O TRNRDY1
RS-232 data transmission enable signal
23 17 TRNRDY2 O TRNRDY2
24 29 BRK1 O BRK1
Break code detection signal
25 18 BRK2 O BRK2
26 30 CTS1- I (CTS1-)GND
RS-232 clear to send signal
27 20 CTS2- I (CTS2-)GND
28 31 TRNEMP1 O TRNEMP1
RS-232 transmission buffer empty signal
29 21 TRNEMP2 O TRNEMP2
30 14 NC – NC
31 24 NC – NC
32 38 NC – NC
33 48 NC – NC
34 19 OPEN NC
35 43 OPEN NC
36 32 TRNDT1 O TRNDT1
RS-232 transmission data signal
37 22 TRNDT2 O TRNDT2
38 35 DSR1- I DSR1-
RS-232 data set ready signal
39 23 DSR2- I DSR240 36 RTS1- O NC
Request to send signal
41 25 RTS2- O NC
42 37 DTR1- O DTR1-
RS-232 data terminal ready signal
43 26 DTR2- O DTR144 39 RCVCLK1- I GND
Data reception clock
45 27 RCVCLK2- I GND
46 33 CLOCK I CLOCK Clock signal
47 34 RST I RES RESET signal
48 40 VCC – +5V +5V
4 26
Page 70
4. Power supply circuit
The ER-A550 supplies +5V to +24V, and ±12V is generated from
+24V in the DC/DC convertor circuit.
Fig. 4-1
(1) The PX signal from the OPC1 alternately turns on and off the
comparator output of IC 8 (pin 7), which causes Q1 to turn on
and off. (Circuit
Α
)
Fig. 4-2
T1: Software starting: 26.04us
Normal operation: 13.02us
∗ After POFF cancel (Power ON), software start is made for
13.3ms.
Duty (Q1: ON/OFF) : Software strating: 12.5%
Noemalperation : 25%
(2) The potential at point
α
is 4.8V when the output voltage is
+12V(About +11V). A load fluctuation causes the +12V output to
change. At point
β
of the comparators (+) side, a triangular
waveform appears as shown in Fig. 4-2.
(3) The comparator (IC No. 8...Circuit
Β
), the potential at point α
is compared with that of point
β
. If the potential at point α is
lower than point
β
, Q1 activating time is prolonged to raise
the output voltage (by increasing the duty cycle). On the contrary, if the potential at point
α
is higher, the transistor activating time is hortened to decrease the output voltage (by decreasing the duty cycle). As Q1 duties cycles are varied by detecting
the +12V output fluctuation in the comparator (Circuit
Β
), the
output voltage is regulated at a constant level.
Fig. 4-3
Potential at point a changes according to a fluctuation in the
+12V output. Waveform at point a differs depending on the state
of +12V output.
(4) The pin 3 output of the IC9 chip at circuit
Χ
is at a high level
when the pin 1 input is at 5V. But, when it drops below 4.5V, the
line goes to the GND level. This causes Q1 to turn off so that
+12V and 12V are shut off. It is provided for prevention from
malfunction in the logic circuit when the +5V supply from malfunction in the logic circuit when the +5V supply from the ERA550 main frame drops.
∗ IC9: Not used
5. ER-A5RS channel setting
The ER-A5RS ports can be set to channel 1 - 7 and invalid (inhibit)
with SW1 on the PWB.
SW1 setting contents
SW1 1~3 are used for channel setting of RS-232 connector 1
(RSCN1).
SW1 4~6 are used for channel setting of RS-232 connector 2
(RSCN2).
+24V
+24V
+5V
+12V
-12V
T800mA
+
C49
100µ
50V
R22
4.3K
IC9
1
2
D2
+
+
C51
C52
RD33E B1
ZD2
R17
2.7KG
8
4
2
3
+
-
R14
10KG
C28
330P
R13
100KG
+
-
6
5
R16 R15
10K 10K
C
B
A
Q1
ZD1
RD27EB4
T1
H6752RC
+5V
3
D3
100µ35V x 2
R24
2.2K
1
R18
2.2KG
IC8
9393
7
IC8
9393
D1
E352
C50
10µ
16V
ZD3
RD5.1EL1
PX
c
a
b
+5V
GND
OFFON
+5V
GND
OFFONOFF
PX
Q1
ON,OFF
c
Point
3.255µs
T1
ONOFF ON ONOFF OFF OFF
+5V
GND
500mV
+4.8V
+1.4V
GND
GND
+1.4V
+4.8V
+5V
PX
Q1
ON, OFF
Point
a
b
c
Point
Point
a
Point
c
Point
+3V
*1
*2 *3
(a)
(0)
(1)
SW1
RSCN1
RSCN2
OPTCN1
SW1
RSCN1
setting
321
0 0 0 RS-232 invalid
0 0 1 Channel 1
0 1 0 Channel 2
0 1 1 Channel 3
1 0 0 Channel 4
1 0 1 Channel 5
1 1 0 Channel 6
1 1 1 Channel 7
SW1
RSCN2
setting
654
0 0 0 RS-232 invalid
0 0 1 Channel 1
0 1 0 Channel 2
0 1 1 Channel 3
1 0 0 Channel 4
1 0 1 Channel 5
1 1 0 Channel 6
1 1 1 Channel 7
Note
1) If RSCN1 port and RSCN2 port of the ER-A5RS are set to the
same channel, RSCN2 port becomes invalid and only RSCN1 is
valid.
2) If RSCN of the ER-A5IN and the ER-A5RS connector are set to
the same channel, the buses compete and the operation cannot
be assured. In addition, it may break the hardware. Never set the
two to the same channel. Be sure to set them to different channels
or to set invalid.
6
5
4
3
2
1O
F
F
1
0
654
CN2
321
CN1
4 27
Page 71
6. Circuit diagram
4
1
3
5
6
2
4
1
3
5
6
2
A
B
CD
E
FGHI
A
B
CD
E
FGHI
+5V
+24V
+5V
RCVDT2
737271706968676665
7475767778
RCVRDY2
TRNRDY2
BRK2
64636261605958575655545352
51
1
11
5
4
J
J4
IC4
75188
IC4
IC4
3
2
FL8
FL7
FL6
FL2
FL4
11 13
12
IC3
75189A
3
2
IC3
6
5
7
100K -4
DTR1
RTS1
TRNDT1
RCVDT1
DSR1 12
11
13
RA4
RA4
8
10
9
IC3
(C65)
C63
102
C61
102
CTS1
FL1
FL3
3
9
2
8
4
10
RA4
RA4
IC3
IC5
6
4
13
11
5
12
75189A
C64
102
C66
102
J3
DCD1
CI1
R12
R11
R10
C17
222
1.2K
100K
3.3K
FL5
ER1
RS1
SD1
RD1
DR1
CS1
CD1
CI1
13
8
12
J11
J12
IC7
75188
IC7
IC7
3
2
FL14
FL15
FL16
FL9
FL11
6 4
5
IC5
75189A
11
12
IC6
100K -4
DTR2
RTS2
TRNDT2
RCVDT2
DSR2 6
5
7
RA6
10
9
IC6
(C67)
C68
102
C62
102
CTS2
FL10
FL13
3
12
2
11
4
13
RA6
RA6
IC6
IC6
6
4
1
3
5
2
75189A
C69
102
C70
102
J9
DCD2
CI2
R21
R19
R20
C37
222
1.2K
100K
3.3K
FL12
ER2
RS2
SD2
RD2
DR2
CS2
CD2
CI2
11
13
9
10
8
10
8
9
RA6
FB
C
FB
+
-
+24V
T800mA
ZD1
RD27EB4
C49
100µ50V
Q1
T1
H6752RC
D2
D3
1
2
3
+5V
IC9
R24
2.2K
C51
C52
ZD2
100µ/35V x2
RD33EB1
R17
2.7KG
R18
2.2KG
814
2
3
IC8
9393
R14
10KG
+12V
-12V
+
-
R13
100KG
R15
10K
R16
C28
330P
10K
IC8
9393
7
6
5
ZD3
RD5.1EL1
D1
E352
R22
4.3K
C50
10µ/16V
J1
J8
CTS1
CTS2
1234567891011
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
3635343332313029282726
25
NC
NC
RES
RTS1
DSR1
RST
CLOCK
TRNDT1
TRNEMP1
CTS1
BRK1
TRNRDY1
RCVCLK2
DTR2
RTS2
DB4
DB5
DB6
DB7
TRNCLK1WCS1
RSLCT0RRCVRDY1
RSLCT1
CS2
RCVDT2
NC
TRNCLK2
RCVRDY2
TRNRDY2
DRK2
CTS2
TRNEMP2
TRNDT2
OPEN
DSR2
48
47
46
45
44
43
42
40
39
38
37
41
NC
GND
RCVDT1
DB3
DB2
OPEN
DB1
DB0
VCC
RCVCLK1
NC
DTR1
NC
NC
NC
+5V
IC
MB89371A
79
80
SLO0
SLO1
SLO2
SLI0
SLI1
SLI2
RCVDT1
RCVRDY1
TRNRDY1
BRK1
DB7
DB6
DB5
DB4
GND
DB2
DB1
DB0
TRNEMP1
TRNRDY0
RCVDT0
RCVRDY0
TRNEMP0
BRK0
XOUT
RES
DB3
5
6
879
432
1
NC
NC
NC
NC
1011121316151417181920
RES
OPTCSD0D1D2D3D4D5D6D7
GND
212223242625272829
30
RSRQA0A1A2A3A4A5
POFF
TRQ1
WR
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
NC
CS1
AB1
R
AB0
CS0
W
VCC
GND
RTS1
CI1
CD1
CTS1
CI0
RTS0
PX
44
45
46
47
48
49
50
+5V
+5V
100
99
98
97
96
95
94
93
92
91
90
89
87
86
85
84
83
82
81
88
GND
VCC
CD0
CTS0
NC
CTS1
DCD1
(C2)
(C7)
RES
OPTCSD0D1D2D3D4D5D6D7
RSRQA0A1
A5
POFFWRTRQ1
A4A3A2
(C19)
(C40)
(C39)
RD
RC
103-6
SW1
12345
6
C29
C30
C31
C32
C15
C14
C13
C12
331 x4
RA3
RA2
10K-6
10K-8
101 x4 101 x4
C11
C10C9C8
C33
C34
C46
C45
C44
C43
331 x6
TRNEMP2
TRNRDY1
RCVDT1
RCVRDY1
TRNEM P 1
BRK1
RA3
RA5
10K-4
R8
R9
10K
10K
RES
(C47)
C48
103
CS2
AB1
R
AB0
CS1
W
RTS2
CI2
DCD2
CTS2
CI1
RTS1
R7
R6
R5
R4
R2
R3
10K x6
C27
C26
C25
C23
C22
C21
101 x6
IC1
F256004PJ
R1
1M
X1
9.83MHz
AB0
AB1
NC
+
+
+
ER-A5RS
Page 72
C
D
B
A
1
2
3
4
6
C
D
B
A
5
1
2
3
4
6
5
No. No.SIGNAL SIGNAL
1 36 GNDGND
2 37 GNDGND
3 38 GNDGND
439
(φ)
RDO
5 40 NU1WRO
6 41 +5VBREQ
7 42 +5VBACK
8 43 TRQ2A23
9 44 TRQ1A22
10 45 EXINT1A21
11 46 EXINT0A20
12 47 TRRQA19
13 48 RSRQA18
14 49 RFSHA17
15 50 IPLONA16
16 51 D7A15
17 52 D6A14
18 53 D5A13
19 54 D4A12
20 55 D3A11
21 56 D2A10
22 57 D1A9
23 58 D0A8
24 59 POFFA7
25 60 VRAMA6
26 61 A3A5
27 62 (+12V)A4
28 63 +24V+24V
29 64 +24V+24V
30 65 A2A1
31 66 RESA0
32 67 ASRESET
33 68 NU2OPTCS
34 69 GNDGNDP
35 70 GNDGNDP
No. No.SIGNAL SIGNAL
1
36
GNDGND
2
37
GNDGND
3
38
4
39
(φ)
RDO
5
40
NU1
WRO
6
41
+5V
BREQ
7
42
+5V BACK
8
43
TRQ2A23
9
44
TRQ1
A22
10
45
EXINT1
A21
11
46
EXINT0
A20
12
47
TRRQ
A19
13
48
RSRQ
A18
14
49
RFSHA17
15
50
IPLON
A16
16
51
D7
A15
17
52
D6
A14
18
53
D5
A13
19
54
D4
A12
20
55
D3
A11
21
56
D2
A10
22
57
D1
A9
23
58
D0
A8
24
59
POFF
A7
25
60
VRAM
A6
26
61
A3
A5
27
62
(+12V)
A4
28
63
+24V+24V
29
64
+24V
+24V
30
65
A2
A1
31
66
RES
A0
32
67
AS
RESET
33
68
NU2OPTCS
34
GND
GNDP
GND
GNDP
35
No. SIGNAL
1
2
3
4
5
6
7
8
9
CD1
RD1
SD1
ER1
GND
DR1
RS1
CS1
CI1
RSCN1
OPTCN2OPTCN1
ER-A5RS
No. SIGNAL
1
2
3
4
5
6
7
8
9
CD2
RD2
SD2
ER2
GND
DR2
RS2
CS2
CI2
RSCN2
4 29
Page 73
7. PWB layout
4 30
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