Sharp PC-1211, CE-121 Service Manual

SHARP CORPORATION

CONTENTS

1. Specifications . .

. . . . . . . .

. . . . . . .

. . . . . .

. . . .

. . . . . . . . . . . . . . . . . . 2

2. Block diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. .

. . .

. .

4

3. LSI signal description

12

4

.

About servicing

17

5. Cassette operation

. . . . . . . . . . . . . . . .

. . .

. . . . . . . . . . . . . . . . . . . . . . .

18

6. Check program

·

· · ·

25

7. Circuit diagram

. . . . . . .

. .

. . . . . . . .

. .

. . .

. . . . . . . . . . . . . . . . . . . . . .

26

8. PC-1211 parts list & guide

· ·

32

9. CE-

121 parts list & guide . . . .

. . . . . . . . . . .

. .

. . . . .

· · · · . ·

· · ·

· ·

· · ·

34

MODEL

PC-1211, CE-121

----SHARP----

SERVICE

MANUAL

2

Add

(+),Subtract(-), Multiply

(+),Divide(/), Power raising (A

)

Trigonometric

functions

:

SIN (sine), COS (cosine), TAN (tangent)

Inverse trigonometric functions: ASN (sine " ), ACS

(cosine

-

1

),

ATN (tangent

-

1

)

Logarithmic functions: LOG (common logarithm), LN (natural

logarit

hm

[ln]

)

·

Exponential functions: EXP (exponential)

Angular transformations: DMS (decimal notation to sexagesimal notation),

DEG (sexagesimal notation to decimal n

otation

)

Square root extraction:

r

Signum

function

.

SGN

Absolute

value

:

ABS

(IX

I)

In terization: INT Execution of arithmetic operation

is

commanded by the ENTER key

.

1-3. Arithmetic functions

•

Buffers

:

•

Capacities

:

12

digits of mantissa and 2 digits of exponent. According to mathematical formula (with priority consideration and judge function) Program memory; 1424

steps, max (PC1211)

Data memory; Fixed memory

26 memories Flexible memory (commonly usable with the program memory)

178 memories, max (PC 1211) Reserve program; 18 kinds, 48 steps, max Input buffer; 80 steps Data buffer;

8

stages

Functional buffer;

16

stages (but

15

stages for

parenthesis

) Subroutine buffer; 4 stages "FOR NEXT" stagement

buffer: 4 stages

•

Computational capacity:

•

Computational method:

1-2. Basic

functions

•

Displaytube: LF8017JE

•

Display method: 5 x 7 dot matrix liquid crystal

•

Display capacity: 24 coulumns (alphanumerics and symbols)

1-1 . Display

INS

OJ

ITJ []]

El G

DEL

w w

rn

w

@g

G] [[] []]

W

[

MODE

\

CA/BREA

K

1(

A

<

>

~~

PO

WER

IT]

[TI

0

OJ OJ

[SHFTj

!

"

#

s

%

¥

?

•

;

~

0 0

IT]

[!]

~

[I]

~ 0

0

[}]

0

0 0

0

IT]

[TI~

IT]

0

[I]

0

0 ~

~

ERi

RESERVABLE

KEY

S

1. SPECIFICATIONS

3

Data

protection

:

Program memory, data

memory, reserve program memory

P

eripheral unit: Audio cassette unit

(recording/reading of the program memory,

d

ata

memory and reserve program memory)

Physical dimensions: 175(W)

x 70(D) x 44(H) mm

1-7. Others

Four MR44 (mercury batteries) 300 hours

0.01

iw

About 6 minutes

B

attery:

B

attery life:

Power con

sumption:

Automatic power shut off:

1

-6. Power source

1-5. Programming language

BAS

IC (Beginne

r's All purpose Symbolic Instruction Code)

....

(right), ~(left) INS D

EL

+(down), t (up)

Cursor shift:

Insertion

.

Deletion

:

Line control:

1-4. Editorial

functions

4

-

0..

0

0.

~

cc

I

t

cc

_

Cfl

-e-

...

I

u

...::...

I

~

...

cc

"'

~

;!:

"-

(/)

l

>::

(/) (/) (/)

~

u;

~

L<(

-x:J-i

·-

"'

00

lH-lH

"'

t--

::J

.....

Bd"id

""

0..

....

-

ds!

a

u

~

-

ir:

~

.0

-

"'

~

...

::a

en

G:

eo

co

~

0

B;

"-

::il

x

-

"'

8

0.

-

<-

cc

-c

~

rn

''

Z<

;:;,

"'

(/)

:i:

11;[

i

CJ

>

>>

>

I

"-

"'

.0

:i:

:;;

-'-

~

r-

00

0

A.. f

:;;:

'.,

-c:

:;:

~

--

,___

"'

~

I

,_

,___

~

I+-

,__

-

0..

~

a

i.........:..::

-

V

H

"'

q

,\\/N

~·l•lt--

x

...

~

8V-!V

0

"'

-

cc

"'

0

u

x

-

I

"'

-

0

...

0

...

II

(/)

-

.l

I

u

0

-

(/)

~

(/)

~

::il

tOia-

!OJG

rn

/I--

c,

<

~

' l

¥---

·-

6

.0

rn

-

°'

er:

s-,

G:

'7

rn

.o

~

rn

"'rn

-

rn

c.

~

~ ~U":l

~

qs

00

v;

;;;

~

Cl

rn

""

CJ

'--

"'

-

c

I+---

>O-

<llO..

"-

(/)

u

t--

~

i+--

:>Cl

ID

c

!.---

><

-

.....

~

-

>

L'lCJ

""

..__

::J

....

'-

L'lZO

0..

u

Ul

~

I+--

;::::=:¢

-s-

sc

>::

·

-

I

:'.:

>::

-

en

>::

I

z

»

"'

cc

0

>::

in

;..

¢=

~

>::

o

:E

<(

a:

CJ

<(

c

~

0

...J

m

en

(/)

CJ

z

0

"'

0

~~

u

"'

.l

<

.l

z

<

CJ

z

CJ

.l

<

z

CJ

(/)

5

•

The CPU I functions to read key-in data or read the instruction to be executed from the

RAM

,

and decides what

is

to be done for the control of arithmetical operation (i.e. control of

arithmetic sequence, memorizing of arithmetical

data, and its readout), or interprete the syntax

of the BASIC instruction for deciding what

is

to be executed, or determines and prepares the

information to be displayed, but the CPU I does not perform any execution by

itself

.

It

only arranges the data and information in proper sequence and acts to provide instruction code to the CPU II via the buffer. On the other

hand, the CPU II constantly receives execution instructions from the CPU I via the transfer buffer and executes operation against each of instructions or sometimes performs to exchange data depending on the

situation. Although it shares major part of execution in term of execution, it performs some kinds of auxiliary CPU when looked in the view that it does not perform any decision by

itself

.

Clock stop

Clock stop control

I

Power shut off control

I

Power off

Display processing routine

Input buffer Computational result Error

Arithmetic routine

Character generator

Cassette routine Print routine Buzzer

Recognition of printer

Key input routine Acknowledgement of the remaining

program One instruction to one program step

incorporation Interpreter:

Program execute statement

Cassette control statement Command statement

Printer control

Execution of manual operation

CPU

II

CPUI

These CPUs are provided with internal ROM, and each of CPUs shares the following assignments:

2-1. CPU I,

CPU II

System

configuration

(see

the

system

block

diagram)

System of this unit consists of the following components:

1)

CPU I (SC43157) x 1

2) CPU II (SC43178) x 1

3) 4K-bit RAM (TC5514P x 3)

4) Display chip (SC43125 x 3, with built-in RAM)

5) 2AND gate (TC401 l UBP x 1)

6) 2AND

20R

(TC4019BP x 1)

7) Inverter (TC4069BP x 1)

8) Quard Analog Switch Multiplexer (TC4066BP)

9) LCD (24-digit FEM dot LCD)

10) Key

11) Crystal (CSB2560)

8

6

In the case of manual operation of the pocket computer, the instruction code (key code)

is

written

into the RAM in the display chip (input buffer) after information

is

put through the keyboard and

converted into the instruction code by the CPU

I,

then this instruction code (display, at this case)

is

transfered to the CPU II

via

the transfer buffer.

As

the CPU II receives this instruction, the CPU

II

then decodes this instruction

(display, at this case) and executes display processing. Upon the

completion of this processing,

it

is

then notified to the CPU I, then the CPU I confirms the comple-

tion of the task by the CPU II before terminating their jobs.

CPU

Il

Ex: Actions of CPU I and CPU II at the time of key data entry.

7

Although RAM area is mainly shared by the

program, data

and reserve program

memories, it

is

also used for the sub-

routine stack, FOR NEXT statement stack and fixed

memories (W, X, Y, Z).

1536

1472 1504

001

048

(PC1211)

Reserve pro

gram

------- - - - - - --

Program

or

flexible

memory

~------

-------

Fixed memories (W - Z)

Subroutine I FOR

stack

A certain number

of

C-MOS RAM

(1

-

3

chips, 4K bits each) and another RAM incorporated inside

the display chip are used in this pocket computer, having varieties of configurations

as

described

below:

•

Map

of

4K-bit RAM

153

6 Bytes

2-2.

RAM

II

8

•

Input buffer Remaining 80 bytes (10 memories equivalent) of the display chip 1 is

used for the input

buffer

,

which

is

used in the following

functions:

1.

Any information entered through the keyboard

is

stored once in this

buffer, thus allowing up

to 80 steps.

2. The display contents

is

stored by the CPU I and the CPU II makes selection out of this dat

a.

3. When an

arithmetical instruction is

entered, its procedure

is

stored in this buffer by the CPU

I

and the CPU

II

performs operation according to this procedure.

4. When program or reserve program

is to

be recorded or read out during the execution of the

cassette control

instruction, action takes place through this input buffer.

•

Transfer buffer 8

bytes

(1

memory

equivalent) of the

display chip 1 is used

as a transfer buffer which

is

used in

the

transaction of instruction between the CPU I and the CPU II.

16 bi

ts

----1}4bit

1

memory

•

Fixed memory The total memory of 176 bytes from the display chip 2 and 3 is

used

as a

fixed

memories, A-V

(22 memories).

•

8-digit display buffer

40 bytes of 8-digit display buffer

is

used

as a

display data buffer during displaying and also used

as a buffer memory for arithmetical result during the arithmetical operation.

128

80 step input buffer

Fixed memories (L-V, 11

memories)

Fixed memories (A-K, 11

memories)

Transfer buffer

040 04

8

8-digit display buffer

000

DISPLAY CHIP

3

DISPLAY CHIP

2

DISPLAY CHIP

1

•

Map of the RAM incorporated in the display chip There are three lK-bit RAMs (128 bytes each) incorporated in each of display chips (SC43125), having the following

configurations

:

9

Fig 2-3-1

The

numeri

ca

figure "4

", to be displayed by the CPU II,

is converted into the relevant character

code and carried through on the address data bus. First of

all

,

the segment Sl

is

selected with the

address

A8-Al "

00000000" to store the data DI04-DI01

"1000

"

in

t

he display buffer

(see Fig

.

2-3-1

). To store second half 4 bits of the

data, only

AS

in the address in turned "1

" to make the

address "00010000" to store data "0001 ". In the same

manner, the address "00000001"

is

selected

for storing the first half 4-

bit data

"O

100" for he segment S2 and the sec

ond half 4-bit data "000 I"

is

stored with the address "00010001 ".

S40

S32 S3

3

S34

Sl6

Sl7

Sl

8

1

S2

A5=0

A5=1

DI04 DI02 DI04 DI02

'--------..,..-~

Address

0

1

0

0 0

)

F

0

1

0 0

1

)

F

0

1

0

1

0

~

F

Al

I

A8

A7

A6 A4

Hl

DDD•D

H2

oo••

o

H3

o•o•

o

H4

•oo•o

H

5

•••••

H6

ooo•o

H7

ooo•o

Sl

S2 S3

S4 S5

Ex: Displaying numerical figure

"4"

There are 8 x

40=320 bits ( 40 bytes) of area in the display buffer in the display chip.

Disp

lay bu

ffer

XOOl 0100

H8 H7 H6 H5 H4 H3 H2

Hl

X

OOl 1000

Co

unter/

decoder

HA

T

he contents of disp

lay

indicated by the CPU

I is

received

by the CPU II

via the input buffer and

m

akes converted into

respecti

ve

character codes,

then they are carried over to the display buffer in

t

he disp

lay

chi

p through the address data

bus

.

• Designatio

n of the display data

The following structure is

observed in the display buffer in the display

chip

.

2-3. Display

the

ata.

'U

I

up

er

,

10

HA: Clock frequency for the counter. This signal

is

counted and decoded to perform sy

nchroni

-

zation with the comman

signal, Hl-H7, generated from the CPU II.

DSIP: With high level of this

signal, processing of display operation

is

indicated (RAM data

designated by

Hl-H8

is

sent out on SI

-S40).

The data stored in the display buffer

is

carried through

SI-S40

(Fig. 2-3-2) to be fed to

the LCD.

(To

indicate "4

" on the

display, H4 and HS are

engag

ed for SI,

H3 and HS

for S2,

etc.,

all the same

throughout

S6-S40.)

F

ig 2-3-

2

S

2

Sl

H7

H6

LJl....____flJ

L

I

H

5

LJ

H

4

H3

H

2

Hl

-----------

--------

-

--

GND

--

---

VA

--------.

-----------Vs

--------

Vn1SP

HA

DI SP

0.5ms

~

- -----

-3.9V

VDISP

VB

------

-2.lV

- - - --- -3.

9V

L_

VM

-------IV

...._

__ - - - --- -

2.8

V

6.8ms--

--

VA

-- ---

ov

...._

__ - - - --- -I.8V

11

E

ye positi

on

30

°

o

Adjustments of reference voltage VD ISP The VDISP had been precisely adjusted to become -3.74V at an ambient temperature of 20°C and -4.29V at 0°C.

In case there

is

a

n

eed of

readjusting the voltage after servicing the LCD or exchanging

some of power source

components, be sure to look on the LCD from

30° of angle from the ve

rtical line while adjusting the pot.

:D.

Low side voltage of common signals

(Hl-H7)

for

LCD

. High side voltage for segment signals (Sl - S40) Intermediate voltage of the common and

segment signals

Low side voltage of segment signals.

VA

,

VM and VB become pulses in an amplitude of several volts owing to influence

caused from the LSI.

VA: VM:

VB

:

NOTE

:

ata

o The

liquid

crystal

reference voltage

VDISP

is

generated in the above

circuitry in order to

avoi

d

occurrence of such unpleasant phenomena

as

blurred character or contrast

variation that might

degrade display

performance, which

is

caused by a slight voltage variation in the liquid crystal

reference voltage VD ISP, since the

5 x 7

dot matrix liquid crystal

is

used in the disp

lay of this

pocket

computer.

A) VDD is

generated in the CPU

II

on the basis of VGG.

B) The gate vol

tage of MOS FET is

controlled by the 250KS1 pot to regurate the voltage for VDISP.

Furthermore, the voltage of VDISP

is

changed by the thermistor to meet with temperature

varia

-

tion,

so as to maintain proper display

performance

.

C) Line between the reference voltage VD ISP and GND

is divided by resistor to make ou

t VA, VM

and VB

.

V

DISP

:

20°

o

C PUil

Yoo

Relation between

ternperture

and VDISP

M

OS FET

ioo»

2-4. Power source

12

Pin No.

Signal name In/Out

Description

1

F4a Out

Chip Enable signal (RAM3 select signal)

2

F3a Out

Chip Enable signal (RAM2 select signal)

3

F2a Out

Chip Enable signal (RAM 1 select signal)

4

Fla

Out

Chip Enable signal (Display chip 1 select signal, for input buffer and transfer buffer usage) During

display: Low

/

- - - -

-

- -

During read-in: turns momentarily high

6

VGG

In

Source

voltage("-"

voltage of battery)

7

VGG

In

8

Xin

In

Basic clock (pulse signal in 256KHz)

9

TESTl

Connected with GND

10

TEST2

11

RESET In All reset switch input

Normally high but turns low when the all reset switch

is

depressed.

12

R/Wa

Out

RAM Data Read/Write signal During display: High

________

Depression of the key causes it momentary

low!

13

DIO

l

In/Out

Data Bus (for address designation of the input buffer and

14

DI02

In/Out

transfer buffer in RAM and display chip 1 ).

15

DI03

In/Out

During display: High

\_

16

DI03

In/Out

During

read-in: Low

17

B8a

Out

Address Bus (for address designation

of

the input buffer and

18

B7a

Out transfer buffer in RAM and display chip 1 )

.

19

B6a

Out

20

BS

a

Out

During

display

:

___

Mementary generation

21

B

4a Out

22

B3a

Out During read-in

:

lllllllllll

l

llllllllllll

l

23

B2a Out

24

Bla

Out

30

GND

In

Source voltage

(OV)

40 S16a

Out

Busy signal to the CPU II (High during the execution in the CPU

I)

During display: Low During read-in: turns momentarily high

3. LSI SIGNAL DESCRIPTIONS

3-1. SC43157 (CPU

I)

13

No

.

Signal name

In

/Out

Description

1

F4

Out

Buzzer signal When the buzzer

is

off: Low

----i

0. 2 5msl--

When the buzzer

is on:

LS1___J

2

F3

Out

Chip Enable signal (Display chip 3 select signal)

3

F2

Out

Chip Enable signal (Display chip 2 select signal)

4

Fl

Out

Chip Enable signal (Display chip 1 select signal)

During display: Low

----- ____

__

During read-in: Turns mementarily high

5

VDD

Out

For liquid crystal drive voltage preparation (VDD :; V GG)

6

VGG

In

Source

voltage("-"

voltage of the battery)

7

VGG

In

-

8

Xin

In

Basic clock (Pulse signal in 256KHz)

11

RESET

In

All reset switch input

3-2.

SC43178 (CPU

II)

Pin No.

Signal name

In/Out

Description

-

41

Sn Out

Key Strobe

signal, RAM Address signal

42

Si

Out

Key Strobe signal, RAM Address signal

43

Sl3 Out

Key Strobe signal

44

Sl2

Out

45

Sll

Out

During display: High

46 SlO

Out

Depression of the key causes it momentary low

47 S9

Out

48

S8 Out

49 S7 Out

50

S6 Out

51

SS

Out

52

S4 Out

53

S3

Out

54 S2

Out

55

Kil

In

Key input signal

56

Ki2 In

57

Ki3

In

During display: Low

58

Ki4

In

Depression of the key causes it momentary high

59

S16b

In

Busy signal of the CPU II (high during the execution

of

the

(Ki5)

CPU II)

I

During

display: Low

Depression

of

the key causes it momentary

high'.

n

14

Pin No.

Signal name

In

/Out

Description

1

2

R/V

I

Out

RAM Data Read/Write signal During display: High During read-in: Turns momentarily

low-- - - -

- -

-

13

DI04 In/Out

Data Bus (for data transaction between RAM and display chip)

14 DI03

In/Out

During display: High

lS DI02 In/Out

During read-in: Turns

low--l[lllll

16

DIOl

In/Out

17

B8b

Out

Address Bus (for address designation of the display chip)

18

B7b

Out

During display: Bl

b=high, B2B=low, B3b=low,

B4b=low

,

19

B6b Out

BSb=high,

B6b=high,

B7b=low, B8b=low

20

BSb Out

During

read-in: Turns momentarily high

21

B4b

Out

.

______

/

22

B3b Out

23

B2b

Out

24 Blb

Out

2

S

HA Out

Display signal (Common signal counting

pulse

)

.ruu

Being generated during

displaying

--10.Smst--

26

DISP Out

Display command signal During display: High During

execution: Low

27

VM

In

LCD display voltage (Intermediate voltage of the segment signal)

28

VA

In

LCD display voltage (High side voltage

of

the segment signal)

29

GND

In

Supply voltage (OV)

30

H4 Out

LCD common signals (backplate)

31

H7

Out

32

H3 Out

33

H6 Out 34 H2 Out 3S

HS

Out

36

Hl

Out

37

VDISP

In

LCD display voltage (Low side voltage

of

the common

signal

)

38

VB

In

LCD display voltage (Lo

w side voltage of the segment

signal

)

39

Sl6

Out

Busy signal to the CPU I (

High during the ex

ecution in the CPU II) During display: Low

/

Depression of key causes it momentarily high.

40 SIS Out

Record signal to the cassette tape and print

data

.

4

1

Sl4

Out

Remote signal to the MT.

15

Pin No.

Signal name

In/Out

Description

42

Sl3

Out

Busy signal to the printer.

43

Sl2

Out

Expansion signal

-~

During

display: Low Depression of the CA (ON) key causes an instant pulse generation

.

49

S6

Out

For DEF symbol display (engaged: low, not engaged: high)

54 Sl

Out

For symbol display

(SHIFT, DGE, RAD,

GRAD, RESERVE, PRO, RUN) Same waveform as the segment signal.

55

Kil

In

CPU I Busy signal (High during the execution in CPU

I)

(Sl6a)

56

K.i2

In

Expansion signal

To be connected to Sl 2 (CPU II) for

PC-1211

.

57

K.i3

In

Printer Busy signal Low when the priner is

not

operated

.

58

K.i4

In

Printer connection identifying signal. Low when the printer

is

not

connected

.

5

9

l~5

In

Casse

tte reproduct sign

al.

60

K.i6

In

ON key input signal

1)

)

16

TC4019BP TC4066BP

(Quad

AND-OR

select gate)

(

Quad bilateral switch

)

1

4

13

1

5

CIN

IN/ouT

OUf/IN

1

3

1

2

1

5

2

CIN

12

4

IN/ouT our /IN

3

4

6

11

5

CIN

8

IN/ouT

OUT/IN

9

6

10

12

7

CJN

11

IN/our

OUT/IN

10

9

7

GND

5

4

2

6

3

2

5

4

3

7

GND

6

8

Vnn

14 13 1

2

11 10

9

Vno 14

13 12

11 10 9

TC4069

P

(

HEX in

verter

TC4

011UBP

(

Quad 2

- input positive

NAND gate

)

3-3

IC

17

Fig 4 -

2

Screw(c)

Screw(e

l

Under

850µA

Under 12µA

•

Measuring current c

onsumption

Power source voltage. 4.72

V

Current

consumption

: After depress the ON key: After depress the OFF key

:

Fig 4-

1

Lac

h

•

Disassembl

y proc

edure

1

) Remove the 2 screws (a) and

2 sc

rews (b ).

2) Separate the

upper

cabine

t from the lower cabinet from the screw

side, as the

y are

latched

togethe

r at three

points, A, B,

and C.

•

Repair

ing procedu

re

1)

As

the back o

f the

arithmeti

c printed board comes into sight after the removal of the lower cabinet, the arithmetic printed board can be checked from the back

side

.

2) Replacement of

the CPU II is

possible

.

3)

If

the key

printed bo

ard is

to be

checked, the arithmetic printed boa

rd has to be bent in right

angle

after removi

ng the screws ( d) and ( e ). Inspection of the CPU I

is

possible

if

the bu

zzer is

removed af

ter re

moving

the screw

(c)

.

4) The key printed b

oar

d can be dismounted from the upper cabinet when the 9 screws

(f)

and

2 screws (g) are

removed. But, c

are must be exercised in dismounting the prin

ted

board, as

key tops may come fa

lling down one after

another

.

•

Replacement

of the

LSI

1)

It

will be much convenient if the LSI use soldering pencil

(UKOG

-0078CSZZ) is use

d for

replacing the LSI.

2)

Be

sure to remove t

he key printed board from the upper cabinet

first, if the LSI on the key

printed board

is

to be removed.

If

the LSI was removed with the key printed

boar

d being

fitted on the

upper cabinet,

there is a

possibilit

y of deforming the key rubber by the

heat of

the

soldering pencil.

3) Be

sure to cut the legs of IC,

if IC was removed.

~--S

crew (b)

4.

ABOUT SERVICING

5

18

1

bit

4KHz

DATA" i

"

2

KHz

DATA"O"

1 = Check sun code (after every 8 steps or one data

memory.)

2 = 8

steps of program or reserve program 3 = End code of recording. 4 = This gap, composed of all

"l ",

is

inserted at each step the recording exceeds 80

steps, during

which teime the next 80 steps of data to be input

is

prepared in the input

buffer

.

5 = All

"l"

is

recorded for a period of about 6 seconds in order to avoid non-recordable area

located at the top of the tape and

is

also used for the cueing of the recording head.

6 = With this program or reserve program name

is

indicated. 7 = File name 8 = Data memory

is

indicated with this

code

.

9 = Area for one data memory.

Recording method

Data "O" and

"l"

are identified by changing the frequency of the recording signal

(F4")

.

Data memory recording format

Recording

format of

program or reserve program

Contents

of

program

or

reserve program

80 steps

4

1+1

5-1. Recording

Recording

metho

d

5. CASSETTE OPERATION

19

KI

5

Amplifier circuit

Schmitt circuit

CPU

11

Output signal from the EAR PHONE jack of the tape recorder

is

amplified and shaped in the

Schmitt

circuit, to be input to the CPU II through the

KiS

terminal of the CPU II.

5-2.

Reproduction

When recording signal "1"

is to

be

rec

orded, Sl 5 is

turned l

ow level and the

sign

al

F4

(clock

pulse of'..;'.

4KHz)

is

output during that

period. When recording signal "O" is to be recorded, SI

5

is

turned high level and the F4 output

is

inhibited during that

period, at

which

duration the

reverse si

gnal of HA (clock pulse of:::

2KHz)

is carried on the recording si

gnal.

Then, this signal

is

supplied to the MIC terminal of the tape rec

order via the modulation circuit

of the

CE121.

Signal waveform at the

time of recording

Rec

ording signal

(F 4

11

)

F4

HA

s

15

., ~

F<"---+ To CE121 cassette

rnodulation circui

t

Sl5 ~

Recording signal

(F4")

generation

circuit

rea

TI

20

Deactivation of

the· relay

(cassette

to

stop running)

Lr

\

QA-u

\

Activation of

the

relay

(cassette to

start

running)

~Startup

of the cassette operation

~

Termination of the cassette operation

Sl4----i--~~~~~~~~~__.r--

The TC 4528P

is a mono-stable multivibrator which can perform trigger operation and reset operation and two circuits are contained in the same chip. "

A" outputs a pulse which

is

dependable on the time constant of CR at the falling edge of the input

signal, and "B" outputs a pulse which

is

dependable on the time constant of CR at the rising edge of

the input signal. The relay operates

ON

and OFF according to the current flow to the

coil, and it

is

activated when "A"

is

active and deactivated when "B"

is

active.

NR-5711

-----..,

5

ru_

I

L------~

0.0

4.:7

PF

4

70Kn

100

2

Kn

4

Ain

Q

6

2

SA733

MT

A

REMOTO

5

Bin

QA

7

74'

W

(Sl4

)

TC4528BP

33

n

3

0.047

µF

VGG

100

8

1

4

Kn

8

in

QB

10

2

SA7

33

83

B

GND

11

Bin

QB

9

1

4w

TC4528BP

3

30

13

The CEl

21

will control the REMOTE terminal in automatic manner against the record, playback

and check commands.

5-3. Remote control

21

No.

Read in

Display

Remark

s

1

l

oFF

I

2

Connect the CE121

with th

e

tape recorder.

3

Connect the PC 12

11 with the

CE121.

4

l

oNI

>

R

UN

Make sure t

hat the symb

ol

RUN

is on the display

.

Otherwise, let the symbo

l

Rillf :Jo8iEJlayed us

ing

t

he key

.

2. Checking CE121

Assumes that the st

ep 1 has alre

ady been

executed

The test data have to be written into PC-1211 in the above

manne

r.

No.

Read in

Display Remarks

1

lMODEI -

lMODE)

>

RESERVE

Make the RESERVE symbol indicated on the display

afte

r

d1f

essinf the

I

E

TER

key

.

2

NEW

_

RESERVE

3

IENTERI

>

RESERVE

4

l

SHFTI

z

Z:_

RESERV

E

5 P.#

lSHFTl

f Af

lSHF'rj; A(

204

) Z: P.#

YA'; A(204

)

RESERVE

6

!

ENTER!

Z: PRINT #fAf; A(204)RESERV

E

7 lsHFTI X

X:_

RESERVE

8

1.# !

SHFTlfAY lSHFTl; A(7

6)

X: I. #YAT; A(2

04)

_

RESERV

E

9

!

ENTER!

X: INPUT #JAY; A(204)RESERVE

10

I

SHFTI

ISP.CI

.

-

RESERV

E

11

A(76)

:

A(204

)

RESERVE

12

I

ENTERI

:

A(204

)

13

I

MODEI

>

DEF

14

!

MODEi

>

RUN

15

I

SHFTI

ISPC I =

100

A(204)=100

_

RUN

16

!ENTER!

RUN 100

5-4. Testing the CE121

1. Writing test

data t

o PC-1211

First of all, test data must be entered to PC1211 for checking CE121.

22

NOTE:

•

When next CE121 check is

to

be

performed in executing secondary

test, be sure to enter

"A(204)=100"

.

•

Repeat once again from the

"l.

Writing test data to PCl 211 ",

if the contents of PCl 211

happens to change.

I.

It

requires inspection if one of following conditions is

recognized

.

1.

When the cassette starts

to

run at Step 6.

2. When the cassette fails to run or no sound is heard at Step 8.

3. When the cassette does not stop at Step 9.

4. When reproducing sound

is

not heard at Step 13.

II.

Repeat the procedure in the following case.

1.

When "5 "

is

displayed at Step 13,

repeat operation from Step 10.

If

the same indica-

tion is still on the display, repeat the procedure from Step 5 after entering "A(204)=100".

If

the same indication is

to

remain on the display even after

this, it requires detailed inspection.

2. When

"100." is

not displayed at Step 16,

repeat operation from Step 10.

If

the specific

indication does not appear on the display, repeat the procedure fro

m Step 5 after entering

"A(204)=100".

If

the specific indication

is

not to appear on the display even after

this, it

r

equires detailed

inspection

.

No

.

Read in

Display

Remarks

5

>

RUN

Make sureof the tape recording location.

6

>

RUN

Depress the [REC] and

[PLAY] buttons. Then, the

cassette will come to

halt

.

7

lsHFTI Z

PRINT

#TA';

A(204)_RUN

8

!ENTER!

RUN

The cassette starts

to

run

generating

sound

.

9

>

RUN

The cassette comes to stop quitting sound

generation

.

10

>

RUN

Depress the (PLAY) button. But, the fassette is

still at halt.

11

>

RUN

Return the cassette tape until the beginning of th" recording

.

12

lsHFTI X

INPUT

#'A';

A(204)_RUN

13

IENTERI

R

UN

The cassette

starts to run

generating reproducing

sound

.

14

>

R

UN

The cassette comes to stop

quitting sound generation.

15

lsHFTI lsPcl

A(204)

_

R

UN

16

IENTERJ

RUN

100

.

17

RUN

100

.

Push the [STOP]

button

.

18

lOFFI

19

Disconnect PCl 211 from CE121.

2

0

Disconnect CE121 from the

cassette recorder

unit

.

23

Plug

Tape recorder

No.

Read in Display

EAR

REM

Remarks

PHOE

MIC

OTE

PLAY

REC

STOP

1 ( loFFI)

Connect PC 1211 with CE121.

2

[QH]

.

>

RUN

0 0

Determine the location of the tape to be

recorded

.

3

>

RUN

0

0 0 0

0

Make sure

that

the

cassette tape does

not

run.

4

cs. jsHIFTl'A

CS. ,A_

RUN

0

0 0

0

5

!ENTER!

RUN

0 0

0

The cassette tape starts to run and the recording sound is

heard

.

6

>

RUN

0

0 0

0

The sound

is

inter-

rupted

and the cassette tape comes to halt

with">" indicated on the display.

7

>

RUN

0 0

Return the tape to the beginning of the recording.

8

>

RUN

0

9

CLO.? lsHFTI'A

CLO.?Y A_

RUN

0

0 0

0

10

jENTERj

RUN

0

The display con-

tents comes to dis-

appear from the

display and the

cassette tape starts

to run generating

the reproducing

sound.

11

>

RUN

0

0 0

0

Sound generation is

interrupted

and the cassette tape comes to halt with

">" indicated on

the display.

12

RUN

13

IOFFI

The CE 121 is in proper operation

if

the following procedures are ended successfully.

0

1

PAUSE

P R I N T

#

'f D 'f

O:GOTO 10

A(201)

5-5. About repairing of CE121

Program

24

Cassette operation ON/

OFF control must be properly executed when the above signals are observed

during the execution of program.

Deactivation of

the relay

(cassette tape

to

stop

)

n

.........

_

___.n

.......

__

#

10 pin

of TC4528

and

--Jl+---

#3 terminal

of

the relay

~ L

1

msec, mi

n

-----,

n n

rt_

#

6 pin

of TC4528

and

~

1msec, mi

n

#

5 terminal

of

the relay

_J

L__

--~,

Activation of

the relay

(cassette tape

to

start

running)

#

5 and 12 pins

of

TC4528BP

(or

equivalent)

•In display~

.

.,,4 .,14

In

.

~4

·

..j4

In

~-

-

-.j+

~~cording

recording In

display

recording In display

L

No

.

Read in

Display

Remarks

1

RUN

_

RUN

No need of running the ta

pe recorder.

2

IENTE~--

RUN

Recording sound

is

audible.

3

RUN

Recording sound goes out and "1 O." is

displa

yed on

the

display for a period of about 1 second.

4

-

RUN

[Cautions]

1.

Check the machine with the check procedure provided

separately, if the cassette tape happens to

keep running at Step 3,

the cassette tape fails to run at Step 5,

or the cassette tape fails to stop

at Step 6.

2. Check the recording circuit of the CE121 if

no recording sound

is

audible at Step

5.

3. In case no reproducing sound

is

audible at Step 10, proceed to playback another recorded tape to

check if reproducing sound

is

audible with that

tape

.

If

reproducing sound

is

not audible with

that

tape, proceed to check the reproducing circuit of the CE121

as

it may be not

functioning

properly.

If

the reproducing sound is

audible with the second

tape, check the recording circuit

of the CE

121

as

no proper recording may not have been carried

out

.

6. CHECK

PROG

F.

-

DISPLAY

READ

I N

1

I 21314151

6

I

1l s I

9

l1oln l12ll3lul15!16!11i

1al19I

l

[1lliJ

>

-

2

IALL RESET

!

>

I

'

3

5/9 !ENTE

R!

I

5

5 5 5 5

5 I 5

5

-

4

IMODEI

>

,

5

I

p

· ls

HFT

I

w

o

K lsHFTI

w

IENTERI

l

:

p

R

I N

T

"'

0

K

"'

2 lS

HFT

I w z lsH

FTI w P

"'

"'. p

'

l

~

6

2

z

7

I SHFT

I w s ISHFT

I w !ENTER!

2

:

"'

z

"'

p

R

I N

T

"

s

"'

I

I I

8

3

B E

E p 2

IEN

TERI

3 : B

E E

P

2

IM

ODEI

~,

'

I

•

9

>

I

G R A D iENTE

Rl

I

1

0

>

,

I

·l

11

I SHFTI

ISPCI

0

I

4

7 IEN

TERI

:

0 l 4

7

IMODEI

I

1

2

>

,

'

ISHFTI

z

I

1

3

s

14

IMODEI lsHFTllsPcl

0

I 4 7

15

@RA

D

IEN

TERI

I

>

I

6

R

· lE

NTER

l

0

K

1

I

ENTER

I

T

1

7

s

I

1

8

I

ENTER

I

'r

T

'r

.:

>

'

-

!OFF

I

1

9

-

'

T

I

20

'

'r

21

I

2 2

23

I

-

2 4 25 26

I

T

l

'

27

I

;

-

28

I

.

I

29 3

0

I

3

1

I

'

I

32 33

I

'

' '

l l

'

"l

34

I

'

l

'

35

I

'

l

I

v

B

I

3 6

I

' ' '

'

37

I

'

3

8

I

'

3

9

'

40

25

DISPLAY

SYMBOL

Cassete

11

I 12 I 1

3

lu

I

15

I

!6 I 1

1

I

i

s

I

19

I 20 I 21I22 I 2 3 I 2 4

S

HFT

DEG PRO

~

S

mm

PL

A) REC

STO

P

REMJT]

RAD

GRAD DE

F

RUN

I

0 0

I

5

5 5 5 5 5

5

E -

0

1

0 0

I

0

K

'f

(

0)

0 0

I

(

0)

0 0

T'

s

T'

I

(0)

I

0 0 0

0

I

0

0 0

(0)

0 0

I

0 0

(0)

0 0

(0)

0 0

I

0

0 0

I

0 0

0

I

·

'

I

!HECK PROGRAM

26

H ~~Hn

....

.

SUB PWB

n

VGG*

--

D

DF/F

Q

~

s

0000

16

1 2 3

4

a

K'

C

P

G

L i PR

l

1

H

A

,

S

16L

lOOKn

--ir-+-+--+-l--1...J""-/C-H-+-L---'''

5 6

l~O~

P;;;F

t---f-+-H----1J

50

WV

I

D-7-

GND

I

nl

~

VGG

I

L..----....J

S4"

'-

,_

--

-

µ_,.-

,

•B

2a

~~

~:

I

t:-:t--'A_2

__

-J.. __

'--------!lrt--++-----i· ill

1

I

5

:

I

~

I

•

Bla

~-~

I

T.Q''~A=l

~--r------=i-

---r-tt-t---++----+'~D

·101

I

7

I

'Q

'"

";,

- -

_

J

:· ioxo

r

' 3

~

1-1-

CMT ' lOKn"\....___,.

~lt-t---t-+-t---~-l--1-LJ

J'k/1..,/ e

Recording

TC4011 UBP

.,,,..._] - -

Signe

q

[rc

4-059

p

l

12 I

I

A3

-

514

R

EM OTO

Signet

I

VGG

I

Op

tion

Jo

Co

ntrol

I I

51

3

I

l

I

D

AT

AI

515

I I

I

c

M

T

I

Ki4

~

~~C!_l~

!_,

CCZZ

J

I

Opt ion: I/0 connect signal

I

7-1. Operation Circuit

Diagram

7. CIRCUIT DIAGRAM PARTS

5

16L

R/Wb Xin

A S Sn

8

i

AAAAAAA

7654321

GRAM

PARTS

&

SIGNALS

POSITION

F

2a

F 3a

F

4a

BP

13

1

9

TC40

69P

[~J_

1

2

I

D

8

V

M

,____

_

1:::

-

B

P

VM

§=

~

·-v.

-

56'

BP

>--'-

D51

5BBL1

L:

56'

._~

i

TC4019P

(2)

~

V

nrsP Vnrsi ~

1AS

'-----

i2

gi

0

TC4066

P

113

I

~

l

M

I

(RAM

)

A

7

-

TC 5514PX

3

12

I

~

I

,___

I

,___

-

I IA6

-

(3)

-

'-'-

11

1

'-'-

150Kn

I

-

~

L-

F

4a

1

GKD

Tbermi stor

I

-

h

~

tJ

GND

I I

VA

_

IA5

10

l

>

~

,!

<R

"~:

~

"'

~

I

~

-

~

-H

I

~

,___

VM~

r----

....J

>

--,TC4019P(I

J

--

,.

'-

i

!OW

V

I

-

--

=z~

~

=-

IOOKn

~

.._

~

-

- JOQ

µF

IA4

Vg

-

i.lf

13 I

'-'-

(21

I

>-

'-'-

i~~

}

2~

Kn

I

--

'-'-

-

I

F3a

1

Vmsr

~

.--

'-'

Von

'-

.._

I

~

::;J

1

'-

IA3

'-

1

2

I

L-~

I

VGG

"

I I

~

I

!A2

A

7

GND

-

A6

AB>--

1

11

I

A5

Si

-r-

I

A4

Sn

~

I

'-

Al

DIOl

-

I

A

2

(I)

DI0

2

-

A

3

DI03

I

F

2a

1

,

.

•A

l

DI04

-

vGG

R

A''

~

10

I

IOOKn

.

"

_J

·

~

1~PF

-

.,,

r=n

PWB

'

~

0

28

FUNCTI

ON

7-3. Key

Circuit

DODOO

0

D

0

D

ODOO

0

D

0 0

0

D D D

0 0 0 0

D 0

0

D

0

o o o

D

0

D

0

D

0

D D D 0 D

D D

0

DD

00

D D

0

D

B

D~

00

0

D

D D

0

ODD

D 0

0

D

0

DO

qoo

D

D D D D O D D D , D

DO

D

ODD

D D D D

DODD

D

DO

D D

DD OD

D D D D D D

D D

0

D

D D D D D D

DODOO

DOD

D O

o o

D

0

D D

ODO

0 0 D D D

ODD

ODD 0 D D D

DOD

D

0

0 0

DO

D

DO

D

o

D

D D

D

D D D D O D D O D O D D

ODD

0000

0

D D D D D D

D

0

D D D 0 000

00

D

0

D D

D

0

ODD

O

D D D DD

D

D D

ODO

DO

DOO

DD

D

DODOO DD DD DODOO

D

ODOO

DODOO

D

D D D D D

D

O

D D O

DDO D D D D

D

OD

DO

DOO

0

o o o o o

o

o o

o o o o o

o

D

0

O

ODD

o o o

00

0

o

o o

DO

D

ODDO

o o

D 0

0000

o

o o

ODD

D D

0 D

D D

D D D

O D

DD

D

DOD

OO

D

0

DODD

D

0

DO

DOO

DODOO

0 D

DODO

0 0 D

DO

D D

D 0

0

D

0

D

0 0

DODO

D 0

000

00 DODOO D D

D

0

D

DODOO

0

ODDO

D D

0 0 DD

ODD OD

D

DO

D D

D

0

DODOO

0 0

DD OD

ODDO

0 0

DODO 0

0

DOD

0 0

0 0 D D

0

ODO

0

D D D

DOD

D D

0

DODOO

D

DOD

D

0000

ODD

D D

D O

0 D

D 0

D

0

O

DO

0000

D

0

D

ODD

O D D D

0000

D

D D D

D

...

• •

•

.

•

•••••

DD OD O

D

DO

0 0 0

D

DOD

OO

0

D

0

0000

0 0

D D D D

D

• •

.

••

•

...

.

•

••

.

• •

.....

• •

•

.

•

.

..

.

•

...

f

""

~

H MR44X4

~ !5

~t~~f~

~ ? ~

))) )

Ht

~

J

J J

~ t•••"''

~"~"'~"~·~~,

'--

$2']Vl

VlUlVlVl'Jl

UllJlU'IVlVlllll.fl00Vl<ntl)S

~~

'--

sza

sn

l----"

-

s2s

ss

~

,...____

580

54 ___,;

--

cw

SC43125

ss

-'

I'- 58

1

52

____,

r--

s32

DJS

PLAY CH!P(3

)

SI

~

['--- Sas

AS

_......,

t"--

53

4

A7 ---+.

bM

535~*

*~~~~~~~

~~s

~~<~AS~

I'--- 531

52 -

C---

532

DlS

PLAY CH]P(2

)

SI

-

i'--

S3

3

A5

_......,

I'-- 53

4

A7--+.

~ 585~ ~~~~ ~~~

~~ ~~~~<~<AB~

~ S2

7~~~~~~:;~~~~~~;;~~~

)_

'--

s2s

se

-

----

529

S5

---"

'---53-0

S•-

...---

GND

SC4312

5

ss

-

r

r r

~

r r

~

J

~ r r

s

-

,,

_

,,

_

,.

_

ss

-

- =~

~~

I

,\

=-_, .,.-_-

=-= ~~

'O.':

~rJ~

1

:

~

rJ~

~

I~=

I

\

-

6±M

I

J

=-=-=-

....

I I I

I

: :

:

~l

;:::~

~~=J

)~

-==-

-=-~~~

1--:

I o

I

\

++

+

I

~

li:

~

fij•~

~l*

~

s

=

!

=-~

l"t

-~

_____

..;

(' MSM401 3RS

~

i-------

~

,__-1•1•

AAX3

30

r

4

CMT

REMOTE

Y4

W

(

s

14)

5

33!1

3

5

0WV

0.047 FF

470Kn

VG

G

lOOK

n

e

16WV

15

14

Ef>

lO)lF

QB

2

SA7

33

12

10

GND

BQB 9

%

W

11

TC

4528

13

B

P

33

!1

50WV

0. 0

47 )lF 470 Kn

lOOKn

TC4069P

DS1588Ll

6

DS1

588

Ll

lOOKn

0.( 25

47

0Kn

2S

A 733

CMT

L

OAD output

(

KI 5 )

RECORD inp

ut

( F4")

7-5. CE-121 Circuit Diagram

R

E.YOTE

EAR PHONE

MI

C

..

~

..

~,~

I

,

3

:

L------------J

1

4

'----1•1•

AAX3

%

W

33

.n

1

Y

4W

33

.n

N

R 5711

r---- --- --- -.,

5

I

'--~~~~~~+---<~>-----.-..

:

I

2

SC458KS

12

O.Ol

µF 2SC

458KS

25

WV

lOOK.n

0. 047

J1-

F/5

0WV

..

,t

..

.

,.

I

i

uo

2

SA 733

PC-1211-

[gj

NO

.

PART TMANEI 5PAKCE

TiN5E2

LPLTP

I TLABZI RR-DZ

I RR-DZI RR-DZI RVR-ME VCEAAL VCKYPL VHDD51

VHHl54

VHi5C4

VH i 5C4 VHi5C4 VHiTC4 VHiTC4 VHiTC4 VHiTC4 VH i TCE VRC-M1 VRD-51 VRD-51 VRD-51 VRD-51 VRD-51 VRD-51 VRD-51 V525C4 V525..J

4 RC-5ZI RCR5PI VCKYPL VCTY

PL

RC-5Z

I

VRD-5

1

VCK

YPL

DKiT

-1

PC-1211-[j]

32

NO

.

PARTS

CODE

DESCRIP

TI

ON

NEW

PARTS

PRICE

RAN

K

MARK RAN

K

1

LX-BZ I I

02CCZZ

S

cre

w

N

c

A

B

2

LX-BZI032CCZZ

S

cre

w

c

A A

3

HDECAl705CCZZ

B

ottom

cabine

t

N

D

A

N

4

PZETLl323CCZZ

Ins

ulator sh

eet

N

c

A

B

5

PTPEHI062CCZZ

T

ap fo

r

chassis

c

A A

6

LCH551078CCZZ

C

hassis

N

c

A

c

7

GFTAAl231CCZZ

L

id

N

D

A

B

8

XBP5D20P09000

S

cre

w

c

A

9

RALMBl006CCZZ

Buzzer

B

A

H

10

LX-BZI060CCZZ

Screw X9

o

A A

11

XTP5D20P05000

Screw

c

A

12

QCNTMI036CCZZ

A

l l reset switch

o

A

B

13

PCU551081CCZZ

Cushion

c

A

14

QCNW-1 I 35CCZZ Flex

ib le wire (22

)

N

B

A

o

15

QCNCWl259CCOi

Connector (9pin)

N

B

A

H

16

PGUM5

I I

90CCZZ

Rubber

connector

c

A

F

17

VVLLF8017..JE-I

LCD

N

B B

A

18

PTPEHl033CCZZ

Tape for LCD

c

A

19

LANGK1290CCZZ

Angle for LCD

c

A

D

2 0

PFiLWl230CCZZ

F

ilte

r

c

A

H

2

1

HDECAl527CCZZ

D

isp

lay mask

c

A

c

22 PFi

LWl228CCZZ

Display filter

.

c

A

c

23

PGUMMl254CCZZ

Key ru

bber

B

A

K

24

M5PRCI098CCZZ

E

arth

spring

c

A

25

..JKNBZ1515CC04

Key

top (18key

)

N

c

A F

26

..JKNBZl515CC05

Keyt

op

(17key

)

N

c

A F

27

..JKNBZl516CC02

Keyt op (SHIFT) X

20pcs

N

c

A

E

28

..JKNBZ1566CCOI

Keyt op (ENT ER) X 1 0 pcs

N

c

A

G

29

..JKNBZ1492CC02

Keyt

op (Numeral

)

N

c

A

E

30

..JKNBZl567CCOI

Keyt op (CL) X20pcs

N

c

A

E

3

1

QTANZl287CCZZ

"Battery terminal

(+,

-)

c

A

B

32

QTANZ1292CCZZ

Battery te

rminal

(

+)

c

A

B

33

QTANZl250CCZZ

Battery

terminal

(-)

c

A

B

34

XU55D20P04000

Screw

c

A

35

LANGTl336CCZZ

A

ngle

for

bottom cabinet

N

c

A

B

36

CCABB2299CC02

T

o p c

abinet

N

D

A

s

3

7

GFTAA1232CCZZ

Lid for connec

tor

N

D

A

B

38

QCNW

-1 I 37CCZZ

Flexibl

e wir e

N

B

A

c

39

QTANZl293CCZZ

B

attery te

rminal

(+.-)

N

c

A

B

UBAGZ I 2 I I

CCZZ

Hard ca se

N

D

A M

SPAKA5108CCZZ

Packing cushio

n

N D

A

F

TiNSE3137CCZZ

Instruction

book

(U.S. A)

N D

A

p

8. PC-1211 PARTS LIST & GUIDE

PC-1211-[g]

1

33

NO

.

PARTS CODE

DESCRIPT

ION

NEW

PARTS

PRICE

::r,;.

MARK RAN

K

TMANEIOIOCCZZ

Program lib

rary

N

D

A

z

SPAKC5012CCZZ

Pack

ing

case

N

D

A

G

TiNSE2826CCZZ

Basic text

N

D

A

K

LPLTPl070CCZZ

Tenplat

e

N

D

A

8

TLABZl295CCZZ

Name lavel

D

A A

RR-DZI006CCZZ

R

esisto

r

1/BW

143Kohm ±2%

c

A

B

RR-DZl007CCZZ

R

esistor 1 /

BW

12. 7Kohm ±2%

c

A

B

RR-DZI008CCZZ

R

esistor 1 /

BW 21.0Kohm ±2

%

c

A

B

RVR-MB510QCZZ

V

aliable resistor

250Kohm

c

A

D

VCEAAUIAW107Q

Capa

cit

or

lµF

50V

c

A

E

VCKYPUIHB221K

Capacit

or 220PF 50V

c

A

8

VHDDSl588Ll-I

Diode

DS1588L1

8

A

D

VHHl54KD-5

/-I

Ther

mistor

150Kohm

B

A

c

VHiSC43125

/

-I

L. S. i (Dis

play chip

)

B

A

x

VHiSC43157

/

-I

L. S. I (

CPU-

I

)

N

B

F

VHiSC43178

/

-I

L. S.

i

(

CPU-

II)

N

8

D

VH i TC40 I I

UBP

I

i. C.

8

A F

VHiTC4019P

/-I

i.

C.

B

A

K

VHiTC4066P/-I

i. C.

8

A

K

VHiTC4069P

/

-I

i. C

.

B

A

H

VHiTC5514P/-I

L. S. i

(

RAM

)

8

B

D

VRC-MT2BGl65J

R

esistor

1/BW

1.6Mohm ±5

%

c

A

8

VRD-ST2BYIOIJ

R

esistor

1/BW 100

ohm ±5

%

c

A A

VRD-ST2BY223J

R

esisto

r

1/B

W

22Kohm ±5

%

c

A

VRD-ST2BYl03

J

R

esistor

1/BW 10Kohm ±5%

c

A A

VRD-ST2BY104J

Resisto

r

1/BW

100Kohm ±5

%

c

A A

VRD-ST2BYl05J

Resist

or

1/BW 1Mohm ±5%

I

c

A

VRD-ST2BY472

J

Resistor

1/B

W

4.7Kohm ±5%

I

c

A A

VRD-ST2BY474

J

Resist

or

1/B

W

470Kohm ±5

%

I

B

A A

VS2SC458KS

/-I

Transistor

2SC458KS

B

A

c

VS2SJ40-///-I

MOS FET

2SJ40

c

A

G

RC-SZl005CCZZ

Capacitor

0.1µ

F lOV

c

A

c

RCRSPl024CCZZ

C

rystal

N

c

A

H

VCKYPUIHBIOI

K

C

apacitor

lOOPF 50V

c

A

VCTYPUIEX

I03M

Capa

cito

r

l

OOOOPF 25

V

c

A

B

RC-SZl007CCZZ

Capacitor lµF lOV

I

c

A

F

VRD-ST2BY224J

Resistor 1 /

BW

220Kohm ± 5%

c

A A

VCKYPUIHBI02K

Capacitor 1 OOOPF 50V

c

A

DKiT-IOOICCZZ

SUB-PWB

Kit

N

•

33

l

/.iii

34

NO

.

PARTS CODE

DESCRIPTION

NEW PARTS

PRICE RANK

MARK RANK

1

GCABA2315CCZZ

Bot

tom cabinet

N

D

A

G

2

LX-BZl038CCZZ

Screw

c

A A

3

GLEGGIOl2CCZZ

Ru

bber foot

c

A

4

GFTABl235CCZZ

B

attery lid

N

D

A

c

5

XTBSD20P06000

S

crew

c

A A

6

QPLG..JI008CCZZ

P

lug

N

B

A

Q

7

QCNCMl260CCOI

C

onnector

(9pin

)

N

B

A

G

8

XTBSD20P05000

Screw

c

A A

9

LANGTl334CCZZ

An

gle

N

c

A

c

10

QTANZl266CCZZ

Bat

tery

terminal

9

c

A A

11

QTANZl072CCZZ

Ba

ttery ter

mina

l

EB

c

A

12

HDECAl684CCZZ

D

ec.

panel

A

N

D

A

c

1

3

HDECAl685CCZZ

Dec.

panel

B

N

D

A

D

14

GCABB2316CCZZ

T

op

cabinet

N

D

A

G

SPAKA5097CCZZ

P

acking case

N

D

A

D

SPAKC5

I I

I

CCZZ

P

acking case

N

D

A

D

SPAKA5109CCZZ

Pa

cking cushion

N

D

A

E

VCEAAUICWI06Q

Capacitor

10

µF 16

V

c

A

B

VCQYKUIHM472K

Capacitor 0.

004

7µF

50V

c

A

B

VCQYKUIHM473K

Capacitor

0.047µF 50

V

c

A

B

VCTYPUIEXI03M

C

apacitor

0.01µF 25

V

c

A

B

VCTYPUINXI04M

Capacitor

0.1µ

F 12V

c

A

B

VHDDSl588Ll-I

Diode

DS1

588

L1

B

A

B

VH i NR57

I I/ /-1 Relay

NR571

1

N

B

A

w

VHiTC4069P/-

I

I.

C. TC4069

P

B

A

H

VHiTC4528BP-I

I.

C.

TC452

8BP

N

B

A

p

VRD-ST2BYI03..J

R

esistor

1/8W

10Kohm

±5%

c

A A

VRD-ST2BYl04..J

R

esistor

1/8W 1

00K

ohm ±5%

c

A A

VRD-ST2BYl05..J

R

esisto

r

1/8

W

1Mohm ±5%

c

A A

VRD-ST2BYl83..J

R

esisto

r

1/8

W

18Kohm

±5

%

c

A A

VRD-ST2BY223..J

R

esistor

1/B

W

22Kohm ±5%

c

A A

VRD-ST2BY271..J

R

esisto

r

1/8W 270ohm ±5%

c

A A

VRD-ST2BY474..J

R

esistor

1/8W

470K

ohm ±5

%

c

A

VRD-ST2BY564..J

R

esistor

1/B

W

560K

ohm ±5

%

c

A A

VRD-ST2EY330..J

R

esistor

1/4

W

33ohm ±5%

c

A A

VS2SA733-

//-I

T

ransistor 2SA7

33

B

A

D

VS2SC458KS/-I

Tr

ansistor

2SC458KS

B

A

c

J

9. CE-121 PARTS LIST & GUIDE

35

1

0

~

/

~5

7 .~

4

SHARP CORPORATION

Industrial Instruments Group Reliability & Quality Control Department

Yamatokoriyama, Nara 639-11, Japan

1

981

March Printed

in Jap

an

•