The VND670SP is a monolithic device made
using STMicroelectronics VIPower technology,
intended for driving motors in fullbridge
BLOCK DIAGRAM
10
1
PowerSO-10
configuration. The device integrates two 30 m
Power MOSFET in high side configuration, and
provides gate drive for two external Power
MOSFET used as low side switches.IN
allow to select clockwise or counter clockwise
and IN
A
drive or brake; DIAGA/ENA, DIAGB/ENBallow to
disable one half bridge and feedback diagnostic.
Built-in thermal shut-down, combined with a
currentlimiter,protectsthechipin
overtemperature and short circuit conditions.
Short to battery protects the external connected
low-side Power MOSFET.
V
CC
Ω
B
DIAGA/EN
DIAG
PWM
(*) See note at page 5
IN
A
IN
B
A
/EN
B
B
Undervolt.
Overtemp.AOvertemp.
INTERNAL
SUPPLY
LOGIC
B
Current
Limiter B
Short to battery
Short to battery
Current
Limiter A
GND
OUT
OUT
GATE
GATE
A
B
A
B
June 20001/13
1
VND670SP
ABSOLUTE MAXIMUM RATING
SymbolParameterValueUnit
V
I
max1
I
max2
I
I
I
EN
I
pw
I
gs
V
ESD
T
T
STG
CURRENT AND VOLTAGECONVENTIONS
Supply voltage-0.3 .. 40V
CC
Maximum output current (continuous)15A
Maximum output current (250 ms pulse duration)20A
Reverse output current (continuous)-15A
In normaloperating conditions the DIAGX/ENXpinis considered asan input pin by the device. Thispin must be externally
pulled high.
IN
A
IN
DIAGA/ENADIAGB/EN
B
OUT
B
OUT
A
GATE
B
GATE
A
B
1111HHLLBrake to V
1011HOPENLHClockwise
0111OPENHHLCounter cw
0011OPENOPENHHBrake toGND
XX00OPENOPENLLStand by
1X10HOPENLLHS
0X10OPENOPENHLMOS
X101OPENHLLHS
X001OPENOPENLHMOS
PWM pin usage:
In all cases,a “0” on the PWM pin will turn-off both GATE
GATE
turn on again depending on the input pin state.
B
and GATEBoutputs. When PWM rises back to “1”, GATEAor
A
TYPICAL APPLICATION CIRCUIT FOR DC TO 10KHz PWM OPERATION
R
prot
1K
DIAGA/EN
R1
A
+5V
V
CC
+5V
R1
DIAGB/EN
VND670SP
R
prot
1K
PWM
R
prot
1K
IN
A
GATE
OUT
A
A
UP
GND
R
gnd
(*)
OUT
B
IN
B
GATE
B
Comment
CC
only
A
only
A
only
B
only
B
R
prot
1K
B
R
prot
1K
M
DOWN
External Power Mos A
(*) Reverse battery protection:
- series relay in VCCline: R
- series fuse in VCCline with antiparallel diode between ground and VCC:R
=0 Ohms
gnd
External Power Mos B
=10 Ohms.
gnd
5/13
VND670SP
TYPICAL APPLICATION CIRCUIT FOR A 20KHZ PWM OPERATION
R
prot
1K
R
prot
1K
R
prot
1K
DIAGA/EN
IN
PWM
27Ω
+5V
R1
DIAGB/EN
R
prot
1K
B
R1
A
+5V
V
CC
VND670SP
OUT
A
GATE
A
A
R
(*)
gnd
UP
OUT
B
R
prot
1K
B
GATE
IN
B
M
D1
D2
DOWN
27Ω
External
Power Mos A
External
Power Mos B
(*) Reverse battery protection:
- series relay in VCCline: R
- series fuse in VCCline with antiparallel diode between ground and VCC:R
=0 Ohms
gnd
6/13
=10 Ohms.
gnd
VND670SP
WAVEFORMS AND TRUTH TABLE(CONTINUED)
In case of a fault condition the DIAGX/ENXpin is consideredas anoutput pin by the device.
The fault conditions are:
- overtemperature on one or both high sides;
- short to battery condition on theoutput (saturation detection on the external connected Power
MOSFET).
Possible origins of fault conditions may be:
OUT
is shorted to ground ---> overtemperature detection on high side A.
A
OUT
is shorted to VCC---> external Power MOSFET saturation detection (driven by GATEA).
A
When a fault condition is detected, the user can know which power element is in fault by monitoring the IN
EN
and DIAGB/ENBpins.
A
In any case, when a fault is detected, the faulty half bridge is latched off. To turn-on the respective output (GATE
OUT
) again, the input signal must rise from low to high level.
The PWM pin allows to test the load connection between two half-bridges. In the test mode (V
Power Mos gate drivers are disabled. The IN
to connect one side of the load at V
continuity of the load connection. In case of load disconnection the DIAD
CC
pulled down.
orINBinputs allow to turn-on the High Side A or B, respectively, in order
A
voltage. The check of the voltageon the other side of the load allow to verify the
CAll functions of the device are performed as designed after exposure to disturbance.
E
Test Levels ResultITest Levels ResultIITest Levels Result
III
One or more functions of the deviceare not performed as designed after exposure to disturbance
and cannot be returned to proper operationwithout replacing the device.
Test Levels Result
IV
8/13
1
Figure 1: Test conditions for High Side switching times measurement.
VND670SP
V
OUTA, B
(dV
OUT
/dt)
80%
on
90%
(dV
OUT
/dt)
off
10%
t
V
INA, B
t
d(on)
t
r
t
d(off)
t
f
t
Figure 2: Testconditions for external PowerMOSFETswitchingtimesmeasurement.
V
gsA, B
80%
10%
90%
20%
t
V
pw
t
dong
t
rg
t
doffg
t
fg
Figure 3: Definitionof the external Power MOSFET turn-ondead time t
IN
A
IN
B
OUT
A
V
gsA
t
del
t
del
9/13
11
VND670SP
Waveforms
NORMAL OPERATION(DIAG
DIAGA/EN
DIAGB/EN
IN
IN
PWM
OUT
OUT
GATE
GATE
A
B
A
B
A
B
A
B
NORMAL OPERATION(DIAG
DIAGA/EN
DIAGB/EN
IN
IN
PWM
OUT
OUT
GATE
GATE
A
B
A
B
A
B
A
B
/ENA=1, DIAGB/ENB=1)
A
/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
A
10/13
1
CURRENT LIMITATION/THERMALSHUTDOWN or OUTASHORTED TO GROUND
Information furnished is believed to be accurate and reliable. However,STMicroelectronicsassumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patentrights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replacesallinformation previously supplied. STMicroelectronics products
are not authorized for use as critical components in lifesupport devices or systemswithout express written approvalof STMicroelectronics.
Australia - Brazil - China - Finland- France - Germany - Hong Kong - India - Italy - Japan - Malaysia -Malta -
Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - Printed in ITALY- All Rights Reserved.
STMicroelectronics GROUP OF COMPANIES
http://www.st.com
13/13
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