Datasheet VNH5019A-E Datasheet (ST)

Features

Typ e R

VNH5019A-E

■ ECOPACK

■ Automotive Grade: compliance with AEC

DS(on)

18 mΩ typ

(per leg)

®

: lead free and RoHS compliant

I

out

30 A 41 V

guidelines

■ Output current: 30 A

■ 3 V CMOS compatible inputs

■ Undervoltage and overvoltage shutdown

■ High-side and low-side thermal shutdown

■ Cross-conduction protection

■ Current limitation

■ Very low standby power consumption

■ PWM operation up to 20 khz

■ Protection against:

– Loss of ground and loss of V

■ Current sense output proportional to motor

CC

current

■ Charge pump output for reverse polarity

protection

■ Output protected against short to ground and

short to V

CC

Description

The VHN5019A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side drivers and two low-side
switches. The high-side driver switch is designed
using STMicroelectronics’ well known and proven
proprietary VIPower
to efficiently integrate on the same die a true

®

M0 technology that allows

VNH5019A-E

Automotive fully integrated

H-bridge motor driver

V

ccmax

MultiPowerSO-30™

Power MOSFET with an intelligent
signal/protection circuit.

The three dice are assembled in
MultiPowerSO-30 package on electrically isolated
lead-frames. This package, specifically designed
for the harsh automotive environment offers
improved thermal performance thanks to exposed
die pads. The input signals IN
directly interface to the microcontroller to select
the motor direction and the brake condition.

The DIAG

/ENA or DIAGB/ENB, when connected

A

to an external pull-up resistor, enable one leg of
the bridge. They also provide a feedback digital
diagnostic signal. The CS pin allows to monitor
the motor current by delivering a current
proportional to its value when CS_DIS pin is
driven low or left open. The PWM, up to 20 KHz,
lets us to control the speed of the motor in all
possible conditions. In all cases, a low-level state
on the PWM pin turns-off both the LS
switches. When PWM rises to a high-level, LS
LS

turn-on again depending on the input pin

B

state.

Output current limitation and thermal shutdown
protects the concerned high-side in short to
ground condition.

The short to battery condition is revealed by the
overload detector or by thermal shutdown that
latches off the relevant low-side.

Active V

pin voltage clamp protects the device

CC

against low energy spikes in all configurations for
the motor.

CP pin provides the necessary gate drive for an
external n-channel PowerMOS used for reverse
polarity protection.

and INB can

A

and LSB

A

A

or

December 2011 Doc ID 15701 Rev 8 1/37

www.st.com

1

Contents VNH5019A-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Waveforms and truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.1 Thermal calculation in clockwise and anti-clockwise operation in

steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1.2 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2 MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.3 MultiPowerSO-30 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . 32

4.4 MultiPowerSO-30 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2/37 Doc ID 15701 Rev 8

VNH5019A-E List of tables

List of tables

Table 1. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 7. Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 8. Switching (V

Table 9. Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 10. Current sense (8 V < V

Table 11. Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 12. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 14. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 15. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 16. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 17. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 27

Table 18. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 20. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

= 13 V, R

CC

= 0.87 W, Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

LOAD

< 21 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CC

Doc ID 15701 Rev 8 3/37

List of figures VNH5019A-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection

(option A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection

(option B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 21

Figure 11. Waveforms in full bridge operation (part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Waveforms in full bridge operation (part 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. Definition of delay response time of sense current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16. MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 26

Figure 19. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 20. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 28

Figure 21. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . 28

Figure 22. Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 23. MultiPowerSO-30 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24. MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 25. MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 26. MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4/37 Doc ID 15701 Rev 8

VNH5019A-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

6

##

#(!2'%
05-

0

/54

&!5,4
$%4%#4)/.

,3!?/6%24%-0%2!452%

/65

6

#,!-0?(3

(3

!

#522%.4
,)-)4!4 )/.?!

!

#,!-0?,3

,3

!

/6%2,/!$
$%4%#4/2?!

'.$

!

$2)6%2

!

$2)6%2

!

(3

!

+

,3

!

,/')#

$)!'!%.!).!#3 #3?$)3 07- )."$)!'"%.

0/7%2
,)-)4! 4)/.

,3"?/6%24%-0%2!4 52%

(3"?/6%24%-0%2!452%(3!?/6%24%-0%2!452%

$2)6%2

(3

#522%.4
,)-)4!4 )/.?"

+

$2)6%2

,3

"

#,!-0?(3

"

#,!-0?,3

"

/6%2,/!$

$%4%#4

"

/2?"

(3

"

/54

"

"

,3

"

'.$

"

("1($'5

Doc ID 15701 Rev 8 5/37

Block diagram and pin description VNH5019A-E

Figure 2. Configuration diagram (top view)

OUT

N.C.

V

IN

ENA/DIAG

CC

A

A

A

1

OUT

A

Heat Slug2

30

CS_DIS

EN

/DIAG

B

PWM

CS

IN

B

B

V

CC

Heat Slug1

CP

V

BAT

V

CC

OUT

B

Heat Slug3

N.C.

OUT

B

Table 1. Suggested connections for unused and not connected pins

15 16

Connection / pin Current sense N.C. OUTx

OUT

A

N.C.
GND

A

GND

A

GND

A

OUT

A

N.C.
V

CC

N.C.
OUT

B

GND

B

GND

B

GND

B

N.C.
OUT

B

INPUTx, PWM

DIAGx/ENx

CS_DIS

Floating Not allowed X X X

To ground Through 1 kΩ resistor X Not allowed

Table 2. Pin definitions and functions

Through 10 kΩ

resistor

Pin Symbol Function

1, 25, 30

2,14,17, 22,

24,29

3, 13, 23

12 V

OUTA,

Heat Slug2

N.C. Not connected

,

V

CC

Heat Slug1

BAT

Source of high-side switch A / drain of low-side switch A, power
connection to the motor

Drain of high-side switches and connection to the drain of the
external PowerMOS used for the reverse battery protection

Battery connection and connection to the source of the external
PowerMOS used for the reverse battery protection

Status of high-side and low-side switches A; open drain output.
This pin must be connected to an external pull-up resistor. When
externally pulled low, it disables half-bridge A. In case of fault

5EN

/DIAG

A

detection (thermal shutdown of a high-side FET or excessive

A

ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see

(detected on OUTA)

Table 13: Truth table in fault conditions

)

6/37 Doc ID 15701 Rev 8

VNH5019A-E Block diagram and pin description

Table 2. Pin definitions and functions (continued)

Pin Symbol Function

6CS_DIS

4IN

A

Active high CMOS compatible pin to disable the current sense
pin

Clockwise input. CMOS compatible

7 PWM PWM input. CMOS compatible.

Output of current sense. This output delivers a current

8CS

proportional to the motor current, if CS_DIS is low or left open.
The information can be read back as an analog voltage across
an external resistor.

Status of high-side and low-side switches B; Open drain output.
This pin must be connected to an external pull up resistor. When
externally pulled low, it disables half-bridge B. In case of fault

9EN

/DIAG

B

detection (thermal shutdown of a high-side FET or excessive

B

ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see

(detected on OUTA)

10 IN

B

11 CP

OUT

15, 16, 21

26, 27, 28 GND

18, 19, 20 GND

1. GNDA and GNDB must be externally connected together

B,

Heat Slug3

A

B

Counter clockwise input. CMOS compatible

Connection to the gate of the external MOS used for the reverse
battery protection

Source of high-side switch B / drain of low-side switch B, power
connection to the motor

Source of low-side switch A and power ground

Source of low-side switch B and power ground

Table 13: Truth table in fault conditions

.

(1)

(1)

)

Table 3. Block descriptions

(1)

Name Description

Logic control

Overvoltage + undervoltage

High-side, low-side and clamp
voltage

High-side and low-side driver

Linear current limiter

High-side and low-side
overtemperature protection

Low-side overload detector

Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the

Ta bl e 12

.

Shut down the device outside the range [4.5 V to 24 V] for the
battery voltage.

Protect the high-side and the low-side switches from the
high-voltage on the battery line in all configuration for the motor.

Drive the gate of the concerned switch to allow a proper R

DS(on)

for the leg of the bridge.

Limits the motor current, by reducing the high-side switch
gate-source voltage when short-circuit to ground occurs.

In case of short-circuit with the increase of the junction’s
temperature, it shuts down the concerned driver to prevent its
degradation and to protect the die.

Detects when low-side current exceeds shutdown current and
latches off the concerned low-side.

Doc ID 15701 Rev 8 7/37

Block diagram and pin description VNH5019A-E

Table 3. Block descriptions

Name Description

Charge pump

Fault detection

Power limitation

1. See

Figure 1

(1)

(continued)

Provides the voltage necessary to drive the gate of the external
PowerMOS used for the reverse polarity protection

Signalizes an abnormal condition of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.

Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.

8/37 Doc ID 15701 Rev 8

VNH5019A-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

CP

V

CP

I

INA

I

V

INA

V

INB

INB

I

ENA

IN

IN

CP

A

B

DIAGA/EN

I

ENB

V

ENA

V

ENB

DIAGB/EN

PWM

I

pw

V

pw

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “absolute maximum ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

program and other relevant quality document.

Table 4. Absolute maximum rating

I

BAT

I

S

BAT

GND

V

CC

CS_DIS

GND

A

OUT

OUT

CS

I

A

B

I

SENSE

I

CSD

V

B

CSD

I

OUTB

V

SENSE

OUTA

V

OUTB

V

OUTA

V

A

B

V

BAT

V

CC

GND

I

GND

Symbol Parameter Value Unit

V

V

I

max

I

I

I

I

CS_DIS

Maximum battery voltage

BAT

Maximum bridge supply voltage + 41 V

CC

Maximum output current (continuous) 30 A

I

Reverse output current (continuous) -30 A

R

I

Input current (INA and INB pins) +/- 10 mA

IN

Enable input current (DIAGA/ENA and DIAGB/ENB pins) +/- 10 mA

EN

PWM input current +/- 10 mA

pw

CP output current +/- 10 mA

CP

CS_DIS input current +/- 10 mA

(1)

-16

+41

V
V

Doc ID 15701 Rev 8 9/37

Electrical specifications VNH5019A-E

Table 4. Absolute maximum rating (continued)

Symbol Parameter Value Unit

V

- 41

V

V

T

1. This applies with the n-channel MOSFET used for the reverse battery protection. Otherwise V
shorted to VCC.

Current sense maximum voltage

CS

Electrostatic discharge (human body model: R = 1.5 kΩ,

ESD

C = 100 pF)

Case operating temperature -40 to 150 °C

T

c

Storage temperature -55 to 150 °C

STG

CC

+V

CC

2kV

has to be

BAT

V
V

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max. value Unit

R

thj-case

R

thj-amb

Thermal resistance junction-case HSD 1.7 °C/W

Thermal resistance junction-case LSD 3.2 °C/W

Thermal resistance junction-ambient See

Figure 18

°C/W

10/37 Doc ID 15701 Rev 8

VNH5019A-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8 V < V

< 21 V, -40 °C < Tj < 150 °C, unless

CC

otherwise specified.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

CC

I

S

R

ONHS

R

ONLS

V

f

I

L(off)

Operating bridge supply
voltage

Supply current

Static high-side
resistance

Static low-side
resistance

High-side
free-wheeling diode
forward voltage

High-side OFF-state
output current (per
channel)

5.5 24 V

OFF-state with all fault cleared and ENx = 0 V
(standby):

= INB = PWM = 0; Tj = 25 °C; VCC = 13 V

IN

A

IN

= INB = PWM = 0

A

10 15

OFF-state (no standby):
INA = INB = PWM = 0; ENx = 5 V

ON-state:
IN

or INB = 5 V, no PWM

A

488mA

INA or INB = 5 V, PWM = 20 kHz

I

= 15 A; Tj = 25 °C 12.0

OUT

I

= 15 A; Tj = - 40 °C to 150 °C 26.5

OUT

= 15 A; Tj = 25 °C 6.0

I

OUT

= 15 A; Tj = - 40 °C to 150 °C 11.5

I

OUT

= 15 A,

I

f

= 150 °C

T

j

= 25 °C; V

T

j

= 125 °C; V

T

j

= ENX = 0 V; VCC = 13 V 3

OUTX

= ENX = 0 V; VCC = 13 V 5

OUTX

0.6 0.8 V

60

6

µA
µA

mA

mA

mΩ

mΩ

µA

Table 7. Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

Low-level input voltage

IL

High-level input

V

IH

voltage

I

Low-level input current V

INL

High-level input

I

INH

current

IHYST

Input hysteresis
voltage

V

Normal operation (DIAG
acts as an input pin)

Normal operation (DIAGX/ENX pin
acts as an input pin)

= 0.9 V 1 µA

IN

V

= 2.1 V 10 µA

IN

Normal operation (DIAGX/ENX pin
acts as an input pin)

/ENX pin

X

0.9 V

2.1 V

0.15 V

Doc ID 15701 Rev 8 11/37

Electrical specifications VNH5019A-E

Table 7. Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

= 1 mA 5.5 6.3 7.5

V

V

Table 8. Switching (VCC = 13 V, R

Input clamp voltage

ICL

Enable low-level

DIAG

output voltage

Symbol Parameter Test conditions Min Typ Max Unit

f PWM frequency 0 20 kHz

t

d(on)

HSD rise time

IN

= -1 mA -1.0 -0.7 -0.3

I

IN

Fault operation (DIAGX/ENX pin
acts as an output pin); I

= 0.87 Ω, Tj = 25 °C)

LOAD

= 1 mA

EN

Input rise time < 1µs
(see

Figure 9

)

V

0.4 V

250 µs

t

d(off)

t

t

t

DEL

t

rr

I

RM

Table 9. Protection and diagnostic

HSD fall time

LSD rise time (see

r

LSD fall time (see

f

Delay time during change of
operating mode

High-side free wheeling
diode reverse recovery time

Dynamic cross-conduction
current

Input rise time < 1µs
(see

(see

(see

I

OUT

(see

Figure 9

Figure 8

Figure 8

Figure 7

Figure 10

= 15 A

Figure 10

)

)12µs

)12µs

) 200 400 1600 µs

)110ns

)

250 µs

2A

Symbol Parameter Test conditions Min Typ Max Unit

V

USD

V

USDhyst

V

OV

I

LIM_H

I

SD_LS

VCC undervoltage
shutdown

V

undervoltage

CC

shutdown hysteresis

V

overvoltage shutdown 24 27 30 V

CC

4.5 5.5 V

0.5 V

High-side current limitation 30 50 70 A

Low-side shutdown current 70 115 160 A

High-side clamp voltage

V

CLPHS

(1)

(VCC to OUTA = 0 or

= 0)

OUT

B

= 15 A 43 48 54 V

I

OUT

Low-side clamp voltage

(1)

V

CLPLS

T

TSD

(OUTA = V
OUT

B

Thermal shutdown

(2)

temperature

or

CC

= VCC to GND)

= 15 A 27 30 33 V

I

OUT

= 2.1 V 150 175 200 °C

V

IN

12/37 Doc ID 15701 Rev 8

VNH5019A-E Electrical specifications

Table 9. Protection and diagnostic (continued)

Symbol Parameter Test conditions Min Typ Max Unit

T

TSD_LS

T

TR

T

HYST

1. The device is able to pass the ESD and ISO pulse requirements as specified in the

2. T

TSD

3. Valid for both HSD and LSD

Table 10. Current sense (8 V < V

Low-side thermal
shutdown temperature

(3)

Thermal reset temperature 135 °C

(3)

Thermal hysteresis 7 15 °C

is the minimum threshold temperature between HS and LS

< 21 V)

CC

= 0 V 150 175 200 °C

V

IN

Table 15

.

Symbol Parameter Test conditions Min Typ Max Unit

I

K

0

dK

0/K0

K

1

dK

1/K1

K

2

dK

2/K2

K

3

dK

3/K3

V

SENSE

I

SENSEO

t

DSENSEH

I

OUT/ISENSE

Analog current sense ratio
drift

I

OUT/ISENSE

Analog current sense ratio
drift

I

OUT/ISENSE

Analog current sense ratio
drift

I

OUT/ISENSE

Analog current sense ratio
drift

Max analog sense output
voltage

Analog sense leakage current

Delay response time from
falling edge of CS_DIS pin

= 3 A, V

OUT

= - 40 °C to 150°C

T

j

I

= 3 A; V

OUT

T

= -40 °C to 150 °C

j

I

= 8 A, V

OUT

= - 40 °C to 150°C

T

j

I

= 8 A; V

OUT

= -40 °C to 150 °C

T

j

I

= 15 A, V

OUT

T

= - 40 °C to 150°C

j

I

= 15 A; V

OUT

= -40 °C to 150 °C

T

j

I

= 25 A, V

OUT

= - 40 °C to 150°C

T

j

I

=25 A; V

OUT

T

= -40 °C to 150 °C

j

= 15 A, R

I

OUT

I

= 0 A, V

OUT

= 0 V,

V

IN

= - 40 to 150°C

T

j

I

= 0 A, V

OUT

= 5 V,

V

IN

= - 40 to 150°C

T

j

= 5 V, V

V

IN

I

SENSE

(see fig

SENSE

= 90% of I

Figure 13

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSEmax

)

= 0.5 V,

= 0.5 V,

= 1.3V,

= 1.3V,

= 2.4 V,

= 2.4 V,

= 4 V,

= 4 V,

4670 7110 10110

-19 19 %

6060 7030 8330

-14 14 %

6070 6990 7810

-12 12 %

6000 6940 7650

-12 12 %

= 1.1 kΩ 5V

= 0 V, V

CSD

= 5 V,

05

= 0 V, V

CSD

= 0 V,

0100

< 4 V, I

OUT

= 8 A,

50 µs

µA

V

= 5 V, V

t

DSENSEL

Delay response time from
rising edge of CS_DIS pin

IN

I

SENSE

(see fig

= 10% of I

Figure 13

SENSE

< 4 V, I

SENSEmax

)

OUT

= 8 A,

20 µs

Doc ID 15701 Rev 8 13/37

Electrical specifications VNH5019A-E

Table 11. Charge pump

Symbol Parameter Test conditions Min Typ Max Unit

EN

V

I

BAT

Charge pump output

CP

voltage

Charge pump standby
current

= 5 V V

X

ENX = 5 V, V

= ENB = 0 V 200 nA

EN

A

= 4.5 V 10.5

CC

+ 5 V

CC

CC

+ 10

V

2.4 Waveforms and truth table

In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled-high
PWM pin usage: in all cases, a “0” on the PWM pin turns-off both LS
When PWM rises back to “1”, LS

Table 12. Truth table in normal operating conditions

or LSB turn-on again depending on the input pin state.

A

and LSB switches.

A

IN

INBDIAGA/ENADIAGB/ENBOUTAOUTBCS (V

A

= 0 V) Operating mode

CSD

1 1 1 1 H H High imp. Brake to V

10 1 1 H LI

01 1 1 L HI

SENSE

SENSE

= I

/K Clockwise (CW)

OUT

= I

OUT

Counterclockwise

/K

(CCW)

0 0 1 1 L L High imp. Brake to GND

CC

14/37 Doc ID 15701 Rev 8

VNH5019A-E Electrical specifications

Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery

protection (option A)

V

BAT

Reg 5V

μ

C

DIAG

33nF

3.3K

1K

1K

1K

10K

1.5K

/EN

A

PWM

CS

+ 5V

V

A

HS

IN

A

LS

A

S

D

G

V

BAT

CP

CC

A HS

OUT

A

OUT

B

DIAGB/EN

B

LS

B

B

IN

B

M

GND

A

GND

B

Note:
The external N-channel Power MOSFET used for the reverse battery protection should have the following characteristics:

- BVdss > 20 V (for a reverse battery of -16 V);
< 1/3 of H-bridge total R

- R

DS(on)

- Standard Logic Gate Driving

DS(on)

+5V

3.3K

1K

1K

C

Doc ID 15701 Rev 8 15/37

Electrical specifications VNH5019A-E

Figure 5. Typical application circuit for DC to 20 kHz PWM operation with reverse battery

protection (option B)

V

CC

Reg 5V

DIAG

μ

C

33nF

Note:
The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple onto supply line at PWM
operation. Stored energy of the motor inductance may flyback into the blocking capacitor, if the bridge driver goes into 3-state. This causes a
hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500 µF per 10 A load current is recommended.

Table 13. Truth table in fault conditions (detected on OUTA)

3.3K

1K

1K

1K

10K

1.5K

A

/EN

PWM

IN

CS

+ 5V

A

A

HS

LS

A

GND

V

A

OUT

A

CC

V

CP

BAT

OUT

B

HS

B

LS

DIAGB/EN

B

B

IN

B

M

A

100K

S

G

D

GND

+5V

3.3K

1K

1K

C

B

IN

IN

A

1

B

DIAGA/EN

A

DIAGB/EN

B

OUT

A

OUT

B

H

1

0L

1

1HI

0

OPEN

0

0L

X X 0 OPEN

Fault Information Protection Action

Note: In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the

device. This pin must be externally pulled high.

In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.

16/37 Doc ID 15701 Rev 8

CS (V

CSD

High

impedance

/K

OUTB

High

impedance

=0V)

VNH5019A-E Electrical specifications

The fault conditions are:

● overtemperature on one or both high-sides (for example, if a short to ground occurs as

it could be the case described in line 1 and 2 in the

Ta bl e 1 4

);

● Short to battery condition on the output (saturation detection on the low-side

Power MOSFET).

Possible origins of fault conditions may be:

● OUT

● OUT

is shorted to ground. It follows that, high-side A is in overtemperature state.

A

is shorted to VCC. It follow that, low-side Power MOSFET is in saturation state.

A

When a fault condition is detected, the user can know which power element is in fault by
monitoring the IN

, INB, DIAGA/ENA and DIAGB/ENB pins.

A

In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn-on the
respective output (OUT

) again, the input signal must rise from low-level to high-level.

X

Figure 6. Behavior in fault condition (how a fault can be cleared)

Note: In case of the fault condition is not removed, the procedure for unlatching and sending the

device in Stby mode is:

- Clear the fault in the device (toggle: INA if ENA=0 or INB if ENB=0)

- Pull low all inputs, PWM and Diag/EN pins within tDEL.

If the Diag/En pins are already low, PWM=0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.

Doc ID 15701 Rev 8 17/37

Electrical specifications VNH5019A-E

Table 14. Electrical transient requirements (part 1)

ISO T/R

Test level

7637/1

Tes t Puls e

I II III IV Delay and impedance

1 -25 V -50 V -75 V -100 V 2 ms, 10 Ω

2 +25 V +50 V +75 V +100 V 0.2 ms, 10 Ω

3a -25 V -50 V -100 V -150 V 0.1 μs, 50 Ω

3b +25 V +50 V +75 V +100 V 0.1 μs, 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2 Ω

Table 15. Electrical transient requirements (part 2)

ISO T/R

7637/1

Test Pulse

I II III IV

1C C C C

2C C C C

3a C C C C

3b C C C C

4C C C C

Test levels

5C E E E

Table 16. Electrical transient requirements (part 3)

Class Contents

C

E

All functions of the device are performed as designed after exposure to
disturbance.

One or more functions of the device are not performed as designed after
exposure to disturbance and cannot be returned to proper operation without
replacing the device.

18/37 Doc ID 15701 Rev 8

VNH5019A-E Electrical specifications

2.5 Reverse battery protection

Against reverse battery condition the charge pump feature allows to use an external
N-channel MOSFET connected as shown in the typical application circuit (see

As alternative option, a N-channel MOSFET connected to GND pin can be used (see typical
application circuit in figure

Figure 5

).

Figure 4

).

With this configuration we recommend to short V

pin to VCC.

BAT

The device sustains no more than -30 A in reverse battery conditions because of the two
body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5019A-E is pulled-down to the V
inserted to limit the current sunk from the microcontroller I/Os. If I

line (approximately -1.5 V). Series resistor must be

CC

is the maximum

Rmax

target reverse current through microcontroller I/Os, series resistor is:

V

–

R

IOsVCC

--------------------------------=

I

Rmax

Figure 7. Definition of the delay times measurement

V

INA,

t

V

INB

t

PWM

t

I

LOAD

t

t

DEL

DEL

t

Doc ID 15701 Rev 8 19/37

Electrical specifications VNH5019A-E

Figure 8. Definition of the low-side switching times

PWM

t

V

OUTA, B

90%

80%

t

f

20%

10%

Figure 9. Definition of the high-side switching times

V

INA,

V

OUTA

t

d(on)

t

d(off)

90%

10%

t

r

t

t

t

20/37 Doc ID 15701 Rev 8

VNH5019A-E Electrical specifications

Figure 10. Definition of dynamic cross conduction current during a PWM operation

IN

=1, INB=0

A

PWM

t

I

MOTOR

t

V

OUTB

t

I

CC

I

RM

t

t

rr

Doc ID 15701 Rev 8 21/37

Electrical specifications VNH5019A-E

Figure 11. Waveforms in full bridge operation (part 1)

NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)

DIAGA/EN
DIAGB/EN
IN

A

IN

B

A

B

LOAD CONNECTED BETWEEN OUTA, OUT

PWM

OUT

A

OUT

I

OUTA->OUTB

B

CS (*)

t

CS_DIS

(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE

DEL

NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)

LOAD CONNECTED BETWEEN OUTA, OUT

DIAGA/EN

DIAGB/EN

IN

IN

PWM

OUT

OUT

I

OUTA->OUTB

A

B

A

B

CS
CS_DIS

A

B

B

t

DEL

B

CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND

IN

A

IN

B

I

OUTA->OUTB

T

DIAGA/EN

DIAGB/EN

jHSA

I

LIM

Tj < T

TSD

A

B

CS

CS_DIS

limitation

normal operation

current

power limitation

shorted to ground

OUT

A

22/37 Doc ID 15701 Rev 8

Tj =T

TSD

Tj > T

T

TSD_HSA

T

TR_HSA

TR

normal operation

VNH5019A-E Electrical specifications

Figure 12. Waveforms in full bridge operation (part 2)

OUTA shorted to VCC (resistive short) and undervoltage shutdown

CS_DIS

IN

A

IN

B

OUT

A

OUT

B

I

OUTA->OUTB

I

SD_LS

I

LSA

T

TSD_LS

T

j_LSA

DIAGB/EN

DIAGA/EN

CS

CS_DIS

IN

A

IN

B

OUT

A

OUT

B

I

OUTA->OUTB

I

LSA

T

j_LSA

DIAGB/EN

DIAGA/EN

CS

B

A

V<nominal

normal operation OUTA softly shorted to V

OUTA shorted to VCC (pure short) and undervoltage shutdown

I

SD_LS

T

TSD_LS

B

A

V<nominal

CC

normal operation undervoltage shutdown

normal operation OUTA hardly shorted to V

CC

normal operation under voltage shutdown

Doc ID 15701 Rev 8 23/37

Electrical specifications VNH5019A-E

Figure 13. Definition of delay response time of sense current

INPUT

CS_DIS

LOAD CURRENT

CURRENT SENSE

t

DSENSEH

t

DSENSEL

The VNH5019A-E can be used as a high power half-bridge driver achieving an
on- resistance per leg of 9.5 mΩ. The figure below shows the suggested configuration:

Figure 14. Half-bridge configuration

V

CP

IN

A

IN

B

/EN

DIAG

A

DIAGB/EN
PWM

CS_DIS

OUT

A

GND

CC

V

GND

B

OUT

BAT

B

M

A

B

A

V

BAT

OUT

CP

V

A

GND

CC

A

IN
IN

/EN

DIAG

A

DIAGB/EN

PWM

CS_DIS

OUT

GND

B

A
B
A
B

B

The VNH5019A-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAG
to put unused half-bridges in high-impedance. The figure below shows the suggested
configuration:

24/37 Doc ID 15701 Rev 8

/ENX pins allow

X

VNH5019A-E Electrical specifications

Figure 15. Multi-motors configuration

V

CP

IN

A

IN

B

DIAG

A

DIAGB/EN
PWM

OUT

A

/EN

CC

V

OUT

BAT

B

M

2

A
B

V

BAT

OUT

CP

V

CC

A

DIAG

/EN

A

DIAGB/EN

PWM

CS_DISCS_DIS

OUT

IN

A

IN

B
A
B

B

GND

A

M

1

GND

B

GND

GND

M

B

3

A

Doc ID 15701 Rev 8 25/37

Package and PCB thermal data VNH5019A-E

3 Package and PCB thermal data

3.1 MultiPowerSO-30 thermal data

Figure 16. MultiPowerSO-30™ PC board

Note:

Layout condition of Rth and Zth measurements (PCB FR4 area= 58 mm x 58 mm, PCB thickness=2 mm, Cu thickness=35 mm, Copper areas:
from minimum pad lay-out to 16 cm

Figure 17. Chipset configuration

2

).

CHIP 1

R

thA

R

thAB

Figure 18. Auto and mutual R

CHIP 2

R

thB

thj-amb

R

thBC

vs PCB copper area in open box free air

R

CHIP 3

R

thC

thAC

condition

50

45

40

35

30

25

20

15

10

°C/W

5

0

0 2 4 6 8 1012141618

cm2 of Cu Area (refer to PCB layout)

RthA
RthB = RthC
RthAB = RthAC
RthBC

26/37 Doc ID 15701 Rev 8

VNH5019A-E Package and PCB thermal data

3.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-state mode

Table 17. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode

Chip 1 Chip 2 Chip 3 Tjchip1 Tjchip2 Tjchip3

• R

P

ON OFF ON

ON ON OFF

dchip1

P

dchip1

ON OFF OFF P

P

ON ON ON

dchip1

P

R

dchip1

dchip3

R

• R

thAC

• R

thAB

) • R

thA

thA

• R

thA

+ P

+ T

+ P

+ T

thA

+ (P

thAB

amb

amb

+ T

+ T

dchip3

dchip2

amb

dchip2

amb

•

•

+

P

dchip1

P

• R

dchip1

P

dchip1

Pdchip2 • R

R

+ P

thAB

• R

R

thBC

thAB

• R

dchip3

thAB

+ T

+ T

+ P

amb

thAB

thB

• R

+ P

amb

dchip2

+ T

+ P

thBC

dchip3

• R

amb

dchip1

+ T

•

thB

•

amb

R

P

dchip1

P

dchip1

P

dchip1

thBC

P

dchip1

+ P

• R
R

• R

R

• R

thAC

+ T

thC

thAC

thBC

• R

thAB

dchip3

+ T

thAC

• R

+ P

amb

+ P

amb

+ T

+ P

dchip3

dchip2

dchip2

thC

amb

+ T

•

•

•

amb

3.1.2 Thermal calculation in transient mode

Ths= P

T

lsA

T

lsB

Figure 19. Chipset configuration

dhs

= Pd

= Pd

• Zhs + Z

• Zls + Pdhs • Z

lsA

• Zls + Pdhs • Z

lsB

hsls

• (Pd

+ Pd

lsA

+ Pd

hsls

+ PdlsA • Z

hsls

lsB

lsB

) + T

• Z

amb

+ T

hsls

+ T

hsls

CHIP 1

Z

amb

amb

ls

Z

hsls

CHIP 2

Z

ls

Z

lsls

Z

CHIP 3

Z

ls

hsls

Equation 1: pulse calculation formula

Z

THδ

where

RTHδ Z

δ tpT⁄=

THtp

1 δ–()+⋅=

Doc ID 15701 Rev 8 27/37

Package and PCB thermal data VNH5019A-E

Figure 20. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse

ZTH -HSD @ cu area

100

HSD-16 cm^2 Cu
HSD-8 cm^2 Cu
HSD-4 cm^2 Cu
HSD-footpr in t
HsLsD-16 cm^2 Cu
HsLsD-8 cm^2 Cu
HsLsD-4 cm^2 Cu

10

°C/W

1

HsLsD-footprin t

0.1

0.001 0.01 0.1 1 10 100 1000tim e (sec)

Figure 21. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse

ZTH -LSD @ cu area

100

LSD-16 cm^2 Cu
LSD-8 cm ^2 Cu
LSD-4 cm ^2 Cu
LSD-footprint
LsLsD-16 cm^2 Cu
LsLsD-8 cm^2 Cu

1

LsLsD-4 cm^2 Cu
LsLsD-footprint

Z

ls

Z

lsls

10

°C/W

0.1

0.001 0.01 0.1 1 10 100 1000

28/37 Doc ID 15701 Rev 8

ti me ( sec)

VNH5019A-E Package and PCB thermal data

Figure 22. Thermal fitting model of an H-bridge in MultiPowerSO-30

Table 18. Thermal parameters

(1)

Area/island (cm2) Footprint 4 8 16

R1 = R7 (°C/W) 0.1

R2 = R8 (°C/W) 0.3

R3 = R10 = R16 (°C/W) 0.5

R4 (°C/W) 6

R5 (°C/W) 30 24 24 24

R6 (°C/W) 56 52 42 32

R9 = R15 (°C/W) 0.05

R11 = R17 (°C/W) 0.7

R12 = R18 (°C/W) 10

R13 = R19 (°C/W) 36 26 26 26

R14 = R20 (°C/W) 56 42 36 28

R21 = R22 (°C/W) 35 25 25 25

R23 (°C/W) 160 150 150 150

C1 = C7 = C9 = C15 (W.s/°C) 0.005

C2 = C8 (W.s/°C) 0.01

C3 (W.s/°C) 0.03

C4 (W.s/°C) 0.4

C5 (W.s/°C) 1.5 2 2 2

C6 (W.s/°C) 3 4 5 6

C10 = C16 (W.s/°C) 0.015

C11 = C17 (W.s/°C) 0.05

C12 = C18 (W.s/°C) 0.3

C13 = C19 (W.s/°C) 1.2 2 2 2

C14 = C20 (W.s/°C) 2.5 3 4 5

C21 = C22 = C23 (W.s/°C) 0.01 0.008 0.008 0.008

1. The blank space means that the value is the same as the previous one.

Doc ID 15701 Rev 8 29/37

Package and packing information VNH5019A-E

4 Package and packing information

4.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:
ECOPACK

®

is an ST trademark.

4.2 MultiPowerSO-30 mechanical data

Figure 23. MultiPowerSO-30 package dimensions

N

A2

B

h x 45°

30

e

A

www.st.com

0.35
S

L

BOTTOM VIEW

F1 F1

.

A3

F2

E1

1

C

D

E

F2

F3

30/37 Doc ID 15701 Rev 8

VNH5019A-E Package and packing information

Table 19. MultiPowerSO-30 mechanical data

Data book mm

Symbol

Min. Typ. Max.

A 2.35

A2 1.85 2.25

A3 0 0.1

B0.42 0.58

C0.23 0.32

D 17.1 17.2 17.3

E 18.85 19.15

E1 15.9 16 16.1

e1

F1 5.55 6.05

F2 4.6 5.1

F3 9.6 10.1

L 0.8 1.15

N 10°

S0° 7°

Doc ID 15701 Rev 8 31/37

Package and packing information VNH5019A-E

4.3 MultiPowerSO-30 suggested land pattern

Figure 24. MultiPowerSO-30 suggested pad layout

32/37 Doc ID 15701 Rev 8

VNH5019A-E Package and packing information

4.4 MultiPowerSO-30 packing information

The devices can be packed in tube or tape and reel shipments (see

summary

for packaging quantities).

Table 20: Device

Figure 25. MultiPowerSO-30 tube shipment (no suffix)

Dimension mm

A

C

B

Base q.ty 29
Bulk q.ty 435
Tube length (± 0.5) 532
A3.82
B23.6
C (± 0.13) 0.8

Figure 26. MultiPowerSO-30 tape and reel shipment (suffix “TR”)

Reel dimensions

SO-28 tube shipment (no suffix)

Dimension mm

Base q.ty 1000
Bulk q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
D (min) 20.2
G (+ 2 / -0) 32
N (min) 100
T (max) 38.4

Tape dimensions

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986

Description Dimension mm

Tape width W 32
Tape hole spacing P0 (± 0.1) 4
Component spacing P 24
Hole diameter D (± 0.1/-0) 1.5
Hole diameter D1 (min) 2
Hole position F (± 0.1) 14.2
Compartment Depth K (max) 2.2
Hole Spacing P1 (± 0.1) 2

End

To p

cover

tape

500 mm min

No componentsNo components Components

Empty components pockets

User direct ion of feed

500 mm min

Start

Doc ID 15701 Rev 8 33/37

Order codes VNH5019A-E

5 Order codes

Table 20. Device summary

Order codes

Package

Tube Tape and reel

MultiPowerSO-30 VNH5019A-E VNH5019TR-E

34/37 Doc ID 15701 Rev 8

VNH5019A-E Revision history

6 Revision history

Table 21. Document revision history

Date Revision Changes

22-Jan-2008 1 Initial release.

Uploaded corporate template by using V3 version
Added

Table 5: Thermal data

Section 2.1: Absolute maximum ratings

– Added text

Table 6: Power section

–IS: added max value for INA = INB = PWM = 0; Tj = 25 °C;

=13V in Test conditions, deleted INA = INB = PWM = 0

V

CC

–Vf: changed Test conditions, changed typ/max value
–I

04-Nov-2009 2

: deleted and copied in

RM

R

= 0.87 W, Tj = 25 °C)

LOAD

Table 8: Switching (VCC = 13 V, R

–t

: changed min/typ/max value

DEL

–Copied I
Updated

row by

RM

Table 6: Power section

Table 10: Current sense (8 V < V

Table 11: Charge pump

–VCP: changed min/max value for ENX = 5 V, changed typ

value for EN
Updated
Updated
Added

Chapter 4

= 5 V, VCC = 4.5 V

X

Figure 11: Waveforms in full bridge operation (part 1)
Figure 12: Waveforms in full bridge operation (part 2)

Table 8: Switching (VCC = 13 V,

whole row

= 0.87 W, Tj = 25 °C)

LOAD

< 21 V)

CC

Updated following tables:

Table 6: Power section

–
–

Table 9: Protection and diagnostic

16-Dec-2009 3

–

Table 10: Current sense (8 V < V

Added

Figure 6: Behavior in fault condition (how a fault can be

CC

< 21 V)

cleared)

Added

Chapter 3: Package and PCB thermal data

06-Apr-2010 4

Updated

Table 6: Power section

–I

Table 5: Thermal data

:

: updated test condition and max value

S

Updated table notes on

Table 10: Current sense (8 V < V

.

Table 9: Protection and diagnostic

< 21 V)

CC

:

.

–dK0/k0, dK1/k1, dK3/k3: updated minimum end maximum

values.

19-Apr-2010 5 Updated

25-May-2010 6

Updated
Updated

Table 10: Current sense (8 V < V

Features
Table 6: Power section

list.

.

CC

< 21 V)

.

Doc ID 15701 Rev 8 35/37

Revision history VNH5019A-E

Table 21. Document revision history (continued)

Date Revision Changes

02-Sep-2010 7 Updated

Updated
Added

Table 1: Suggested connections for unused and not

connected pins

Updated

Table 8: Switching (V

–T
–T

, TTR, T

TSD

TSD_LS

22-Dec-2011 8

Updated

OUTA)

Updated
and

Figure 12: Waveforms in full bridge operation (part 2)

Table 5: Thermal data

.

Figure 1: Block diagram

Table 3: Block descriptions

: added note

HYST

= 13 V, R

CC

= 0.87 W, Tj = 25 °C)

LOAD

:

: added row

Table 13: Truth table in fault conditions (detected on

Figure 11: Waveforms in full bridge operation (part 1)

36/37 Doc ID 15701 Rev 8

VNH5019A-E

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2011 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

Doc ID 15701 Rev 8 37/37