Datasheet VNI4140K Datasheet (ST)

Page 1
Quad high-side smart power solid-state relay
Features
Typ e V
VNI4140K VCC-41 V 0.08 Ω 0.7 A 41 V
1. Per channel.
■ Output current: 0.7 A per channel
■ Junction overtemperature protection
■ Case overtemperature protection for thermal
demag
(1)
R
independence of the channels
■ Thermal case shutdown restart not
simultaneous for the various channels
■ Protection against loss of ground
■ Current limitation
■ Undervoltage shutdown
■ Open drain diagnostic outputs
■ 3.3 V CMOS/TTL compatible inputs
■ Fast demagnetization of inductive loads
■ Conforms to IEC 61131-2
■ ESD according to IEC 61000-4-2 up to +/-
25 kV

Figure 1. Block diagram

DS(on)
(1)
I
out
(1)
V
CC
VNI4140K
Datasheet − production data
PowerSSO-24
Description
The VNI4140K is a monolithic device made using STMicroelectronics VIPower technology, intended for driving four independent resistive or inductive loads with one side connected to ground. Active current limitation avoids dropping the system power supply in case of shorted load. Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In overload condition, channel turns OFF and back ON automatically so as to maintain junction temperature between T condition makes case temperature reach T overloaded channel is turned OFF and will restartonly when case temperature has decreased down to T channel in overload, re-start of the overloaded channels will not be simultaneous, in order to avoid high peak current from the supply. Non overloaded channels continue to operate normally. The open drain diagnostics outputs indicates overtemperature conditions.
and TR. If this
TSD
. In case of more than one
CR
CSD
,
March 2012 Doc ID 14174 Rev 10 1/25
This is information on a product in full production.
www.st.com
25
Page 2
Contents VNI1440K
Contents
1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1 VNI4140K thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9 Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25 Doc ID 14174 Rev 10
Page 3
VNI1440K Pin connection

1 Pin connection

Figure 2. Pin connection (top view)

V
CC
IN1
STAT1
IN2
STAT2
GND
STAT3
IN3
STAT4
IN4 NC NC

Table 1. Pin description

Pin Name Description
Tab TAB Exposed tab internally connected to Vcc
1 Vcc Supply voltage
2 IN1 Channel 1 input 3.3 V CMOS/TTL compatible
OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT3
OUT3 OUT3 OUT4 OUT4 OUT4
3 STAT1 Channel 1 status in open drain configuration
4 IN2 Channel 2 input 3.3 V CMOS/TTL compatible
5 STA2 Channel 2 status in open drain configuration
6 GND Device ground connection
7 STAT3 Channel 3 status in open drain configuration
8 IN3 Channel 3 input 3.3 V CMOS/TTL compatible
9 STAT4 Channel 4 status in open drain configuration
10 IN4 Channel 4 input 3.3 V CMOS/TTL compatible
11 NC
12 NC
13 OUT4 Channel 4 power stage output, internally protected
14 OUT4 Channel 4 power stage output, internally protected
15 OUT4 Channel 4 power stage output, internally protected
16 OUT3 Channel 3 power stage output, internally protected
17 OUT3 Channel 3 power stage output, internally protected
Doc ID 14174 Rev 10 3/25
Page 4
Pin connection VNI1440K
Table 1. Pin description (continued)
Pin Name Description
18 OUT3 Channel 3 power stage output, internally protected
19 OUT2 Channel 2 power stage output, internally protected
20 OUT2 Channel 2 power stage output, internally protected
21 OUT2 Channel 2 power stage output, internally protected
22 OUT1 Channel 1 power stage output, internally protected
23 OUT1 Channel 1 power stage output, internally protected
24 OUT1 Channel 1 power stage output, internally protected
4/25 Doc ID 14174 Rev 10
Page 5
VNI1440K Maximum ratings

2 Maximum ratings

Table 2. Absolute maximum rating

Symbol Parameter Value Unit
V
-V
I
I
V
I
V
E
P
T
GND
OUT
V
STAT
Power supply voltage 41 V
CC
Reverse supply voltage -0.3 V
CC
DC ground reverse current -250 mA
Output current (continuos) Internally limited A
I
Reverse output current (per channel) -5 A
R
I
Input current (per channel) ± 10 mA
IN
Input voltage +V
IN
Status pin voltage +V
STAT
Status pin current ± 10 mA
Electrostatic discharge (R = 1.5 kΩ; C = 100 pF) 2000 V
ESD
Single pulse avalanche energy per channel not
AS
simultaneously
Power dissipation at Tc = 25 °C Internally limited W
TOT
T
Junction operating temperature Internally limited °C
J
Storage temperature -55 to 150 °C
STG

2.1 Thermal data

CC
CC
V
V
300 mJ

Table 3. Thermal data

Symbol Parameter Value Unit
R
th(JC)
R
th(JA)
1. Per channel
Thermal resistance junction-case
Thermal resistance junction-ambient Max see Figure 11 °C/W
Doc ID 14174 Rev 10 5/25
(1)
Max 2 °C/W
Page 6
Electrical characteristics VNI1440K

3 Electrical characteristics

10.5 V < VCC < 36 V; -25 °C < TJ < 125 °C; unless otherwise specified

Table 4. Power section

Symbol Parameter Test condition Min Typ Max Unit
Vcc Supply voltage 10.5 36 V
I
R
DS(on)
V
clamp
I
S
I
LGND
V
OUT(OFF)
On-state resistance
Supply current
Output current at turn­off
Off state output voltage
= 0.5 A at TJ = 25 °C
OUT
I
= 0.5 A
OUT
Is = 20 mA 41 45 52 V
All channel in OFF state ON state with V
= 125 °C)
(T
J
VCC = V V
V
STAT
= 24 V, V
GND
= 0 V and I
IN
= 5 V
IN
= VIN =
= 0 V
OUT
= 0 A 1 V
OUT
250
2.4 4
0.080
0.140ΩΩ
µA
mA
1mA
CP
Off state output current
Charge pump frequency
V
IN
= V
= 0 V 0 5 µA
OUT
Channel in ON state
(1)
1450 kHz
I
OUT(OFF)
F
1. To cover EN55022 class A and class B normative.
= 24 V; -25 °C < TJ < 125 °C, RL = 48 Ω, input rise time < 0.1 µs
V
CC

Table 5. Switching

Symbol Parameter Min Typ Max Unit
t
d
t
d
(OFF)
dV/dt
dV/dt
(ON)
Turn on delay - 20 - µs
t
Rise time - 10 - µs
r
Turn off - 30 - µs
t
Fall time - 8 - µs
f
Turn on voltage slope - 3 - V/µs
(ON)
(off) Turn off voltage slope - 4 - V/µs
6/25 Doc ID 14174 Rev 10
Page 7
VNI1440K Electrical characteristics

Table 6. Logical input

Symbol Parameter Test condition Min Typ Max Unit
V
V
V
I(HYST)
I
Input low level voltage 0.8 V
IL
Input high level voltage 2.20 V
IH
Input hysteresis voltage
Input current
IN
V
= 15 V 10
IN
= 36 V 210
V
IN
0.15 V

Table 7. Protection and diagnostic

Symbol Parameter Test condition Min Typ Max Unit
v
STAT
V
USD
V
USDHYS
I
LIM
I
PEAK
Status voltage output low
Undervoltage protection
Undervoltage hysteresis
DC short-circuit current
Maximum DC output current
= 1.6 mA 0.6 V
I
STAT
710.5V
0.4 0.5 V
V
CC
= 24 V; R
< 10 mΩ 0.7 1 1.7 A
LOAD
Dynamic load 1.3 A
µΑ
Hyst Tracking limits 0.2 A
I
LSTAT
T
T
T
HIST
T
CSD
T
T
CHYST
V
demag
TSD
Status leakage current VCC = V
Junction shutdown temperature
Junction reset
R
temperature
Junction thermal hysteresis
Case shutdown temperature
Case reset
CR
temperature
Case thermal hysteresis
Output voltage at turn-OFF
I
OUT
= 36 V 30 µΑ
STAT
= 0.5 A; L
LOAD
>= 1 mH
150 170 190 °C
135 °C
715 °C
125 130 135 °C
110 °C
715 °C
-41VCC-45VCC-
V
CC
52
V
Doc ID 14174 Rev 10 7/25
Page 8
Electrical characteristics VNI1440K

Figure 3. Current and voltage conventions

8/25 Doc ID 14174 Rev 10
Page 9
VNI1440K Truth table

4 Truth table

Table 8 . Tr u th t a ble
Condition INPUTn OUTPUTn STATUSn
Normal operation
Overtemperature
Undervoltage
Shorted load
(Current limitation)
L
H
L
H
L
H
L
H

5 Typical application circuit

Figure 4. Typical application circuit

L
H
L L
L L
L
X
H H
H L
X X
H H
Doc ID 14174 Rev 10 9/25
Page 10
Typical application circuit VNI1440K

Figure 5. Thermal behavior

Vi n( i ) = H
OUT(i) On
STAT(i) Off (H)
1)
NO
Tj ( i ) > Tt s d
YES
4)
Tc > Tc r
YES
OUT(i) Off
STAT(i) On (L)
Tc > Tc s d
NO
NO
NOYES
2)
YES
Tj(i) > Tjr
10/25 Doc ID 14174 Rev 10
3)
Page 11
VNI1440K Switching waveforms

6 Switching waveforms

Figure 6. Switching waveforms

Doc ID 14174 Rev 10 11/25
Page 12
Pin functions VNI1440K

7 Pin functions

Figure 7. Input circuit

Figure 8. Status circuit

12/25 Doc ID 14174 Rev 10
Page 13
VNI1440K Pin functions

Figure 9. Charge pump switching frequency (typical) vs temperature

Freq_CP
2000
1800
1600
1400
1200
CP_frequency (KHz)
1000
800
-50 0 50 100 150 200
temperature("C)
Freq_CP
Doc ID 14174 Rev 10 13/25
Page 14
Package and PC board thermal data VNI1440K

8 Package and PC board thermal data

8.1 VNI4140K thermal data

Figure 10. VNI4140K PC board

Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias,
FR4 area = 77 mm x 86 mm, PCB thickness=1.6 mm, Cu thickness = 70 mm (front and back side), Copper areas: from minimum pad lay-out to 8 cm
Figure 11. R
vs PCB copper area in open box free air condition (one channel ON)
thJA
2
).
14/25 Doc ID 14174 Rev 10
Page 15
VNI1440K Package and PC board thermal data
Figure 12. VNI4140K thermal impedance junction ambient single pulse
(one channel on)
Doc ID 14174 Rev 10 15/25
Page 16
Reverse polarity protection VNI1440K

9 Reverse polarity protection

This schematic can be used with any type of load.
The following is an indication on how to dimension the R
R
= (-VCC) / (-I
GND
where -I maximum rating section of the device datasheet.
Power dissipation in R
PD = (-V
Note: In normal condition (no reverse polarity) due to the diode there will be a voltage drop
between GND of the device and GND of the system.

Figure 13. Reverse polarity protection

is the DC reverse ground pin current and can be found in the absolute
GND
)2/R
CC
GND
GND
)
(when VCC < 0: during reverse polarity situations) is:
GND
+ Vcc
+ Vcc
Input
Input
i
i
Output
Output
Status
Status
i
i
GND
GND
GND
resistor.
i
i
Load
Load
R
R
GND
GND
16/25 Doc ID 14174 Rev 10
Diode
Diode
Page 17
VNI1440K Package mechanical data

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Doc ID 14174 Rev 10 17/25
Page 18
Package mechanical data VNI1440K

Table 9. PowerSSO-24 mechanical data

mm
Symbol
Min. Typ. Max.
A 2.15 2.47
A2 2.15 2.40
a1 0 0.075
b 0.33 0.51
c 0.23 0.32
D 10.10 10.50
E 7.4 7.6
e 0.8
e3 8.8
G 0.1
G1 0.06
H 10.1 10.5
h 0.4
L 0.55 0.85
N 10deg
X 4.1 4.7
Y 6.5 7.1

Figure 14. PowerSSO-24 package dimensions

18/25 Doc ID 14174 Rev 10
Page 19
VNI1440K Package mechanical data

Figure 15. PowerSSO-24 tube shipment (no suffix)

Table 10. PowerSSO-24 tube shipment

Base quantity 49
Bulk quantity 1225
Tube length (± 0.5) 532
A 3.5
B 13.8
C (± 0.1) 0.6
Note: All dimensions are in mm.
Doc ID 14174 Rev 10 19/25
Page 20
Package mechanical data VNI1440K

Figure 16. PowerSSO-24 reel shipment (suffix “TR”)

Table 11. PowerSSO-24 reel dimensions

Base quantity 1000
Bulk quantity 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (2 ± 0) 24.4
N (min) 100
T (max) 30.4
20/25 Doc ID 14174 Rev 10
Page 21
VNI1440K Package mechanical data

Figure 17. PowerSSO-24™ tape dimensions

Table 12. PowerSSO-24™ tape dimensions

Tape width W 24
Tape hole spacing P0 (± 0.1) 4
Component spacing P 12
Hole diameter D (± 0.05) 1.55
Hole diameter D1 (min) 1.5
Hole position F (± 0.1) 11.5
Compartment depth K (max) 2.85
Hole spacing P1 (± 0.1) 2
Note: According to electronic industries association (EIA) Standard 481 rev. A, Feb 1986
Doc ID 14174 Rev 10 21/25
Page 22
Package mechanical data VNI1440K

Figure 18. VN14140k suggested footprint

  
 n 






2



3OLDER-ASK/PENING
Note: STMicroelectronics is not responsible for any PCB related issues. The footprint shown in the
above figure is a suggestion which might not be in line to the customer PCB supplier design rules.
All dimensions are in mm.
22/25 Doc ID 14174 Rev 10
Page 23
VNI1440K Order codes

11 Order codes

Table 13. Order codes

Order codes Package Packaging
VNI4140K PowerSSO-24 Tube
VNI4140KTR PowerSSO-24 Tape and reel
Doc ID 14174 Rev 10 23/25
Page 24
Revision history VNI1440K

12 Revision history

Table 14. Document revision history
Date Revision Changes
16-Nov-2007 1 Initial release
26-Nov-2007 2 Updated electrical parameters values
08-Jul-2008 3
08-Apr-2008 4 Added I
27-Aug-2009 5 Updated Section 9: Reverse polarity protection
09-Dec-2009 6
15-Apr-2010 7 Updated Table 5 on page 6
06-Feb-2012 8
05-Mar-2012 9
19-Mar-2012 10 Minor text changes.
Inserted: Figure 4 on page 9 and Section 9: Reverse
polarity protection on page 16
parameter in Table 4 on page 6
LGND
Added Section 10: Conformity to IEC 61000-4-2 ESD
immunity test
Inserted feature: Conformity to IEC 61000-4-2 ESD immunity test in cover page.
Removed chapter: Conformity to IEC 61000-4-2 ESD immunity test.
Suggested footprint inserted. In Table 4. parameter I
has been added.
LGND
24/25 Doc ID 14174 Rev 10
Page 25
VNI1440K
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Doc ID 14174 Rev 10 25/25
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