The VNI4140K is a monolithic device made using
STMicroelectronics VIPower technology, intended
for driving four independent resistive or inductive
loads with one side connected to ground. Active
current limitation avoids dropping the system
power supply in case of shorted load. Built-in
thermal shutdown protects the chip from
overtemperature and short-circuit. In overload
condition, channel turns OFF and back ON
automatically so as to maintain junction
temperature between T
condition makes case temperature reach T
overloaded channel is turned OFF and will
restartonly when case temperature has
decreased down to T
channel in overload, re-start of the overloaded
channels will not be simultaneous, in order to
avoid high peak current from the supply. Non
overloaded channels continue to operate
normally. The open drain diagnostics outputs
indicates overtemperature conditions.
and TR. If this
TSD
. In case of more than one
CR
CSD
,
March 2012Doc ID 14174 Rev 101/25
This is information on a product in full production.
10.5 V < VCC < 36 V; -25 °C < TJ < 125 °C; unless otherwise specified
Table 4.Power section
SymbolParameterTest conditionMinTypMaxUnit
VccSupply voltage10.536V
I
R
DS(on)
V
clamp
I
S
I
LGND
V
OUT(OFF)
On-state resistance
Supply current
Output current at turnoff
Off state output
voltage
= 0.5 A at TJ = 25 °C
OUT
I
= 0.5 A
OUT
Is = 20 mA414552V
All channel in OFF state
ON state with V
= 125 °C)
(T
J
VCC = V
V
V
STAT
= 24 V, V
GND
= 0 V and I
IN
= 5 V
IN
= VIN =
= 0 V
OUT
= 0 A1V
OUT
250
2.44
0.080
0.140ΩΩ
µA
mA
1mA
CP
Off state output
current
Charge pump
frequency
V
IN
= V
= 0 V05µA
OUT
Channel in ON state
(1)
1450kHz
I
OUT(OFF)
F
1. To cover EN55022 class A and class B normative.
= 24 V; -25 °C < TJ < 125 °C, RL = 48 Ω, input rise time < 0.1 µs
V
CC
Table 5.Switching
SymbolParameterMinTypMaxUnit
t
d
t
d
(OFF)
dV/dt
dV/dt
(ON)
Turn on delay -20-µs
t
Rise time -10-µs
r
Turn off -30-µs
t
Fall time -8-µs
f
Turn on voltage slope-3-V/µs
(ON)
(off) Turn off voltage slope-4-V/µs
6/25Doc ID 14174 Rev 10
Page 7
VNI1440KElectrical characteristics
Table 6.Logical input
SymbolParameterTest conditionMinTypMaxUnit
V
V
V
I(HYST)
I
Input low level voltage0.8V
IL
Input high level voltage 2.20V
IH
Input hysteresis
voltage
Input current
IN
V
= 15 V10
IN
= 36 V210
V
IN
0.15V
Table 7.Protection and diagnostic
SymbolParameterTest conditionMinTypMaxUnit
v
STAT
V
USD
V
USDHYS
I
LIM
I
PEAK
Status voltage
output low
Undervoltage
protection
Undervoltage
hysteresis
DC short-circuit
current
Maximum DC output
current
= 1.6 mA 0.6V
I
STAT
710.5V
0.40.5V
V
CC
= 24 V; R
< 10 mΩ0.711.7A
LOAD
Dynamic load1.3A
µΑ
HystTracking limits0.2A
I
LSTAT
T
T
T
HIST
T
CSD
T
T
CHYST
V
demag
TSD
Status leakage current VCC = V
Junction shutdown
temperature
Junction reset
R
temperature
Junction thermal
hysteresis
Case shutdown
temperature
Case reset
CR
temperature
Case thermal
hysteresis
Output voltage at
turn-OFF
I
OUT
= 36 V 30µΑ
STAT
= 0.5 A; L
LOAD
>= 1 mH
150170190°C
135°C
715°C
125130135°C
110°C
715°C
-41VCC-45VCC-
V
CC
52
V
Doc ID 14174 Rev 107/25
Page 8
Electrical characteristicsVNI1440K
Figure 3.Current and voltage conventions
8/25Doc ID 14174 Rev 10
Page 9
VNI1440KTruth table
4 Truth table
Table 8 .Tr u th t a ble
ConditionINPUTnOUTPUTnSTATUSn
Normal operation
Overtemperature
Undervoltage
Shorted load
(Current limitation)
L
H
L
H
L
H
L
H
5 Typical application circuit
Figure 4.Typical application circuit
L
H
L
L
L
L
L
X
H
H
H
L
X
X
H
H
Doc ID 14174 Rev 109/25
Page 10
Typical application circuitVNI1440K
Figure 5.Thermal behavior
Vi n( i ) = H
OUT(i) On
STAT(i) Off (H)
1)
NO
Tj ( i ) > Tt s d
YES
4)
Tc > Tc r
YES
OUT(i) Off
STAT(i) On (L)
Tc > Tc s d
NO
NO
NOYES
2)
YES
Tj(i) > Tjr
10/25Doc ID 14174 Rev 10
3)
Page 11
VNI1440KSwitching waveforms
6 Switching waveforms
Figure 6.Switching waveforms
Doc ID 14174 Rev 1011/25
Page 12
Pin functionsVNI1440K
7 Pin functions
Figure 7.Input circuit
Figure 8.Status circuit
12/25Doc ID 14174 Rev 10
Page 13
VNI1440KPin functions
Figure 9.Charge pump switching frequency (typical) vs temperature
Freq_CP
2000
1800
1600
1400
1200
CP_frequency (KHz)
1000
800
-50050100150200
temperature("C)
Freq_CP
Doc ID 14174 Rev 1013/25
Page 14
Package and PC board thermal dataVNI1440K
8 Package and PC board thermal data
8.1 VNI4140K thermal data
Figure 10. VNI4140K PC board
Note:Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias,
FR4 area = 77 mm x 86 mm, PCB thickness=1.6 mm, Cu thickness = 70 mm (front and back
side), Copper areas: from minimum pad lay-out to 8 cm
Figure 11. R
vs PCB copper area in open box free air condition (one channel ON)
thJA
2
).
14/25Doc ID 14174 Rev 10
Page 15
VNI1440KPackage and PC board thermal data
Figure 12. VNI4140K thermal impedance junction ambient single pulse
(one channel on)
Doc ID 14174 Rev 1015/25
Page 16
Reverse polarity protectionVNI1440K
9 Reverse polarity protection
This schematic can be used with any type of load.
The following is an indication on how to dimension the R
R
= (-VCC) / (-I
GND
where -I
maximum rating section of the device datasheet.
Power dissipation in R
PD = (-V
Note:In normal condition (no reverse polarity) due to the diode there will be a voltage drop
between GND of the device and GND of the system.
Figure 13. Reverse polarity protection
is the DC reverse ground pin current and can be found in the absolute
GND
)2/R
CC
GND
GND
)
(when VCC < 0: during reverse polarity situations) is:
GND
+ Vcc
+ Vcc
Input
Input
i
i
Output
Output
Status
Status
i
i
GND
GND
GND
resistor.
i
i
Load
Load
R
R
GND
GND
16/25Doc ID 14174 Rev 10
Diode
Diode
Page 17
VNI1440KPackage mechanical data
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
Inserted: Figure 4 on page 9 and Section 9: Reverse
polarity protection on page 16
parameter in Table 4 on page 6
LGND
Added Section 10: Conformity to IEC 61000-4-2 ESD
immunity test
Inserted feature: Conformity to IEC 61000-4-2 ESD
immunity test in cover page.
Removed chapter: Conformity to IEC 61000-4-2 ESD
immunity test.
Suggested footprint inserted.
In Table 4. parameter I
has been added.
LGND
24/25Doc ID 14174 Rev 10
Page 25
VNI1440K
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