Datasheet VND810PEP-E Datasheet (ST)

Features

Type R

VND810PEP-E 160mW

DS(on)

(1)

I

OUT

3.5A

(1)

V

CC

36V

VND810PEP-E

Double channel high-side driver

1. Per each channel.

■ CMOS compatible inputs

■ Open drain status outputs

■ On-state open-load detection

■ Off-state open-load detection

■ Shorted load protection

■ Undervoltage and overvoltage shutdown

■ Loss of ground protection

■ Very low standby current

■ Reverse battery protection

■ In compliance with the 2002/95/EC european

directive

Table 1. Device summary

PowerSSO-12

Description

The VND810PEP-E is a monolithic device made
using| STMicroelectronics
Technology. The VND810PEP-E is intended for
driving any type of multiple load with one side
connected to ground.

The active V

pin voltage clamp protects the

CC

device against low energy spikes (see ISO7637
transient compatibility table).

Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects the
open-load condition in both the on and off-state.

In the off-state the device detects if the output is
shorted to V

. The device automatically turns off

CC

in the case where the ground pin becomes
disconnected.

®

VIPower™ M0-3

Order codes

Package

Tub e Tap e and r eel

PowerSSO-12 VND810PEP-E VND810PEPTR-E

November 2011 Doc ID 10858 Rev 5 1/25

www.st.com

1

Contents VND810PEP-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 14

3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 14

3.1.2 Solution 2: a diode (D

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

) in the ground line . . . . . . . . . . . . . . . . . . . . 15

GND

3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/25 Doc ID 10858 Rev 5

VND810PEP-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Power outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. V
Table 8. Switching (V

Table 9. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 10. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 11. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 12. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 13. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 14. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 15. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 16. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 17. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 18. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

= 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

Doc ID 10858 Rev 5 3/25

List of figures VND810PEP-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 17

Figure 11. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 18

Figure 12. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 18

Figure 13. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 15. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4/25 Doc ID 10858 Rev 5

VND810PEP-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

V

cc

V

GND

INPUT1

STATUS1

INPUT2

STATUS2

cc

CLAMP

OVERTEMP. 1

OVERTEMP. 2

LOGIC

OVERVOLTAGE

UNDERVOLTAGE

CLAMP 1

DRIVER 1

CURRENT LIMITER 1

OPEN-LOAD ON 1

OPEN-LOAD OFF 1

CLAMP 2

DRIVER 2

CURRENT LIMITER 2

OPEN-LOAD ON 2

OPEN-LOAD OFF 2

OUTPUT1

OUTPUT2

Figure 2. Configuration diagram (top view)

GND
NC

INPUT1
STATUS1
STATUS2
INPUT2

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status Not connected Output Input

Floating X X X X

To ground X

1
2
3
4
5
6

12
11
10

9
8
7

V

cc

OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
V

cc

TAB = V

cc

Through 10KΩ

resistor

Doc ID 10858 Rev 5 5/24

Electrical specifications VND810PEP-E

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Table 3: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document available on www.st.com.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

- V

- I

I

- I

I

V

T

CC

CC

GND

OUT

OUT

I

IN

STAT

ESD

P

tot

T

T

c

stg

DC supply voltage 41 V

Reverse DC supply voltage - 0.3 V

DC reverse ground pin current - 200 mA

DC output current Internally limited A

Reverse DC output current - 6 A

DC input current +/- 10 mA

DC Status current +/- 10 mA

Electrostatic discharge (human body model: R=1.5KΩ;
C = 100pF)

- INPUT

- STATUS

- OUTPUT

- V

CC

4000
4000
5000
5000

Power dissipation (per island) at TC = 25°C 54 W

Junction operating temperature Internally limited °C

j

Case operating temperature - 40 to 150 °C

Storage temperature - 55 to 150 °C

V
V
V
V

6/24 Doc ID 10858 Rev 5

VND810PEP-E Electrical specifications

2.2 Thermal data

Table 4. Thermal data (per island)

Symbol Parameter Maximum value Unit

R

thj-case

R

thj-amb

1. When mounted on a standard single-sided FR-4 board with 1cm2 of Cu (at least 35 µm thick) connected to
all V

2. When mounted on a standard single-sided FR-4 board with 8cm2 of Cu (at least 35 µm thick) connected to
all V

Thermal resistance junction-case 2.3 °C/W

Thermal resistance junction-ambient
(one chip ON)

pins.

CC

pins.

CC

2.3 Electrical characteristics

Values specified in this section are for 8V < V
otherwise stated.

Figure 3. Current and voltage conventions

I

INn

V

INn

V

STATn

I

STATn

INPUTn

STATUSn

(1)

61

< 36V; -40°C < Tj < 150°C, unless

CC

V

(*)

F1

V

CC

I

OUTn

OUTPUTn

V

GND

50

OUTn

(2)

°C/W

I

S

V

CC

Note: V

Fn

= V

CCn

- V

during reverse battery condition.

OUTn

Doc ID 10858 Rev 5 7/24

I

GND

Electrical specifications VND810PEP-E

Table 5. Power outputs

Symbol Parameter Test conditions Min Typ Max Unit

V

CC

V

USD

V

OV

R

ON

I

S

I

L(off1)

I

L(off2)

I

L(off3)

I

L(off4)

Operating supply
voltage

5.5 13 36 V

Undervoltage shutdown 3 4 5.5 V

Overvoltage shutdown 36 V

12

12

5

160
320mΩmΩ

40

µA

25

µA

7

mA

5µA

3µA

On-state resistance

Supply current

Off-state output current V

Off-state output current V

Off-state output current

Off-state output current

I

= 1A; Tj = 25°C

OUT

= 1A; V

I

OUT

Off-state; V

= V

V

IN

OUT

Off-state; V

= V

V

IN

OUT

Tj = 25°C

On-state; V

= 0A

I

OUT

= V

IN

OUT

= 0V; V

IN

V

= V

IN

OUT

Tj = 125°C

V

= V

IN

OUT

Tj = 25°C

> 8V

CC

= 13V;

CC

= 0V

= 13V;

CC

= 0V;

= 13V; V

CC

IN

= 5V;

= 0V 0 50 µA

= 3.5V -75 0 µA

OUT

= 0V; V

= 0V; V

CC

CC

= 13V;

= 13V;

Table 6. Protections and diagnostics

Symbol Parameter Test conditions Min. Typ. Max. Unit

T

T

t

SDL

I

V

demag

Shutdown temperature 150 175 200 °C

TSD

T

Reset temperature 135 °C

R

Thermal hysteresis 7 15 °C

hyst

Status delay in overload
conditions

Current limitation

lim

Turn-off output clamp
voltage

T

j

V

CC

5.5V < V

I

= 1A; L = 6mH

OUT

> T

= 13V

CC

TSD

< 36V

3.5 5 7.5

V

-41V

CC

CC

-48V

20 µs

7.5AA

-

CC

55

V

Note: To ensure long term reliability under heavy overload or short circuit conditions, protection

and related diagnostic signals must be used together with a proper software strategy. If the
device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles.

8/24 Doc ID 10858 Rev 5

VND810PEP-E Electrical specifications

Tabl e 7. VCC - output diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

F

Table 8. Switching (V

Forward on voltage - I

= 13V; Tj = 25°C)

CC

= 0.5A; Tj = 150°C 0.6 V

OUT

Symbol Parameter Test conditions Min. Typ. Max. Unit

R

= 13Ω from VIN rising edge

t

d(on)

t

d(off)

Turn-on delay time

Turn-off delay time

L

to V

R
to V

= 1.3V (see Figure 5)

OUT

= 13Ω from VIN falling edge

L

= 11.7V

OUT

30 µs

30 µs

(see Figure 5)

dV

/dt

OUT

dV

/dt

OUT

Table 9. Logic inputs

Turn-on voltage slope

(on)

Turn-off voltage slope

(off)

= 13Ω from V

L

V

= 10.4V (see Figure 5)

OUT

= 13Ω from V

R

L

to V

= 1.3V (see Figure 5)

OUT

OUT

OUT

= 1.3V to

= 11.7V

R

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

I

V

I

I(hyst)

Input low level 1.25 V

IL

Low level input current V

IL

Input high level 3.25 V

IH

High level input current V

IH

= 1.25V 1 µA

IN

= 3.25V 10 µA

IN

Input hysteresis voltage 0.5 V

I

Input clamp voltage

ICL

IN

I

IN

= 1mA

= -1mA

66.8

- 0.7

8V

V/µs

V/µs

V

Table 10. Protections and diagnostics

Symbol Parameter Test conditions Min. Typ. Max. Unit

T

T

t

SDL

I

V

demag

Shutdown temperature 150 175 200 °C

TSD

T

Reset temperature 135 °C

R

Thermal hysteresis 7 15 °C

hyst

Status delay in overload
conditions

Current limitation

lim

Turn-off output clamp
voltage

T

j

V

CC

5.5V < V

I

= 1A; L = 6mH

OUT

> T

= 13V

CC

TSD

< 36V

3.5 5 7.5

V

-41V

CC

CC

-48V

20 µs

7.5AA

-

CC

55

Doc ID 10858 Rev 5 9/24

V

Electrical specifications VND810PEP-E

Tabl e 11. Sta tus pin

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

STAT

I

LSTAT

C

STAT

V

Table 12. Open-load detection

Status low output voltage I

STAT

Status leakage current Normal operation; V

Status pin input capacitance Normal operation; V

I

Status clamp voltage

SCL

STAT

I

STAT

= 1.6mA 0.5 V

= 5V 10 µA

STAT

= 5V 100 pF

STAT

= 1mA
= - 1mA

66.8

- 0.7

8V

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

OL

t

DOL(on)

V

OL

t

DOL(off)

Open-load on-state detection threshold V

Open-load on-state detection delay I

Open-load off-state voltage detection
threshold

Open-load detection delay at turn-off 1000 µs

= 5V 20 40 80 mA

IN

= 0A 200 µs

OUT

= 0V 1.5 2.5 3.5 V

V

IN

Figure 4. Status timings

OPEN - LOAD STATUS TIMING (with external pull-up)

V

> V

OUT

V

INn

I

< I

OUT

OL

OL

OVERTEMP STATUS TIMING

V

INn

Tj > T

TSD

V

V

STATn

t

DOL(off)

t

DOL(on)

V

STATn

t

SDL

t

SDL

10/24 Doc ID 10858 Rev 5

VND810PEP-E Electrical specifications

Figure 5. Switching characteristics

V

OUTn

t

d(off)

90%

dV

OUT

/dt

(off)

t

t

/dt

dV

OUT

(on)

V

INn

Table 13. Truth table

t

d(on)

80%

10%

Conditions Input Output Status

Normal operation

Current limitation

Overtemperature

Undervoltage

Overvoltage

Output voltage > V

Output current < I

OL

OL

L

H

L
H
H

L
H

L
H

L
H

L
H

L
H

L

H

L
X
X

L

L

L

L

L

L

H
H

L
H

(T

(T

< T

j

> T

j

H
H

H

H

L

X
X

H
H

L

H

H

L

TSD

TSD

) H
) L

Doc ID 10858 Rev 5 11/24

Electrical specifications VND810PEP-E

Table 14. Electrical transient requirements (part 1)

ISO T/R

Test le vel

7637/1

Test pulse

I II III IV Delays and impedance

1 - 25V - 50V - 75V - 100V 2ms, 10Ω

2 + 25V + 50V + 75V + 100V 0.2ms, 10Ω

3a - 25V - 50V - 100V - 150V 0.1µs, 50Ω

3b + 25V + 50V + 75V + 100V 0.1µs, 50Ω

4 - 4V - 5V - 6V - 7V 100ms, 0.01Ω

5 + 26.5V + 46.5V + 66.5V + 86.5V 400ms, 2Ω

Table 15. Electrical transient requirements (part 2)

ISO T/R

7637/1

Test pulse

IIIIIIIV

Test le vel

1C C C C

2C C C C

3a C C C C

3b C C C C

4C C C C

5C E E E

Table 16. Electrical transient requirements (part 3)

Class Contents

C

E

All functions of the device are performed as designed after exposure to
disturbance.

One or more functions of the device is not performed as designed after exposure
and cannot be returned to proper operation without replacing the device.

12/24 Doc ID 10858 Rev 5

VND810PEP-E Electrical specifications

Figure 6. Waveforms

NORMAL OPERATION

INPUT

n

OUTPUT VOLTAGE

STATUS

V

INPUT

n

CC

n

OUTPUT VOLTAGE

STATUS

V

INPUT

n

CC

n

OUTPUT VOLTAGE

STATUS

n

n

n

n

V

VCC<V

UNDERVOLTAGE

USD

OVERVOLTAGE

OV

V

USDhyst

undefined

VCC>V

OV

INPUT

n

OUTPUT VOLTAGE

STATUS

INPUT

n

n

OUTPUT VOLTAGE

STATUS

T

INPUT

n

j

n

OUTPUT CURRENT

STATUS

n

OPEN-LOAD with external pull-up

V

n

V

OL

OUT>VOL

OPEN-LOAD without external pull-up

n

OVERTEMPERATURE

T

TSD

T

R

n

Doc ID 10858 Rev 5 13/24

Application information VND810PEP-E

3 Application information

Figure 7. Application schematic

+5V

+5V

μ

R

prot

C

R

prot

STATUSn

INPUTn

GND

V

CC

D

ld

OUTPUTn

R

GND

V

GND

D

GND

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: a resistor in the ground line (R

This can be used with any type of load.

The following show how to dimension the R

1. R

2. R

where - I

≤ 600mV / 2 (I

GND

≥ ( - VCC) / ( - I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

)

)

maximum rating section of the device decathlete.

Power dissipation in R

P

= (- VCC)2/ R

D

GND

GND

(when V

< 0 during reverse battery situations) is:

CC

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

GND

resistor:

GND

only)

S(on)max

becomes the sum of the

14/24 Doc ID 10858 Rev 5

VND810PEP-E Application information

Please note that, if the microprocessor ground is not shared by the device ground, then the
R

will produce a shift (I

GND

S(on)max

* R

) in the input thresholds and the status output

GND

values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R

GND

.

If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.

3.1.2 Solution 2: a diode (D

A resistor (R

= 1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift will not vary if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V

maximum DC rating. The same applies if the device is subject to transients on the VCC

CC

line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the microcontroller I/O pins from latching up.

if the device will be driving an

GND

) in line to

prot

The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:

- V

CCpeak

/ I

latchup

≤ R

prot

≤ (V

OHμC

- V

IH

- V

GND

) / I

IHmax

Example

For the following conditions:

V

CCpeak

I

latchup

V

OHμC

5kΩ ≤ R

Recommended values are:

R

prot

= - 100V

≥ 20mA

≥ 4.5V

prot

= 10kΩ

≤ 65kΩ.

Doc ID 10858 Rev 5 15/24

Application information VND810PEP-E

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (V
microprocessor.

The external resistor has to be selected according to the following requirements:

) like the +5V line used to supply the

PU

1) no false open-load indication when load is connected: in this case we have to avoid V
to be higher than V

V

OUT

= (V

/ (RL + RPU))RL < V

PU

2) no misdetection when load is disconnected: in this case the V
V

Because I
up resistor R

; this results in the following condition R

OLmax

may significantly increase if V

s(OFF)

should be connected to a supply that is switched OFF when the module is in

PU

; this results in the following condition

Olmin

Olmin.

< (V

PU

is pulled high (up to several mA), the pull-

out

PU

- V

OLmax

has to be higher than

OUT

) / I

L(off2)

.

standby.

Figure 8. Open-load detection in off-state

V batt. VPU

V

CC

R

PU

INPUT

STATUS

DRIVER

+

LOGIC

+

R

-

VOL

OUT

I

L(off2)

RL

OUT

GROUND

16/24 Doc ID 10858 Rev 5

VND810PEP-E Package and PC board thermal data

4 Package and PC board thermal data

4.1 PowerSSO-12 thermal data

Figure 9. PowerSSO-12 PC board

Note: Layout condition of R

area= 78mm x 78mm, PCB thickness = 2mm, Cu thickness =70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm

Figure 10.

RTHj_amb(°C/W )

R

thj-amb

70

65

60

55

50

45

0123456789

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

vs. PCB copper area in open box free air condition (one channel ON)

PCB Cu heatsink area (cm^2)

Doc ID 10858 Rev 5 17/24

Package and PC board thermal data VND810PEP-E

Figure 11. PowerSSO-12 thermal impedance junction ambient single pulse (one

channel ON)

ZTH (°C/ W)

100

10

1

Footprint

8 cm

2

0.1

0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Equation 1: pulse calculation formula

Z

THδ

R

TH

δ Z

THtp

1 δ–()+⋅=

where δ = tP/T

Figure 12. Thermal fitting model of a double channel HSD in PowerSSO-12

18/24 Doc ID 10858 Rev 5

VND810PEP-E Package and PC board thermal data

Table 17. Thermal parameters

Area/island (cm2)Footprint8

R1= R7 (°C/W) 0.1

R2= R3 = R8 (°C/W) 1.5

R4 (°C/W) 8

R5 (°C/W) 28 18

R6 (°C/W) 30 22

C1 = C7 (W.s/°C) 0.0001

C2 = C8 (W.s/°C) 0.0007

C3 (W.s/°C) 0.015

C4 (W.s/°C) 0.1 0.1

C5 (W.s/°C) 0.15 0.017

C6 (W.s/°C) 3 5

Doc ID 10858 Rev 5 19/24

Package and packing information VND810PEP-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

5.2 Package mechanical data

Figure 13. PowerSSO-12 package dimensions

20/24 Doc ID 10858 Rev 5

VND810PEP-E Package and packing information

Table 18. PowerSSO-12 mechanical data

Symbol

Min Typ Max

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

Millimeters

k0° 8°

X 2.200 2.800

Y 2.900 3.500

ddd 0.100

Doc ID 10858 Rev 5 21/24

Package and packing information VND810PEP-E

5.3 Packing information

Figure 14. PowerSSO-12 tube shipment (no suffix)

B

A

Figure 15. PowerSSO-12 tape and reel shipment (suffix “TR”)

Base Q.ty 100

Bulk Q.ty 2000

C

Tube length (± 0.5) 532

A 1.85

B 6.75

C (± 0.1) 0.6

All dimensions are in mm.

REEL DIMENSIONS

Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

No componentsNo components Components

Empty components pockets
saled with cover tape.

User direction of feed

Start

500mm min

22/24 Doc ID 10858 Rev 5

VND810PEP-E Revision history

6 Revision history

Table 19. Document revision history

Date Revision Changes

18-Nov-2004 1 Initial release.

Mechanical data updating.

03-Dec-2004 2

03-May-2006 3 Thermal data correction.

03-Dec-2008 4

16-Nov-2011 5

PowerSSO-24 thermal charact. insertion
PC board copper area correction.

Document reformatted and restructured.
Added list of contents, tables and figures.
Added ECOPACK
Update PowerSSO-12 mechanical data.

Document reformatted and restructured in the new Coorporate
template.

®

packages information.

Doc ID 10858 Rev 5 23/24

VND810PEP-E

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24/25 Doc ID 10858 Rev 5