SGS Thomson Microelectronics STPIC44L02PTR Datasheet

1/21July 2003

■ 4-CHANNEL S ERIAL-IN PARALLEL-IN LOW

SIDE PRE-FET DRIVER

■ DEVICES ARE CASCADABLE

■ INTERNAL 55V INDUCTIVE LOAD CLAMP

AND VGS PROTECTION CLAMP FOR
EXTERNAL POWER FETS

■ INDEPENDENT SHORTED-LOAD AND

SHORT-TO-BATTERY FAULT DETECTION
ON ALL GATE TERMINALS

■ INDEPENDENT OFF-STATE OPEN-LOAD

FAULT SENSE

■ OVER-BATTERY-VOLTAGE LOCKOUT

PROTECTION AND FAULT REPORTING

■ UNDER-BATTERY VOLTAGE LOCKOUT

PROTECTION

■ ASYNCRONOUS OPEN-GATE FAULT FLAG

■ DEVICE OUTPUT CANBE WIREDOR WITH

MULTIPLE DEVICES

■ FAULT STATUS RETURNED THROUGH

SERIAL O UTPUT TERMINAL

■ INTERNAL GL OBA L POWER-ON RESET OF

DEVICE AND EXTERNAL RESET TERMINAL

■ HIGH IMPEDANCE CMOS COMPATIBLE

INPUTS WITH HYSTERESIS

■ TRANSITION FROM THE GATEOUTPUT TO

A LOW DUTY CY CLE PWM MODE WHEN A
SHORTEDLOADFAULTOCCURS

DESCRIPTION

The STPIC44L02 is a low-side predriver that
provides serial and parallel input interfaces to
control four external FET power s w itches.
It is mainly desi gned to provide low-frequency
switching, inductive load applicati ons such as
solenoids and relays. Fault status is available in a
serial-data format. Each driver channel has
independent off-state open-load detection and
on-state shorted load short to battery detection.
The STPIC44L02 offers a batteryover voltage and
undervoltage detection and shutdown. If a fault
occurs while using the STPIC44L02, the channel
transitates into a low duty cycle , pulse width
modulated (PWM) signal as long as the fault is
present.
These devices provide control of output channels
through a serial input interface or a parallel input
interface. A command to enable the output from

either interface enables the respective channels
gate output to the external FET. The serial
interface is recom mended when the number of
signals between t he control device and the
predriver are minimized and the speed of
operation is not critical. In applications where the
predriver must respond very quickly or
asynchronously, the parallel input interface is
recommended.
For serial operation, the control device must
transitate C S

from hi gh to low to activate the serial
input interface. When this occurs, SDO, is
enabled, fault data is latched into the serial
interface, and the fault flag is refreshed. Data is
clocked into the serial registers on low to high
transitions of SCLK through SDI. Each string of
data must con sist of at least four bits of data. In
applications where multiple devices are cascaded
together, t he string of data must c onsist of four bits
for each device. A high data bit turns the
respective output c hannel on and a low data bit
turns it off. Fault data for the device is clocked out
of SDO as serial input data is clocked into the
device. Fault data consists of fault flags for
shorted load and open load flags (bits 0-3) for
each of the four output channels. Fault regist er
bits are set or cleared asynchronously to ref lect
the current state of the hardware. A fault must be
present w hen CS

is transitated from high to low to
be captured and reported in the serial fault data.
New faults cannot be captured in the serial
register when CS

is low. CS must be transitated
high after all of the serial dat a has been clocked
into the device. A low to high transition of CS
transfers t he last four bits of serial data to t he

STPIC44L02

4 CHANNEL SERIAL AND PARALLEL

LOW SIDE PRE-FET DRIVER

SOP

STPIC44L02

2/21

output buffer that puts SDO in a high im pedance
state and clears and reenables the fault register.
The STPIC44L02 was designed to allow the serial
input interfaces of multiple devices to be cascated
together to simplify the serial in terfac e of the
controller. Serial input data flows through the
device and is transferred out SDO following t he
fault data in c as caded configurations.
For parallel operation, data is transferred directly
from the parallel input interface IN0-IN3 to the
respective GATE(0-3) output asy nc hronous ly.
SCLK or CS

is not required for parallel control. A 1
on the parallel input turns the respective channel
on, where as a 0 turns it off. Note that either the
serial input interface or the parallel input in terface
can enable a channel. Under parallel operation,
fault data must still be collected t hrough the serial
data interface.
The predriver monitors the drain voltage for each
channel to detect shorted load or open load fault
conditions, in t he on and off st ate respectively.
These devices offer the option of using an
internally genera ted fault reference voltage or an
externally supplied fault reference voltage through
V

COMP

for fault detection. The internal fault

reference is selected by c onnecting V

COMPEN

to
GND and the external reference is selected by
connecting V

COMPEN

to VCC. The drain voltage is
compared to the fault reference when the channel
is turned on to detect shorted load conditions and
when t he channel is off to detect open lo ad
conditions. If a fault occurs, the channel
transitates into a low duty cycle , pulse width
modulated (PWM) signal as long as the fault is
present. Shorted load fault c onditions must be
present for at least the shorted l oad deglicth time,

t

(STBDG)

, to be flagged as a fault. A fault flag is
sent to the control device as well as the serial fault
register bits. More detail on fault detection
operation is presented in the device operation
section of this datasheet.

The device provides prote ction from over battery
voltage and under ba ttery voltage conditions
irrespective of the state of the output channels.
When the battery voltage is greater than the
overvoltage threshold or les s than the
undervotlage threshold, all channels are disabled
and a fault flag is generated. Battery voltage f aults
are not reported in the serial fault data. The
outputs return to normal operation onc e the
battery voltage fault has been corrected. When an
over battery/under battery voltage condition
occurs, the device reports the battery fault, but
disables fault reporting for open and shorted load
conditions. Fault reporting for open and shorted
load conditions are reenabled after the battery
fault condition has been corrected.

This device provides inductive transient protection
on all channels. The drain voltage is clamped to
protect the FET. The c lamp voltage is defined by
the sum of V

CC

and turn on voltage of the external
FET. The predriver also provides a gate to source
voltage (V

GS

) clamp to protect the gate source
terminals of the power FET from exceeding their
rated voltages. An external active low RESET

is
provided to clear all register and flags in the
device. GATE(0-3) outputs are disabled after
RESET has been pulled low.

The d ev ice provide pull-down resistors on all
inputs except CS

and RESET. A pull-up resistor is

usedon CS

and RESET.

ORDERING CODES

Type Package Comments

STPIC44L02PTR SSOP24 (Tape & Reel) 1350 parts per reel

STPIC44L02

3/21

Figure1 : Schematic Diagram

STPIC44L02

4/21

PIN DESCRIPTION

PIN No SYMBOL I/O NAME AND FUNCTION

1FLT

I Fault Flag. FLT is a logic level open-drain output that provides a real time fault flag for

shorted-load, open-load, over-battery voltage, under-battery voltage faults. The
device can be ORed with FLT terminals on other devices for interrupt handling. FLT
requires an external pull-up resistor.

2 VCOMPEN I Fault reference voltage select. VCOMPEN selects the internally generated fault

reference voltage (0) or an external fault reference (1) to be used in the shorted and
open load fault detection circuitry.

3 VCOMP I Fault reference voltage. VCOMP provides an external fault reference voltage for the

shorted-load and open load fault detection circuitry.

4
5
6
7

IN0
IN1
IN2
IN3

I Parallel gate driver. IN0 trough In3 are real-time controls for the gate pre drive

circuitry. They are CMOS compatible with hysteresis.

8CS

I Chip select. A high to low transition on CS enables SDO, latches fault data into the

serial interface, and refreshes FLT. When CS is high, the fault register can change
fault status. On the falling edge of CS

, fault data is latched into the serial output

register and transferred using SDO and SCLK. On a low to high transition of CS

,

serial data is latched in to the output control register.

9 SDO O Serial data output. SDO is a 3-state output that transfers fault data to the controlling

device. It also passes serial input data to the next stage for cascaded operation. SDO
is taken to a high-impedance state when CS

is in a high state.

10 SDI I Serial data input. Output control data is clocked into the serial register through SDI. A

1 on SDI commands a particular gate output on and a 0 turns it off.

11 SCLK I Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial

fault data is clocked out of SDO on the falling edge of the serial clock.

12 V

CC

I Logic Supply Voltage

13 GND I Ground
14

16
19
21

DRAIN0
DRAIN1
DRAIN2
DRAIN3

I FET drain inputs. DRAIN0 through DRAIN3 are used for both open load and short

circuit fault detection at the drain of the external FETs. They are also used for
inductive transient protection.

15
17
18
20

GATE0
GATE1
GATE2
GATE3

O Gate drive output. GATE0 through GATE3 outputs are derived from the V

BAT

supply

voltage. Internal clamps prevent voltages on these nodes from exceeding the VGS
rating of most FETs.

22 RESET

I Reset. A high-to low transition of RESET clears all registers and flags. Gate outputs

turn off and the FLT

flag is cleared.
23 NC Not Connected
24 V

BAT

I Battery Supply Voltage

STPIC44L02

5/21

Figure2 : Pin Configuration

ABSOLUTE MAXIMUM RATING S

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.

Note 1: All voltage value are with respect to GND

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

CC

Logic Supply Voltage (See Note 1)

-0.3 to 7 V

V

BAT

Battery Supply Voltage

-0.3 to 60 V

V

I

Logic Input Voltage Range

-0.3 to 7 V

V

O

Output Voltage (SDO and FLT)

-0.3 to 7 V

V

O

Output Voltage

-0.3 to 15 V

V

I

Logic Input Voltage Range

-0.3 to 7 V

V

DS

Drain to Source Voltage

-0.3 to 60 V

T

C

Operating Case Temperature Range

-40 to +125 °C

T

J

Maximum Junction Temperature

150 °C

T

stg

Storage Temperature Range

-40 to +150 °C

Symbol Parameter Min. Min. Max. Unit

V

CC

Logic Supply Voltage 4.5 5 5.5 V

V

BAT

Battery Supply Voltage 8 24 V

V

IH

High Level Input Voltage 0.85V

CC

V

CC

V

V

IL

Low Level Input Voltage 0 0.15V

CC

V

t

s

Set-up Time, SDI High Before SCLK ↑ 10 ns

t

h

Hold Time, SDI High After SCLK ↑ 10 ns

T

C

Operating Case Temperature -40 125 °C

STPIC44L02

6/21

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING F REE-AIR
TEMPERATURE RANGE (unless otherwise specified.)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

BAT

Supply Current All Outputs OFF, V

BAT

= 12V 50 150 250 µA

I

CC

Supply Current All Outputs OFF, V

BAT

= 5.5V 0.5 1.5 3 mA

V

(ovsd)

Over Battery Voltage
Shutdown

Gate Disabled (see figure 21) 32 34 36 V

V

hys(ov)

Over Battery Voltage Reset
Hysteresys

0.1 0.3 0.5 V

V

(uvsd)

Under Battery Voltage
Shutdown

Gate Disabled (see figure 20) 4.1 4.8 5.4 V

V

hys(uv)

Under Battery Voltage
Reset Hysteresys

50 150 300 mV

V

G

Gate Drive Voltage V

BAT

=8to24V IO=100µA 7 13.5 V

V

BAT

= 5.5 to 8V IO=100µA5 8V

I

O(H)

Maximum Current Output
For Drive Terminal Pull-Up

VO= GND 0.5 1.8 2.5 mA

I

O(L)

Maximum Current Output
For Drive Terminal
Pull-Down

V

O

= 7V 0.5 1.2 2.5 mA

V

(stb)

Short to Battery, Shorted
Load, Open Load Detection
Voltage

V

COMPEN

= L 1.1 1.25 1.4 V

V

hys(stb)

Short to Battery Hysteresys 30 mV

V

D(open)

Open Load OFF State
Detection Voltage
Threshold

V

COMPEN

= L 1.1 1.25 1.4 V

V

hys(open)

Open Load Hysteresys 60 mV

I

I(open)

Open Load Off State
Detection Current

V

DRAIN=VREF

= 1.25V 30 60 80 µA

V

DRAIN

= 24V (see figure 24) 250 µA

I

I(PU)

Input Pull-up Current VCC=5V VI=0 10 µA

I

I(PD)

Input Pull-down Current VCC=5V VI=5V 10 µA

V

hys

Input Voltage Hysteresys VCC= 5V 0.6 0.85 1.1 V

V

O(SH)

High Level Serial Output
Voltage

IO= 1mA 0.8V

CC

V

V

O(SL)

Low Level Serial Output
Voltage

IO= 1mA 0.1 0.4 V

I

OZ(SD)

3-State Current Serial Data
Output

VCC= 0 to 5.5V -10 1 10 µA

V

O(CFLT)

Fault Interrupt Output
Voltage

IO= 1mA 0.1 0.5 V

V

I(COMP)

Fault External Reference
Voltage

V

COMPEN

=H 1 3 V

V

C

Output Clamp Voltage dc < 1% tW=100µs 475563V

STPIC44L02

7/21

SWITCHING CHARACTERISTICS (VCC=5V, V

BAT

=5V, TC= 25°C, unlessotherwise specified.)

Note 1: Thetd1is referred to the falling edge of the first clock after theCSfallsdown

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

(STBFM)

Short to Battery, Shorted
Load, Open Load Fault
Mask Time

(see figures 16, 17) 60 µs

t

(STBDG)

Short to Battery, Shorted
Load, Deglitch Time

(see figures 16, 17) 12 µs

t

PLH

Propagation Turn-On Delay
Time, CS

or IN0-IN3 to

Gate0-Gate3

C

(gate)

= 400pF 3.5 µs

t

PHL

Propagation Turn-Off Delay
Time, CS

or IN0-IN3 to

Gate0-Gate3

C

(gate)

= 400pF 4 µs

t

r1

Rise Time, Gate0-Gate3 C

(gate)

= 400pF 1.5 µs

t

f1

Fall Time, Gate0-Gate3 C

(gate)

= 400pF 2 µs

f

(SCLK)

Serial Clock Frequency 10 MHz

t

rf(SB)

Refresh Time Short to
Battery

(see figure 16) 10 ms

t

W)

Refresh pulse width Short
to Battery

(see figure 16) 68 µs

t

su1

Setup Time CS ↓ to SCLK ↓ (see note 1) (see figure 4) 10 ns

t

pd1

Propagation Delay Time CS
to SDO Valid

R

L

=10KΩ CL= 200pF

(see figure 6)

40 ns

t

pd2

Propagation Delay Time
SCLK to SDO Valid

20 ns

t

pd3

Propagation Delay Time CS
to SDO 3-State

RL=10KΩ CL= 50pF
(see figure 6)

2 µs

t

r2

Rise Time, SDO 3-State to
SDO Valid

RL=10KΩto GND CL= 200pF
Over Battery Fault (see figure 7)

30 ns

t

f2

Fall Time, SDO 3-State to
SDO Valid

RL=10KΩto GND CL= 200pF
No Fault (see figure 8)

20 ns

t

r3

Rise Time, FLT RL=10KΩ CL= 50pF

(see figure 9)

1.2 µs

t

f3

Rise Time, FLT RL=10KΩ CL= 50pF

(see figure 9)

15 ns