SGS Thomson Microelectronics STPCI2 Datasheet

STPC® ATLAS

X86 Core PC Compatible System-on-Chip for Terminals

Issue 1.0 - July 24, 2002 1/111

Figure 0-1. Logic Diagram

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POWERFUL x86 PROCESSOR

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64-BIT SDRAM UMA CONTROLLER

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GRAPHICS CONTROLLER

- VGA & SVGA CRT CONTROLLER

- 135MHz RAMDAC

- ENHANCED 2D GRAPHICS ENGINE

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VIDEO INPUT PORT

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VIDEO PIPELINE

- UP-SCALER

- VIDEO COLOUR SPACE CONVERTER

- CHROMA & COLOUR KEY SUPPORT

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TFT DISPLAY CONTROLLER

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PCI 2.1 MASTER / SLAVE / ARBITER

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ISA MASTER / SLAVE CONTROLLER

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16-BIT LOCAL BUS INTERFACE

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PCMCIA INTERFACE CONTROLLER

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EIDE CONTROLLER

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2 USB HOST HU B INTER FACES

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I/O FEATURES

- PC/AT+ KEYBOARD CONTR O L LER

- PS/2 MOUSE CONTROLLER

- 2 SERIAL PORTS

- 1 PARALLEL PORT

- 16 GENERAL PURPOSE I/Os

- I²C IN TERFACE

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INTEGRATED PERIPHERAL CONTROLLER

- DMA CONTROLLER

- INTERRUPT CONTROLLER

- TIMER / COUNTERS

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POWER MANAGEMENT UNIT

■

WATCHDOG

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JTAG IEEE1149.1

PBGA516

x86

Core

Host

I/F

SDRAM

CTRL

SVGA

GE I/F VIP

PCI

m/s

LB ctrl

PCI Bus

ISA m/s

IPC

PCI m/s

ISA Bus

CRTC

Cursor

Monitor

IDE

I/F

PMU

wdog

Video

Pipeline

C Key K Key

LUT

Local Bus

PCMCIA

I/Os

USB

TFT

TFT I/F

Video In

STPC® ATLAS

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DESCRIPTION

The STPC Atlas integrates a standard 5th generation x86 core along with a powerful UMA graphics/video chipset, support logic including PCI, ISA, Local Bus, USB, EIDE controllers and combines them with standard I/O interfaces to provide a single PC compatible subsystem o n a single device, suitable for all kinds of terminal and industrial appliances.

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X86 Processor core

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Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatib l e .

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Can access up to 4GB of external memory.

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8Kbyte unified instruction and data cache

with write back and write through capability.

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Parallel processing integral floating point unit,

with automatic power down.

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Runs up to 133 MHz (X2).

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Fully static design for dynamic clock control.

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Low power and system management modes.

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Optimized design for 2.5V operation.

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SDRAM Controller

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64-bit data bus.

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Up to 90MHz SDRAM clock speed.

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Integrated system memory, graphic frame

memory and video frame memory.

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Supports 8MB up to 128 MB system memory .

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Supports 16-Mbit, 64-Mbit and 128-Mbit

SDRAMs.

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Support s 8, 16, 32, 64, and 128 MB DIMMs.

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Supports buffered, non buffered, and

registered DIMMs

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4-line write buffers f or CPU to DRAM and PCI

to DRAM cycles.

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4-line read prefetch buffers for PCI masters.

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Programmable latency

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Programmable timing for SDRAM

parameters.

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Support s -8, -10, -12, -13, -15 memory par t s

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Supports memory hole between 1MB and

8MB for PCI/ISA busses.

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32-bit access, Autoprecharge & Power-down

are not supported.

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Enhanced 2D Graphics Controller

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Support s pixel depths of 8, 16, 24 and 32 bit.

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Full BitBLT implementat ion for all 256 raster

operations defined for Windows.

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Support s 4 transparent BLT modes - Bitmap

Transparency, Pat tern Transparency, Source Transparency and Destination Transparency.

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Hardware clipping

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Fast line draw engin e with anti-aliasing.

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Supports 4-bit alpha blended font for anti-

aliased text display.

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Complete double buffered registers for

pipelined operation.

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64-bit wide pipelined architecture running at

90 MHz. Hardware clipping

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CRT Controlle r

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Integrated 135MHz triple RAMDAC allowing

for 1280 x 1024 x 75Hz display.

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8-, 16-, 24-bit pixels.

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Interlaced or non-interlaced output.

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Video Input port

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Accepts video inputs in CCIR 601/656 mode.

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Optional 2:1 decimator

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Stores captured video in off setting area of

the onboard frame buffer.

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HSYNC and B/T generation or lock onto

external video timing source.

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Video Pipeli ne

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Two-tap interpolative horizontal filter.

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Two-tap interpolative vertical filter.

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Color space conversion (RGB to YUV and

YUV to RGB).

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Programmable window size.

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Chroma and color keying for integrat ed video

overlay.

STPC® ATLAS

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TFT Int erface

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Programmable panel size up to 1024 by 1024

pixels.

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Support for VGA and SVGA active matrix

TFT flat panels with 9, 12, 18-bit interface (1 pixel per clock).

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Support for XGA and SXGA active matrix

TFT flat panels with 2 x 9-bit interface (2 pixels per clock).

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Programmable image positionning.

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Programmable blank space insertion in text

mode.

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Programmable horizontal a nd vertical image

expansion in graphic mode.

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One fully programmable PWM (Pulse Width

Modulator) signals to adjust the flat panel brightness and contrast.

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Support s

PanelLink

high speed serial transmitter externally for high resolution panel interface.

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PCI Controller

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Compatible with PCI 2.1 specification.

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Integrated PCI arbitration interface. Up to 3

masters can connect directly. External logic allows for greater than 3 masters.

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Translation of PCI cycles to ISA bus.

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Translation of ISA maste r initiated cycle to

PCI.

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Support for burst read/write from PCI master.

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PCI clock is 1/2, 1/3 or 1/4 Host bus clock.

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ISA master/slave

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Generates the ISA clock from either

14.318 MH z o s c illator clock or P CI c lo ck

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Support s programmable extra wait state for

ISA cycles

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Supports I/O recovery time for back to back

I/O cycles.

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Fast Gate A20 and Fast reset.

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Support s the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

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Support s flash ROM.

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Support s ISA hidden re fresh.

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Buffered DMA & ISA master cycl es t o reduce

bandwidth utilization of the PCI and Host bus.

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Local Bus interface

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Multiplexed with ISA/DMA interface.

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Low latency asynchronous bus

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16-bit data bus with word steering capability.

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Programmable timing (Host clock granularity)

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4 Programmable Flash Chip Select.

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8 Programmable I/O Chip Select.

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I/O devic e timi n g (set u p & reco very time)

programmable

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Support s 32-bit Flash burst.

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2-level hardware ke y protection for Flash boot

block protection.

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Supports 2 banks of 32MB flash devices with

boot block shadowed to 0x000F0000.

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Reallocatable Memory space Windows

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EIDE Interface

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Supports PIO

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Transfer Rates to 22 MBytes/sec

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Supports up to 4 IDE devices

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Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFOs per channel

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Support for PIO mode 3 & 4.

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Individual drive timing for all four IDE devices

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Support s both legacy & native IDE modes

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Supports hard drives larger than 528MB

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Support for CD-ROM and tape peripherals

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Backward compatibil it y wit h ID E (ATA-1).

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Integrated Peripheral Controller

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2X8237/AT compatible 7-channel DMA

controller.

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2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

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Three 8254 compatible Timer/Counters.

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Co-processor error support logic.

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Support s external RTC (Not in Local Bus

Mode).

STPC® ATLAS

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PCMCIA interface

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Support one PCMCIA 68-pin standard PC

Card Socket .

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Power Management support.

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Support PCMCIA/ATA specifications.

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Support I/O PC Card with pulse-mode

interrupts.

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USB Interface

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USB 1.1 compatible.

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Open HCI 1.0 compliant.

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User configurable RootHub.

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Support for both LowSpeed and HighSpeed

USB devices.

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No bi-directionnal or Tri-state busses.

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No level sensitive lat ches.

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System Management Interrupt pin support

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Hooks for legacy device support.

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Keyboard interface

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Fully PC/AT+ compatible

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Mouse interface

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Fully PS/ 2 compatible

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Serial inte rface

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15540 compatible

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Programmable word length, stop bits, parity.

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16-bit programmable baud rate generator.

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Interrupt generator.

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Loop-back mode.

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8-bit scratch register.

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Two 16-bit FIFOs.

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Two DMA handshake lines.

Paralle l port

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All IEEE Standard 1284 protocols supported:

Compatibility, Nibble, Byte, EPP, and ECP modes.

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16 bytes FIFO for ECP.

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Power Manage me nt

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Four power saving modes: On, Doze,

Standby, Suspend.

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Programmable system activity detector

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Support s Intel & Cyrix SMM and APM.

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Supports STOPCLK.

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Support s IO trap & restart .

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Independent peripheral time-out timer to

monitor hard disk, serial & parallel port.

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128K SM_RAM address space from

0xA0000 to 0xB0000

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JTAG

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Boundary Scan com patible IEEE1149 .1.

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Scan Chain control.

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Bypass register compatible IEEE1149.1.

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ID register compatible IEEE1149.1.

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RAM BIST co ntrol.

ExCA

is a trademark of PCMCIA / JEIDA.

PanelLink

is a trademark of SiliconImage, Inc

GENERAL DESCRIPTION

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1. GENERAL DESCRIPTIO N

At the heart of the STPC Atlas is an advanced processor block that includes a powerful x86 processor core along with a 64-bit SDRAM controller, advanced 64-bit accelerated graphics and video controller, a high speed PCI bus controller and industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus).

The STPC Atlas has in addition, a TFT output, a Video Input, an EIDE controller, a Local Bus interface, PCMCIA and super I/O features including USB host hub.

1.1. ARCHITECTURE

The STPC Atlas ma ke s use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memory and graphics frame-buf fer. This me ans a reduction in total system memory for system performances that are equal to that of a comparable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface runni ng at the speed of the processor bus rather than the traditional PCI bus.

The 64-bit wide memory array provides the system with an 800MB/s peak bandwidth. This allows for higher resolution screens and greater color depth. The processor bus runs a t 133 MHz, further increasing “standard” bandwidth by at least a factor of two.

The ‘standard’ PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional low bandwidth functions such as communication ports are accessed by the ST PC Atlas via an internal ISA bus.

The PCI bus is the ma in data comm unication link to the STPC A tl as c hip. Th e STPC Atl as t ran slate s appropriate host bus I/O an d M em ory cycles onto the PCI bus. It also supports the generation of Configuration cycles on the PCI bus. The STPC Atlas, as a PCI bus agent (host bridge class), is compatible with PCI specification 2.1. The chipset also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three external PCI devi ces.

Figure 1-1 describes this architecture.

1.2. GRAPHICS FEATURES

Graphics functions are controlle d through t he onchip SVGA controller and the monitor display is produced through the 2D graphics display engine.

This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost. It performs limited graphics drawing operations which include hardware acceleration of t ext, bitblts, transparent blts and fills. The results of these operations change the contents of the on-screen or offscreen frame buffer areas of SDRAM memory. The frame buffer can occupy a space up to 4 Mbytes anywhere in the physical main memory.

The maximum graphics resolution supported is 1280 x 1024 in 16 Million colours at 75 Hz refresh rate and is VGA and SVGA compatible. Horizontal timing fields are VGA compatible while the vertical fields are extended by one bit to accommodate above display resolution.

To generate the TFT output, the STPC Atlas extracts the digital video stream before the RAMDAC and reformats i t to the TF T form at. T he height and width of the flat panel are programmable.

1.3. INTERFACES

An industry standard EIDE (ATA 2) controller is built in to the STPC Atlas and connected internally via the PCI bus.

The STPC Atlas integrates two USB ports. Universal Serial Bus (USB) is a general purpose communications interface for connecting peripherals to a PC. The USB Open Host Controller Interface (Open HCI) Specification, revision 1.1, supports speeds of up to 12 MB/s. USB is royalty free and is likely to replace lowspeed legacy serial, parallel, keyboard, mouse and floppy drive interfaces. USB Revision 1.1 is fully supported under Microsoft W indows 98 and Windows 2000.

The STPC Atlas PCMCIA controller has been specifically designed to provide the interface with PCMCIA cards which cont ain additional memory or I/O

The power management control facilities include socket power control, insertion/removal capability, power saving with Windows inactivity, NCS controlled Chip Power Down, together with further controls for 3.3V suspend with Modem Ring Resume Detection.

GENERAL DESCRIPTION

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The STPC Atlas implements a multi-function parallel port. The standard PC/AT compatible logical address assignments for LPT1, LPT2 and LPT3 are supported. It can be configured for any of the following three modes and supports the IEEE Standard 1284 parallel interface protocol standards, as follows:

- Compatibility Mode (Forward channel, standard)

- Nibble Mode (Reverse channel, PC compatible)

- Byte Mode (Reverse channel, PS/2 compatible) The General Purpose Input/Output (GPIO)

interface provides a 16-bit I/O facility, using 16 dedicated device pins. It is organised using two blocks of 8-bit Registers, one for lines 0 to 7, the other for lines 8 to 15. Each GPIO port can be configured as an input or an output simply by programming the assoc iated port direction control register. All GPIO ports are configured as inputs at reset, which also la tches the input levels into the Strap Registers. The input states of the ports are thus recorded automatically at reset, and this can be used as a strap register anywhere in the system.

1.4. FEATURE MULTIPLEXING

The STPC Atlas BGA package has 516 balls. This however is not sufficient for all of the integrat ed functions available; some features therefore share the same balls and cannot thus be used at the same time. The ST PC A tlas c onfigurat ion is d one by ‘strap options’. This is a set of pull-up or pulldown resistors on the memory data bus, checked on reset, which auto-configure the STPC Atlas.

There 3 multiplexed functions are the external ISA bus, the Local Bus and the PCMCIA interface.

1.5. POWER MANAGEMENT

The STPC Atlas core is compliant with the Advanced Power Management (APM) specification to provide a standard method by which the BIOS can control the power used by personal computers. The Power Management Unit (PMU) module controls the power consumption, providing a comprehensive set of features that controls the power usage and supports compliance with the United States Environmental Protection Agency's Energy Star Computer Program. The PMU provides the following hardware structures to assist the software in managing the system power consumption:

- System Activity Detection.

- 3 power-down timers detecting system inactivity:

- Doze timer (short durations).

- Stand-by timer (medium durations).

- Suspend timer (long durations).

- House-keeping activity detection.

- House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state.

- Peripheral activity detection.

- Peripheral timer detecting peripheral inactivity

- SUSP# modulation to adjust the system performance in various power down state s of the system including full power-on state.

- Power control outputs to disable power from different planes of the board.

Lack of system activity for progressively longer periods of time is detected by the three power down timers. These timers can generate SMI interrupts to CPU so that the SMM software can put the system in decreasing states of power consumption. Alternatively, system activity in a power down state can g enerate an SMI interrupt to allow the software to bring the system back up to full power-on state. The chip-set supports up to three power down states described above; these correspond to decreasing levels of power savings.

Power down puts the STPC Atlas into suspend mode. The processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. During the suspend mode, internal clocks are stopped. Removing power-down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. Because of the static nature of the core, no internal data is lost.

1.6. JTAG

JTAG stands for Joint Test Action Group and is the popular name for IEEE Std. 1149.1, Standard Test Access Port and Boundary -S can Architec ture. This built-in circuitry is used to assist in the test, maintenance and support of functional circuit blocks. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan registe r so that a component is able to respond to a minimum set of test instructions.

GENERAL DESCRIPTION

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Figure 1-1. Functional description.

x86

Core

Host

I/F

SDRAM

CTRL

SVGA

GE I/F

VIP

PCI

m/s

CTRL

PCI Bus

ISA m/s

IPC

PCI m/s

ISA Bus

CRTC

Cursor

Monitor

IDE

I/F

PMU

Video

Pipeline

C Key K Key

LUT

Local Bus

PCMCIA

I/Os

USB

TFT

TFT I/F

Video In

JTAG

GENERAL DESCRIPTION

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1.7. CLOCK TREE

The STPC Atlas integrates many features and generates all its clocks from a single 14MHz oscillator. This results in multiple clock domains as described in Figure 1-2.

The speed of the PLLs is either fixed (DE VCLK), either programmable by strap option (HCLK) either programmable by software (DCLK, MCLK). When in synchronized mode, MCLK speed is fixed to HCLKO speed and HCLKI is generated from MCLKI.

Figure 1-2. STPC Atlas clock architecture

Kbd/Mouse

IPC

SDRAM controller

North Bridge

14.31818 MHz

XTALO XTALI

OSC14M ISACLK

1/4

DEVCLK

(24MHz)

PLL

(14MHz)

1/2

UARTs

HCLK

PLL

PCICLKI PCICLKO

South Bridge

PWM

1/2 1/3

HCLK

DCLK

PLL

MCLK

PLL

DCLK

MCLKIMCLKO

USB

CRTC,Video,TFT

CPU

VCLK

48MHz

// Port

1/4

1/2

1/26

1/6

VIP

GE, LDE, AFE

PCMCIA

Local Bus

Host

ISA

HCLKI

HCLKO

GENERAL DESCRIPTION

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Figure 1-3. Typical ISA-based Application.

Flash

Boot

ISA

PCI

EIDE

2 Serial Ports

Parallel Port

SVGA

TFT

IRQ

DMA.REQ

DMA.ACK

STPC Atlas

Mouse

Keyboard

USB

VIP

RTC

SDRAM

16 GPIOs

ROMCS#

5V tolerant

GENERAL DESCRIPTION

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Figure 1-4. Typical PCMCIA-based Application.

PCI

Flash

EIDE

2 Serial Ports

Parallel Port

SVGA

TFT

STPC Atlas

Mouse

Keyboard

USB

Boot

VIP

SDRAM

16 GPIOs

ROMCS#

PCMCIA

5V tolerant

GENERAL DESCRIPTION

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Figure 1-5. Typical Local-Bus-based Application.

Flash

Boot

PCI

STPC Atlas

RTC

EIDE

2 Serial Ports

Parallel Port

SVGA

TFT

Mouse

Keyboard

USB

VIP

SDRAM

16 GPIOs

IRQ

Local Bus

GENERAL DESCRIPTION

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PIN DESCRIPTION

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2. PIN DESCRIPTION

2.1. INTRODUCTION

The STPC Atlas integrates most of the functionalities of the PC architecture. Therefore, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Atlas. This offers improved performance due to the tight coupling of the processor core and it’s peripherals. As a result many of the external pin connections are made directly to the on-chip peripheral functions.

Table 2-1 describes the physical implement ation

listing signal types a nd their functional ities. Tab le

2-2 provides a full pin listing and description. Table 2-6 provides a full l isting of the STP C A t las

package pin location physical connection. Please refer to the pin allocation drawing for reference.

Due to the number of pins available for the package, and the number of functional I/Os, some pins have several functions, selectable by strap option on Reset. Table 2-4 provides a summary of these pins and their functions.

Non multi-functional pins associated with a particular function are not available for use elsewhere when that function is disabled. For example, when in the ISA mode, the Local Bus is

disabled totally and Local Bus pins are set to the tri-state (high-impedance) condition.

Table 2-1.

Signal Description

Group name Qty

Basic Clocks, Reset & Xtal (SYS) 19 SDRAM Controller (SDRAM) 95 PCI Controller 51 ISA Controller 80

100

Local Bus I/F 67 PCMCIA Controller 62 IDE Controller 34 VGA Controller (VGA) / I

C10 Video Input Port 11 TFT output 24 USB Controller 6 Serial Interface 16 Keyboard/Mouse Controller 4 Parallel Port 18 GPIO Signals 16 JTAG Signals 5 Miscellaneous 5 Grounds 96 V

3.3 V/2.5 V 36 Reserved 4 Total Pin Count 516

PIN DESCRIPTION

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Table 2-2.

Definitio n of Si gn a l Pins

Signal Name Dir Buffer Type

Description Qty

BASIC CLOCKS AND RESETS

SYSRSTI# I SCHMITT_FT System Reset / Power good 1 SYSRSTO# O BD8STRP_FT Reset Output to System 1

XTALI I

OSCI13B

14.31818 MHz Crystal Input External Oscillator Input

XTALO O 14.31818 MHz Crystal Output 1 PCI_CLKI I TLCHT_FT 33 MHz PCI Input Clock 1 PCI_CLKO O BT8TRP_TC 33 MHz PCI Output Clock 1 ISA_CLK, ISA_CLK2X

O BT8TRP_TC

ISA Clock x1 and x2 Multiplexer Select Line for IPC

OSC14M O BD8STRP_FT ISA bus synchronisation clock 1 HCLK I/O BD4STRP_FT 66 MHz Host Clock (Test pin) 1 DEV_CLK O BT8TRP_ TC 24 MHz Peripheral Clock 1 DCLK I/O BD4STRP_FT 135 MHz Dot Clock 1 V

_xxx_PLL 2.5V Power Supply for PLL Clocks 7

MEMORY CONTROLLER

MCLKI I TLCHT_TC Memory Clock Input 1 MCLKO O BT8TRP_TC Memory Clock Output 1 CS#[1:0] O BD8STRP_TC DIMM Chip Select 2

CS#[3]/MA[12]/BA[1] O BD16STARUQP_TC

DIMM Chip Select Memory Address Bank Address

CS#[2]/MA[11] O BD16STARUQP_TC

DIMM Chip Select Memory Address

MA[10:0] O BD16STARUQP_TC Memory Row & Column Address 11 BA[0] O BD16STARUQP_TC Bank Address 1 RAS#[1:0] O BD16STARUQP_TC Row Address Strobe 2 CAS#[1:0] O BD16STARUQP_TC Column Address Strobe 2 MWE# O BD16STARUQP_TC Write Enable 1 MD[0] I/O BD8STRUP_F T Memory Data 1 MD[53:1] I/O BD8TRP_TC Memory Data 53 MD[63:54] I /O BD8STRU P_F T Memory Data 10 DQM[7:0] O BD8STRP_TC Data Input/Ouput Mask 8

PCI INTERFACE

AD[31:0] I/O BD8PCIARP_FT Address / Data 32 CBE[3:0] I/O BD8PCIARP_FT Bus Commands / Byte Enables 4 FRAME# I/O BD8PCIARP_FT Cycle Frame 1 TRDY# I/O BD8PCIARP_FT Target Ready 1 IRDY# I/O BD8PCIARP_FT Initiator Ready 1 STOP# I/O BD8PCIARP_FT Stop Transaction 1 DEVSEL# I/O BD8PCIARP_FT Device Select 1 PAR I/O BD8PCIARP_FT Parity Signal Transactions 1 PERR# I/O BD8PCIARP_FT Parity Error 1 SERR# O BD8PCIARP_FT System Error 1 LOCK# I TLCHT_FT PCI Lock 1 PCI_REQ#[2:0] I BD8PCIARP_FT PCI Request 3 PCI_GNT#[2:0] O BD8PCIARP_FT PCI Grant 3 PCI_INT#[3:0] I BD4STRUP_FT PCI Interrupt Request 4

Note

; See

Table 2-3

for buffer type descriptions

PIN DESCRIPTION

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ISA BUS INTERFACE

LA[23:17] O BD8STRUP_FT Unlatched Address Bus 7 SA[19:0] O BD8STRUP_FT Latched Address Bus 20 SD[15:0] I/O BD8STRP_FT Data Bus 16 IOCHRDY I BD8STRUP_FT I/O Channel Ready 1 ALE O BD4STRP_FT Address Latch Enable 1 BHE# O BD8STRUP_FT System Bus High Enable 1 MEMR#, MEMW# I/O BD8STRUP_FT Memory Read & Write 2 SMEMR#, SMEMW# O BD8STRP_FT System Memory Read and Write 2 IOR#, IOW# I/O BD8STRUP_FT I/O Read and Write 2 MASTER# I BD4STRUP_FT Add On Card Owns Bus 1 MCS16# I BD4STRUP_F T Memory Chip Select 16 1 IOCS16# I BD4STRUP_FT I/O Chip Select 16 1 REF# I BD8STRP _FT Refresh Cycle 1 AEN O BD8STRUP_FT Address Enable 1 IOCHCK# I BD4STRUP_FT I/O Channel Check (ISA) 1 RTCRW# O BD4STRP_FT RTC Read / Write# 1 RTCDS# O BD4STRP_FT RTC Data Strobe 1 RTCAS O BD4STRP_FT RTC Address Strobe 1 RMRTCCS# O BD4STRP_FT ROM / RTC Chip Select 1 GPIOCS# I/O BD4STRP_FT General Purpose Chip Select 1 IRQ_MUX[3:0] I BD4STRP_FT Multiplexed Interrupt Request 4 DACK_ENC[2:0] O BD4STRP_FT DMA Acknowledge 3 DREQ_MUX[1:0] I BD4STRP_FT Multiplexed DMA Request 2 TC O BD4STRP_FT ISA Terminal Count 1 ISAOE# I BD4STRP_FT ISA (0) / IDE (1) SELECTION 1 KBCS# I/O BD4STRP_FT External Keyboard CHIP SELECT 1 ZWS# I BD4STRP_FT ZERO WAIT STATE 1

PCMCIA INTERFAC E

RESET O BD8 STRP _FT Reset 1 A[23:0] O BD8STRUP_FT Address Bus 24 D[15:0] I/O BD8STRP_FT Data Bus 16 IORD#, IOWR# O BD8STRUP_FT I/O Read and Write 2

WP / IOIS16# I BD4STRUP_FT

DMA Request // Write Protect I/O Size is 16 bit

BVD2, BVD1 I BD4STRUP_FT Battery Voltage Detect 2 READY# / IREQ# I BD4STRUP_FT Busy / Ready# // Interrupt Request 1 WAIT# I BD8STRUP_FT Wait 1 OE# O BD8STRUP_FT Output Enable // DMA Terminal Count 1 WE# O BD4STRP_FT Write Enable // DMA Terminal Count 1 REG# O BD4STRUP_FT DMA Acknowledge // Register 1 CD2#, CD1# I BD4STRUP_FT Card Detect 2 CE2#, CE1# O BD4STRP_FT Card Enable 2 VCC5_EN O BD4STRP_FT Power Switch control: 5 V power 1 VCC3_EN O BD8STRP_FT Power Switch control: 3.3 V power 1 VPP_PGM O BD8STRP_FT Power Switch control: Program power 1 VPP_VCC O BD4STRP_FT Power Switch control: VCC power 1 GPI# I BD4STRP _FT General Purpose Input 1

Table 2-2.

Definitio n of Si gn a l Pins

Signal Name Dir Buffer Type

Description Qty

Note

; See

Table 2-3

for buffer type descriptions

PIN DESCRIPTION

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LOCAL BUS INTERFACE

PA[24:20,15,9:8,3:0] O BD4STRP_FT Address Bus [24:20], [15], [9:8], [3:0] 12 PA[19,11] O BD8STRP_FT Address Bus [19], [11] 2 PA[18:16,14:12,7:4] O BD8STRUP_FT Address Bus [18:16], [14:12], [7:4] 10 PA[10] O BD4STRUP_FT Address Bus [10] 1 PD[15:0] I/O BD8STRP_FT Data Bus [15:0] 16 PRD# O BD4STRUP_FT Memory and I/O Read signal 1 PWR# O BD4STRUP_FT Memory and I/O Write signal 1 PRDY I BD8STRUP_FT Data Ready 1 IOCS#[7:4] O BD4STRUP_FT I/O Chip Select 4 IOCS#[3] O BD4STRP_FT I/O Chip Select 1 IOCS#[2:0] O BD8STRUP_FT I/O Chip Select 3 PBE#[1] O BD8STRP_FT Upper Byte Enable (PD[15:8]) 1 PBE#[0] O BD4STRUP_FT Lower Byte Enable (PD[7:0]) 1 FCS0# O BD4STRP_FT Flash Bank 0 Chip Select 1 FCS1# O BT8TRP_TC Flash Bank 1 Chip Select 1 FCS_0H# O BD8STRP_FT Upper half Bank 0 Flash Chip Select 1 FCS_0L# O BD8STRP_FT Lower half Bank 0 Flash Chip Select 1 FCS_1H# O BD8STRP_FT Upper half Bank 1 Flash Chip Select 1 FCS_1L# O BD8STRP_FT Lower half Bank 1 Flash Chip Select 1 IRQ_MUX[3:0]

I/O BD4STRP_FT Muxed Interrupt Lines 4

IDE CONTROLLER

DD[15:12] I/O BD4STRP_FT Data Bus 4 DD[11:0] I/O BD8STRUP_FT Data Bus 12 DA[2:0] O BD8STRUP_FT Address Bus 3 PCS1, PCS3 O BD8STRUP_FT Primary Chip Selects 2 SCS1, SCS3 O BD8STRUP_FT Secondary Chip Selects 2 DIORDY O BD8STRUP_FT Data I/O Ready 1 PIRQ/SIRQ I BD4STRP_FT Primary / Secondary Interrupt Request 2 PDRQ/SDRQ I BD4STRP_FT Primary / Secondary DMA Request 2 PDACK#/SDACK# O BD8STRP_FT Primary / Secondary DMA Acknowledge 2 PDIOR#/SDIOR# O BD8STRUP_FT Primary / Secondary IO Read 2 PDIOW#/SDIOW# O BD8STRP_FT Primary / Secondary IO Write 2

VGA CONTROLLER

RED, GREEN, BLUE O VDDCO Red, Green, Blue 3 VSYNC, HSYNC I/O BD4STRP_FT Vertical & Horizontal Synchronisations 2 VREF_DAC I ANA DAC Voltage reference 1 RSET I ANA Re sistor Set 1 COMP I ANA Compensation 1 COL_SEL O BD4STRP_FT Colour Select 1

I2C INTERFACE

SCL / DDC[1] I/O BD4STRUP_FT I²C Interface - Clock / VGA DDC[1] 1 SDA / DDC[0] I/O BD4STRUP_FT I²C Interface - Data / VGA DDC[0] 1

TFT INTERFACE

TFTR[5:2] O BD4STRP_TC Red 4 TFTR[1:0] O BD4STRP_FT Red 2 TFTG[5:2] O BD4STRP_TC Green 4 ,TFTG[1:0] O BD4STRP_FT Green 2

Table 2-2.

Definitio n of Si gn a l Pins

Signal Name Dir Buffer Type

Description Qty

Note

; See

Table 2-3

for buffer type descriptions

PIN DESCRIPTION

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TFTB[5:2] O BD4STRP_TC Blue 4 TFTB[1:0] O BD4STRP_FT Blue 2 TFTLINE O BD8STRP_TC Horizontal Sync 1 TFTFRAME O BD4STRP_TC Vertical Sync 1 TFTDE O BD4STRP_TC Data Enable 1 TFTENVDD, TFTENVCC

O BD4STRP_TC Enable Vdd & Vcc of flat panel 2

TFTPWM O BD8STRP_TC PWM back-light control 1 TFTDCLK O BT8TRP_TC Dot clock for Flat Panel 1

VIDEO INPUT PORT

VCLK I/O BD8STRP_FT 27-33 MHz Video Input Port Clock 1 VIN[7:0] I BD4STRP_FT Video Input Data Bus 8 ODD_EVEN# I/O BD4STRP_FT Video Input Odd/even Field 1 VCS I/O BD4STRP_FT Video Input Horizontal Sync 1

USB INTERFACE

OC I TLCHTU_TC Over Current Detect 1 USBDPLS[0]

USBDMNS[0]

I/O USBDS_2V5 Universal Serial Bus Port 0 2

USBDPLS[1]

USBDMNS[1]

I/O USBDS_2V5 Universal Serial Bus Port 1 2

POWERON

O BT4CRP USB power supply lines 1

SERIAL CONTROLL ER

CTS0#, CTS1# I TLCHT_FT Clear to send, MSR[4] status bit 2 DCD0#, DCD1# I TLCHT_FT Data Carrier detect, MSR[7] status bit 2 DSR0#, DSR1# I TLCHT_FT Data set ready, MSR[5] status bit. 2 DTR0#, DTR1# O BD4STRP_TC Data terminal ready, MSR[0] status bit 2 RI0#, RI1# I TLCHT_FT Ring indicator, MSR[6] status bit 2 RTS0#, RTS1# O BD4STRP_TC Request to send, MSR[1] status bit 2 RXD0, RXD1 I TLCHT_FT Receive data, Input Serial Input 2 TXD0, TXD1 O BD4STRP_TC Transmit data, Serial Output 2

KEYBOARD & MOUSE INTERFACE

KBCLK I/O BD4STRP_TC Keyboard Clock Line 1 KBDATA I/O BD4STRP_TC Keyboard Data Line 1 MCLK I/O BD4STRP_TC Mouse Clock Line 1 MDATA I/O BD4STRP_TC Mouse Data Line 1

PARALLEL PORT

PE I BD14STARP_FT Paper End 1 SLCT I BD14STARP_FT SELECT 1 BUSY# I BD14STARP_FT BUSY 1 ERR# I BD14STARP_FT ERROR 1 ACK# I BD14STARP_FT Acknowledge 1 PDIR# O BD14STARP_FT Parallel Device Direction 1 STROBE# O BD14STARP_FT PCS / STROBE# 1 INIT# O BD14STARP_FT INIT 1 AUTOFD# O BD14STARP_FT Automatic Line Feed 1 SLCTIN# O BD14STARP_FT SELECT IN 1 PPD[7:0] I/O BD14STARP_FT Data Bus 8

Table 2-2.

Definitio n of Si gn a l Pins

Signal Name Dir Buffer Type

Description Qty

Note

; See

Table 2-3

for buffer type descriptions

PIN DESCRIPTION

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GPIO SIGNALS

GPIO[15:0] I /O BD4STRP _FT General Purpose IOs 16

JTAG

TCLK I TLCHT_FT Test Clock 1 TRST I TLCHT_FT Test Reset 1 TDI I TLCHTD_FT Test Data Input TMS I TLCHT_FT Test Mode Set 1 TDO O BT8TRP_TC Test Data output 1

MISCELLANEOUS

SCAN_ENABLE I TLCHTD_FT Test Pin - Reserved 1 SPKRD O BD4STRP_FT Speaker Device Output 1

Table 2-2.

Definitio n of Si gn a l Pins

Signal Name Dir Buffer Type

Description Qty

Note

; See

Table 2-3

for buffer type descriptions

Table 2-3.

Buffer Type Descriptions

Buffer Description

ANA Analog pad buffer OSCI13B Oscillator, 13 MHz, HCMOS

BT4CRP LVTTL Output, 4 mA drive capability, Tri-State Control BT8TRP_TC LVTTL Output, 8 mA drive capability, Tri-State Control, Schmitt trigger

BD4STRP_FT LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, 5V tolerant BD4STRUP_FT LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant BD4STRP_TC LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger BD8STRP_FT LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, 5V tolerant BD8STRUP_FT LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant BD8STRP_TC LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger BD8TRP_TC LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger BD8PCIARP_FT LVTTL Bi-Directional, 8 mA drive capability, PCI compatible, 5V tolerant BD14STARP_FT LVTTL Bi-Directional, 14 mA drive capability, Schmitt trigger, IEEE1284 compliant, 5V tolerant BD16STARUQP_TC LVTTL Bi-Directional, 16 mA drive capability, Schmitt trigger

SCHMITT_FT LVTTL Input, Schmitt trigger, 5V tolerant TLCHT_FT LVTTL Input, 5V tolerant TLCHT_TC LVTTL Input TLCHTD_TC LVTTL Input, Pull-Down TLCHTU_TC LVTTL Input, Pull-Up

USBDS_2V5 USB 1.1 compliant pad buffer

VDDCO Analog output pad

PIN DESCRIPTION

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2.2. SIGNAL DESCRIPTIONS

2.2.1. BASIC CLOCKS AND RESETS

SYSRSTI#

System Reset/Power good.

This input is low when the reset switch is depressed. Otherwise, it reflects the power supply’s power good signal. PWGD is asynchronous to all clocks, and acts as a negative active reset. The reset circuit initiates a hard reset on the rising edge of PWGD .

Note that while Reset is being asserted, the signals on the device pins are in an unknown state.

SYSRSTO#

Rese t Outpu t to System .

This is the system reset signal and is used to r eset the rest of the components (not on Host bus) in the system. The ISA bus reset is an externally inverted buffered version of this output and the PCI bus reset is an externally buffered version of this output.

XTALI

14.3 MHz Crystal Input

XTALO

14.3 MHz Crystal Output.

These pins are provided for the connection of an external 14.318 MHz crystal to provide the reference clock for the internal frequency synthesizer, from which the HCLK and CLK24M signals are generated.

PCI_CLKI

33 MHz PCI Input Clock.

This signal must be connected to a clock generator and is usually connected to PCI_CLKO.

PCI_CLKO

33 MHz PCI Output Clock .

This is t h e

master PCI bus clock output.

ISA_CLK

ISA Clock Output (also Multiplexer

Selec t Line For IP C).

This pin produces the Clock signal for the ISA bus. It is also used with ISA_CLK2X as the multiplexer control lines for the Interrupt Controller Interrupt input lines. This is a divided down version of the PCICLK or OSC14M.

ISA_CLKX2

ISA Clock Output (also Multiplexer

Select Line For IPC).

This pin produces a signal at twice the frequency of the ISA bus Clock signal. It is also used with ISA_CLK as the multiplexer control lines for the Interrupt Controller Interrupt input lines.

CLK14M

ISA bus synchronisation clock.

This is

the buffered 14.318 MHz clock to the ISA bus.

HCLK

Host Clock.

This is the host clock. Its frequency can vary from 25 to 66 MHz. All host transactions and PCI transactions are synchronized to this clock. Host transactions executed by the DRA M controller are also driven by this clock.

DEV_CLK

24 MHz Peripheral Clock (floppy

drive).

This 24 MHz signal is provided as a convenience for the system integration of a Floppy Disk driver function in an external chip. This clock signal is not available in Local Bus mode.

DCLK

135 MHz Dot Clock.

This is the dot clock, which drives graphics display cycles. Its frequency can be as high as 135 MHz, and it is required to have a worst case duty cycle of 60-40. For further details, r e fe r to Section 3.1.4. bit 4.

2.2.2. MEMORY INTERFACE

MCLKI

Memory Clock Input.

This clock is driving the SDRAM controller, the graphics engine and display controller. This input should be a buffered version of the MCLKO signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the Me mory Bank s.

MCLKO

Memory Clock Output.

This clock drives the Memory Banks on board and is generated from an internal PLL.

The STPC Atlas MClock signal can run up to 100MHz reliably, but PCB layout is so critical that the maximum guaranteed speed is 90MHz

CS#[1:0]

Chip S elect

These signals are used to disable or enable device operation by masking or enabling all SDRAM inputs except MCLK, CKE, and DQM.

CS#[2]/MA[11]

Chip Select/Bank Address

This pin is CS#[2] in the case when 16-Mbit devices are used. For all other densities, it becomes MA[11].

CS#[3]/MA[12]/BA[1]

Chip Select/ Memory

Address/ Bank Address

This pin is CS#[3] in the case when 16 Mbit devices are used. For all other densities, it becomes MA[12] when 2 internal banks devices are used and BA[1] when 4 internal bank devices are used.

MA[10:0]

Memory Address.

Multiplexed row and

column address lines.

BA[0]

Bank Address.

Internal bank address line.

MD[63:0]

Memory Dat a.

This is the 64-bit memory data bus. This bus is also used as input at the rising edge of SYSRSTI# to latch in power-up configuration information into the ADPC strap registers.

RAS#[1:0]

Row Address Strobe.

There are two active-low row address strobe output signals. The RAS# signals drive the memory devices di re ctly without any external buffering.

PIN DESCRIPTION

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CAS#[1:0]

Column Address Strobe.

There are two active-low column address strobe output signals. The CAS# signals drive the memory devices directly without any external buffering.

MWE#

Write Enable.

Write enable specifies whether the memory access is a read (MWE# = H) or a write (MWE# = L). Th is single write enable controls all DRAMs. The MWE# sign als drive the memory devices directly without any external buffering.

2.2.3. PCI INTERFACE

AD[31:0]

PCI Address/Data.

This is the 32-bit multiplexed address and data bus of the PCI. This bus is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions.

PBE[3:0]#

Bus Commands/Byte Enables.

These are the multiplexed command and Byte enable signals of the PCI bus. During the address phase they define the command and during the data phase they carry the Byte enable information. These pins are inputs when a PCI master other than the STPC Atlas owns the bus and outputs when the STPC Atlas owns the bus.

FRAME#

Cycle Frame.

This is the frame signal of the PCI bus. It is an input when a PCI master owns the bus and is an out put when STPC A tlas owns the PCI bus.

TRDY#

Target Ready.

This is the target ready signal of the PCI bus. It is driven as an output when the STPC Atlas is t he target of the current bus transaction. It is used as an input when STPC Atlas init iates a cycle on the PCI bus.

IRDY#

Initiator Ready.

This is the initiator ready signal of the PCI bus. It is used as an output when the STPC Atlas initiates a bus cycle on the PCI bus. It is used as an input during the PCI cycles targeted to the STPC Atlas to determine when the current PCI master is ready to complete the current tra nsa ction .

STOP#

Stop Transaction.

STOP# is used to implement the disconnect, retry and abort protocol of the PCI bus. It is used as an input for the bus cycles initiated by the STPC Atlas an d is used as an output when a PCI master cycle is t argeted to the STPC Atlas.

DEVSEL#

Device Select.

This signal is used as an input when the STPC Atlas initiates a bus cycle on the PCI bus to det erm ine if a P CI slave device has decoded itself to be the target of the current transaction. It is asserted as an output either when the STPC Atlas is the target of the current PCI transaction or when no other device asserts

DEVSEL# prior to the subtractive decode phase of the current PCI transaction.

PAR

Parity Signal Transactions.

This is the pa rity signal of the PCI bus. This signal is used to guarantee even parity across AD[31:0], CBE[3:0]#, and PAR. Thi s signal is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions. (Its assertion is identical to that of the AD bus delayed by one PCI clock cycle)

PERR#

Parity Error

SERR#

System Error.

This is the system error signal of the PCI bus. It may, if enabled, be asserted for one PCI clock cycle if target aborts a STPC Atlas initiated PCI transaction. Its assertion by either the STPC A tlas or by another PCI bus agent will trigger the assertion of NMI to the host CPU. This is an open drain output.

LOCK#

PCI Lock.

This is the lock signal of the PCI bus and is used to implement the exclusive bus operations when acting as a PCI target agent.

PCI_REQ#[2:0]

PCI Request.

These pins a re t he three external PCI master request pins. They indicates to the PCI arbiter that the external agents desire use of the bus.

PCI_GNT#[2:0]

PCI Grant.

These pins indicate that the PCI bus has been g ranted to the master requesting it on its PCI_REQ#.

PCI_INT#[3:0]

PCI Interrupt Request.

These are the PCI bus interrupt signals. They are to be encoded before connection to the STPC Atlas using ISACLK and ISACLKX2 as the input selection strobes.

2.2.4. ISA BU S INTERFACE

LA[23:17]

Unlatched Address.

These unlatched ISA Bus pins address bits 23-17 on 16-bit devices. When the ISA bus is accessed by any cycle initiated from the PCI bus, these pins are in output mode. When an ISA bus master owns the bus, these pins are tristated.

SA[19:0]

Unlatched Address.

These are the 20 low bits of the system address bus of ISA . These pins are used as an input when an ISA bus master owns the bus and are outputs at all other times.

SD[15:0]

I/O Data Bus (ISA).

These are the

external ISA databus pins.

IOCHRDY

IO Channel Ready.

IOCHRDY is the IO channel ready signal of the ISA bus and is driven as an output in response to an ISA master cycle targeted to the host bus or an internal register of

PIN DESCRIPTION

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the STPC Atlas. The STPC Atlas monitors this signal as an input when performing an ISA cycle on behalf of the host CPU, DMA master or refresh. ISA masters which do not monitor IOCHRDY are not guaranteed to work with the STPC Atlas since the access to the system memory can be considerably delayed due to CRT refresh or a write back cycle.

ALE

Address Latch En able.

This is the address latch enable output of the ISA bus and is asserted by the STPC Atlas to indicate that LA23-17, SA190, AEN and SBHE# signals are valid. The ALE is driven high during refresh, DMA master or an ISA master cycles by the STPC Atl a s. ALE is driven low after reset.

BHE#

System Bus High Enable.

This signal, when asserted, indicates that a data Byte is being transferred on SD15-8 lines. It is used as an input when an ISA master owns the bus and is an output at all other times.

MEMR#

Memory Read.

This is the memory read command signal of the IS A bus. It is used as an input when an ISA master owns the bus and is an output at all other times. The MEMR# signal is active during refresh.

MEMW#

Memory Write.

This is the memory write command signal of the IS A bus. It is used as an input when an ISA master owns the bus and is an output at all other times.

SMEMR#

System Memory Read.

The STPC Atlas generates SMEMR# signal of the ISA bus only when the address is below one MByte or the cycle is a refresh cycle.

SMEMW#

System Memory Write.

The STPC Atlas generates SMEM W# signal of the ISA bus only when the address is below one MByte.

IOR#

I/O Read.

This is the IO read command signal of the ISA bus. It is an input when an ISA master owns the bus an d is an out put at al l other times .

IOW#

I/O Write.

This is the IO write command signal of the ISA bus. It is an input when an ISA master owns the bus an d is an out put at al l other times .

MASTER #

Add On Card Owns Bus.

This signal is active when an ISA device h as been granted bus ownership.

MCS16#

Memory Chip Select16.

This is the decode of LA23-17 address pins of the ISA address bus without any qualification of the command signal lines. MCS16# is always an input. The STPC Atlas ignores this signal during IO and refresh cycles.

IOCS16#

IO Chip Select16.

This signal is the decode of SA15-0 address pins of the ISA address bus without any qualification of the command signals. The STPC Atlas does not drive IOCS16# (similar to PC-AT design). An ISA master access to an internal registe r of the S TPC Atlas is executed as an extended 8-bit IO cycle.

REF#

Refresh Cycle.

This is the refresh command signal of the ISA bus. It is driven as an output when the STPC Atlas performs a refresh c ycle on the ISA bus. It is used as an input when an ISA master owns the bus and is used to trigger a refresh cycle. The STPC Atlas performs a pseudo hidden refresh. It requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. The host bus is then relinquished while the refresh cycle continues on the ISA bus.

AEN

Address Enable.

Address Enable is enab led when the DMA controller is the bus owner to indicate that a DMA transfer will occur. The enabling of the signal indicat es to IO devices to ignore the IOR#/IOW# signal during DMA transfers.

IOCHCK#

IO Channel Che ck.

IO Channel Check is enabled by any ISA device to signal an error condition that can not be corrected. NMI signal becomes active upon seeing IOCHCK# active if the corresponding bit in Port B is enabled.

GPIOCS#

I/O General Purpose Chip Select 1.

This output signal is used by the externa l latch on ISA bus to latch t he data on the SD[7: 0] bus . T he latch can be use by PMU unit to control the external peripheral devices to power down or any other desired function.

RTCRW#

Real Time Clock RW#.

This pin is used as RTCRW#. This signal is asserted for any I/O write to port 71h.

RTCDS#

Real Time Clock DS

. This pin is used as RTCDS#. This signal is asserted for any I/O read to port 71h. Its polarity complies with the DS pin of the MT48T86 RTC device when configured with Intel timings.

RTCAS

Real time clock address strobe.

This

signal is asserted for any I/O write to port 70h.

RMRTCCS#

ROM/Real Time clock chip select.

This pin is a multi-function pin. This signal is asserted if a ROM access is decoded during a memory cycle. It should be combined with MEMR# or MEMW# signals to properly access the ROM. During an IO cycle, this signal is asserted if access to the Real Time Clock (RTC) is decoded. It should be combined with IOR# or IOW# signals to properly access the real time clock.

PIN DESCRIPTION

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IRQ_MUX[3:0]

Multiplexed Interrupt Request.

These are the ISA bus interrupt signals. They are to be encoded before connection to the STPC Atlas using ISACLK and ISACLKX2 as the input selection strobes. Note that IRQ8B, which by convention is connected to the RTC, is inverted before being sent to the interrupt c ontroller, so that it may be connected directly to the IRQ# pin of the RTC.

ISAOE#

Bidirectional OE Control.

This signal

controls the OE

signal of the external transceiver

that connects the IDE DD bus and ISA SA bus.

KBCS#

Keyboard Chip Select.

This signal is asserted if a keyboard access is decoded during a I/O cycle.

ZWS#

Zero Wait State.

This signal, when asserted by addressed device, indicates that current cycle can be shortened.

DACK_ENC[2:0]

DMA Acknowledge.

These are the ISA bus DMA ac knowledge sig nals. They are encoded by the STPC Atlas before output and should be decoded ext ernally using ISACLK and ISACLKX2 as the control strobes.

DREQ_MUX[1:0]

ISA Bus Multiplexed DMA

Request.

These are the ISA bus DMA request signals. They are to be encoded before connection to the S TPC Atlas using I SACLK and ISACLKX2 as the input selection strobes.

ISA Terminal Count.

This is the terminal count output of the DMA controller and is connected to the TC line of the ISA bus. It is asserted during the last DMA transfer, when the Byte count expires.

2.2.5. PCMCIA INTERFACE

RESET

Card Reset.

This output forces a hard

reset to a PC Card.

A[25:0]

Address Bus.

These are the 25 low bits of the system address bus of the PCMCIA bus. These pins are used as an input when an PCMCIA bus owns the bus and are outputs at all other times.

D[15:0]

I/O Data Bus (PCMCIA).

These are the

external PCMCIA databus pins.

IORD#

I/O Read.

This output is used with REG# to gate I/O read data from the PC Card, (only when REG# is asserted).

IOWR#

I/O Write

. This output is used with REG# to gate I/O write data from the PC Card, (only when REG# is asserted).

Write Protect.

This input indicates the status

of the Write Protect switch (if fitted) on memory PC

Cards (asserted when the switch is set to write protect).

BVD1, BVD2

Battery Voltage Detect.

These inputs will be generated by memory PC Cards that include batteries and are an indication of the condition of the batteries. BVD1 and BVD2 are kept asserted high when the battery is in good condition.

READY#/BUSY#/IREQ#

Ready/busy/Interrupt

request.

This in put is driven low by memory PC Cards to signal that their circuits are busy processing a previous write command.

WAIT#

Bus Cycle Wait.

This input is driven by the PC Card to delay completion of the memory or I/O cycle in progress.

OE#

Output Enable.

OE# is an active low output which is driven to the PC Card to gate Memory Read data from memory PC Cards.

WE#/PRGM#

Write Enable.

This output is used by the host for gating Memory Write data. WE# is also used for memory PC Cards that have programmable memory.

REG#

Attribute Memory Select.

This output is inactive (high) for all normal accesses to the Main Memory of the PC Card. I/O PC Cards will only respond to IORD# or IOWR# when REG# is active (low). Also see Section 2.2.7.

CD1#, CD2#

Card Detect.

These inputs provide for the detection of correct card i nsertion. CD#1 and CD#2 are positioned at opposite ends of the connector to assist in the detection process. These inputs are internally grounded on the PC Card therefore they will be force d low whenever a card is inserted in a socket.

CE1#, CE2#

Card Enable

. These are active low output signals provided from the PCIC. CE#1 enables even Bytes, CE#2 odd Bytes.

ENABLE#

Enable.

This output is used to activate/ select a PC Card socket. ENABLE# controls the external address buffer logic.C card has been detected (CD#1 and CD#2 = '0').

ENIF#

ENIF

. This output is used to activate/select

a PC Card socket.

EXT_DIR

EXternal Transceiver Direction Control.

This output is high during a read and low during a write. The default power up condition is write (low). Used for both Low and High Bytes of the Data Bus.

VCC_EN#, VPP1_EN0, VPP1_EN1, VPP 2_EN0, VPP2_EN1

Power Control.

Five output signals

PIN DESCRIPTION

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used to control voltages (VP P1, VPP2 and V CC) to a PC Card socket. Also see Section 13.7 .5 .

GPI#

General Purpose Input. This signal is

hardwired to 1.

2.2.6. LOCAL BUS

PA[24:0]

Address Bus Output.

PD[15:0]

Data Bus.

This is the 16-bit data bus.

D[7:0] is the LSB and PD[15:8] is the MSB.

PRD#[1:0]

Read Control output

. These are memory and I/O Read signals. PRD0 # is used to read the LSB and PRD1# to read the MSB.

PWR#[1:0]

Write Control output.

These are memory and I/O Write signals. PWR0# is used to write the LSB and PWR1# to write the MSB.

PRDY

Data Ready input.

This signal is used to create wait states on the bus. When high, it completes the current cycle.

FCS#[1:0]

Two Flash Memory Chip Select

outputs.

These are the Programmable Chip Select

signals for Flash memory.

IOCS#[7:0]

I/O Chip Select output.

These are the Programmable Chip Select signals for up to 4 external I/O devices.

PBE#[1:0]

Byte Enable.

These are the Byte enables that ident ifies on wh ich data bus the date is valid. PBE#[0] corresponds to PD[7:0] and PBE#[1] corresponds to PD[15:8]. These are normally used when 8 bit transfers are transfered across the 16 bit bus.

IRQ_MUX#[3:0]

Multiplex e d Interrupt Lin es.

2.2.7. IPC

DACK_ENC[2:0]

DMA Acknowledge.

These are the ISA bus DMA ac knowledge sig nals. They are encoded by the STPC Industrial before output and should be decoded ext ernally using ISACLK and ISACLKX2 as the control strobes.

DREQ_MUX[1:0]

ISA Bus Multiplexed DMA

Request.

These are the ISA bus DMA request signals. They are to be encoded before connection to the STPC Industrial using ISACLK and ISACLKX2 as the input selection strobes.

ISA Terminal Count.

This is the terminal count output of the DMA controller and is connected to the TC line of the ISA bus. It is asserted during the last DMA transfer, when the Byte count expires.

2.2.8. IDE INTERFACE

DA[2:0]

Address.

These signals are connected to DA[2:0] of IDE devices directly or through a buffer. If the toggling of sign als are t o be m asked du ring ISA bus cycles, they can be externally ORed with ISAOE# before being connected to the IDE devices.

DD[15:0]

Databus.

When the IDE bus is active, they serve as IDE signals D D[11:0]. IDE devices are connected to SA[19:8] directly and ISA bus is connected to these pins through two LS245 transceivers.

PCS1, PCS3, SCS1, SCS3

Primary & Secondary

Chip Selects.

These signals are used as the active high primary and secondary master & slave IDE chip select signals. These signals must be externally NANDed with the ISAOE

signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. In Local Bus mode, they just need to be inverted.

DIORDY

Busy/Ready.

This pin serves as IDE

signal DIORDY.

PIRQ

Primary Interrupt Request.

SIRQ

Secondary Interrupt Request.

Interrupt request from IDE channels.

PDRQ

Primary DMA Request.

SDRQ

Secondary DMA Request.

DMA request from IDE channels.

PDACK#

Primary DMA Acknowledge.

SDACK#

Secondary DMA Acknowledge.

DMA acknowledge to IDE channels.

PDIOR#, PD IOW#

Primary I/O Read & Write.

SDIOR#, SD IOW#

Secondary I/O Read & Write

Primary & Secondary channel read & write.

2.2.9. MONITOR INTERFACE

RED, GREEN, BLUE

RGB Video Outputs.

These are the 3 analog colour outputs from the RAMDACs. These signals are sensitive to interference, therefore they need to be properly shielded.

VSYNC

Vertical Synchronisation Pulse.

This is the vertical synchronization signal f rom the VGA controller.

HSYNC

Horizontal Synchronisation Pulse.

This is the horizontal synchronization signal from the VGA controller.

VREF_DAC

DAC Voltage reference.

This pin is an input driving the digital to analog converters. This allows an external voltage ref erence source to be used.

PIN DESCRIPTION

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RSET

Resistor Current Set.

This is the reference current input to the RAMDAC. Used to set the fullscale output of the RAMDAC.

COMP

Compensation.

This is the RAMDAC compensation pin. Normally, an external capacitor (typically 10nF) is connected between this pin and V

to damp oscillations.

DDC[1:0]

Direct Data Channel Serial Link.

These bidirectional pins are connected to CRTC register 3Fh to implement DDC capabilities. They conform to I

C electrical specifications, they have opencollector output drivers which are internally connected to V

through pull-up resistors.

They can instead be used for accessing I²C devices on board. DDC1 and DDC0 correspond to SCL and SDA respectively.

2.2.10. VIDEO INTERFACE

VCLK

Pixel Clock Input.

This signal is used to synchronise data being transferred from an external video device to either the frame buffer, or alternatively out the TV output in bypass mode. This pin can be sourced from STP C i f n o exte rnal VCLK is detected, or can be input from an external video clock source.

VIN[7:0]

YUV Video Data Input ITU-R 601 or 656.

Time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and Rec656 (except for TTL input levels). This bus typically carries a stream of Cb,Y,Cr,Y digital video at VCLK frequency, clocked on the rising edge (by default) of VCLK.

VCS

Line synchronisation Input.

This is the horizontal synchronisation of the incomming CCIR601 video. The signal is synchronous to rising edge of VCLK.

ODD_EVEN

Frame Synchronisat ion O utput.

This is the vertical synchronisation of the incomming CCIR601 video. The signal is synchronous to rising edge of VCLK. The default polarity for this pin is:

- odd (not-top) field: LOW level

- even (bottom) field: HIGH level

2.2.11. TFT INTERFACE SIGNALS

The TFT (Thin Film Transistor) interface converts signals from the CRT controller into control signals for an external TFT Flat Panel. The signals are listed below.

TFTFRAME,

Vertical Sync. pulse Output.

TFTLINE ,

Horizontal Sync. Pulse Output.

TFTDE,

Data Enable.

TFTR5-0,

Red Output.

TFTG5-0,

Green Output.

TFTB5-0,

Blue Output

TFTENVDD,

Enable VDD of Flat Panel.

TFTENVCC,

Enable VCC of Flat Panel.

PWM

PWM Back-Light Control.

This PWM is

clocked by the PCI clock.

TFTDCLK,

Dot clock for the Flat Panel.

2.2.12. USB INTERFACE

OVER CURRENT DETECT

This signal is used to monitor the status of the USB power supply lines of both devices. USB port are disabled when OC signal is asserted.

USBDPL0, USBDMNS0

UNIVERSAL SERIAL

BUS DATA 0

This signal pair comprises the

differential data signal for USB port 0.

USBDPL1, USBDMNS1

UNIVERSAL SERIAL

BUS PORT 1

This signal pair comprises the

differential data signal for USB port 1.

POWERON

USB power supply lines

2.2.13. SERIAL INTERFACE

RXD0, RXD1

Serial Input.

Data is clocked in using

RCLK/16.

TXD0, TXD1

Serial Output.

Data is clocked out

using TCLK/16 (TCLK=BAUD#).

DCD0#, DCD1#

Input Data carrier detect.

RI0#, RI1#

Input Ring indicator.

DSR0#, DSR1#

Input Data set ready.

CTS0#, CTS1#

Input Clear to send.

RTS0#, RTS1#

Output Request to send.

DTR0#, DTR1#

Output Data terminal read.

2.2.14. KEYBOARD/MOUSE INTERFACE

KBCLK,

Keyboard Clock line.

Keyboard data is latched by the controller on each negat ive clock edge produced on this pi n. The keyboard c an be disabled by pulling this pin low by software control.

KBDATA,

Keyboard Data Line.

11-bits of data are shifted serially through this line when data is being transferred. Data is synchronised to KBCLK.

PIN DESCRIPTION

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MCLK,

Mouse Clock line.

Mouse data is latched by the controller on each negative clock edge produced on this pin. The mouse can be disabl ed by pulling this pin low by software control.

MDATA,

Mouse Data Line.

11-bits of data are shifted serially through this line when data is being transferred. Data is synchronised to MCLK.

2.2.15. PARALLEL PORT

Paper End.

Input status signal from printer.

SLCT

Printer Se l ect.

Printer selected input.

BUSY#

Printer Busy

Input status signal from printer.

ERR#

Error

. Input status signal from printer.

ACK#

Acknowledge.

Input status signal from printer.

PDDIR#

Parallel Device Direction.

Bidirectional control line output.

STROBE#

PCS/Strobe#.

Data transfer strobe line to printer.

INIT#

Initialize Printer.

This output sends an

initialize command to the connected printer.

AUTOFD#

Automatic Line feed.

This output sends a command to the connected printer to automatically generate line feed on received carriage returns.

SLCTIN#

Select In.

Printer sele ct ou tp u t.

PPD[7-0]

Parallel Port Data Lines

Data transfer

lines to printer. Bidirectional depending on modes.

2.2.16. MISCELLANEOUS

SPKRD

Speaker Drive.

This is the output to the speaker and is the AND of the counter 2 output with bit 1 of Port 61h and drives an external speaker driver. This output should be c onnected to a 7407 type high voltage driver.

SCAN_ENABLE

Reserved

. This pin is reserved for Test and Miscellaneous functions. It has to be set to ‘0’ or connected to ground in normal operation.

COL_SEL

Colour Select.

Can be used for Picture in Picture function. Note however that this signal, brought out from the video pipeline, is not in sync with the VGA output signals, i.e. the VGA si gnals run four clock cycles after th e Col_ Sel si gnal .

2.2.17. JTAG INTERFACE

TCLK

Test clock

TDI

Test data input

TMS

Test mode input

TDO

Test data output

TRST

Test reset input

PIN DESCRIPTION

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2.3. SIGNAL DETAIL

The muxing between ISA, LOCAL BUS and PCMCIA is performed by external strap options.

The resulting interface is then d yn amica lly mux ed with the IDE Interface.

Table 2-4.

Multiplexed Signals (on the same pin)

IDE Pin Name ISA Pin Name PCMCIA Pin Names Local Bus Pin Name

DIORDY IOCHRDY DA[2] LA[19]

= 0

DA[1:0] LA[18:17] A[25:24 ] SCS3,SCS1 LA[23:22] A[23:22 ] PCS3,PCS1 LA[21:20] A[21:20 ] DD[15] RMRTCCS# ROMCS# DD[14] KBCS#

Hi-Z

DD[13:12] RTCRW#, RTCDS#

Hi-Z

DD[11:0] SA[19:8] A[19:8]

SD[15:0] D[15:0] PD[15:0] RTCAS

= 0

FCS0# DEV_CLK DEV_C LK FCS1# SA[3] A[3] PRDY SA[2:0] A[2:0] IOCS#[2:0] SMEMW# VPP_PGM PBE#[1] IOCS16# WP/IOIS16# PBE #[0] MASTER# BVD1 PRD # MCS16#

= 0

PWR# DACK_ENC [2:0]

= 0x04

PA[2:0] TC

= 0

PA[3] SA[7:4] A[7:4] PA[7:4] ZWS# GPI# PA[8] GPIOCS# VCC5_E N PA[ 9] IOCHCK# BVD2 PA[ 10] REF# RESET PA[11] IOW# IOWR# PA[ 12] IOR# IORD# PA[13] MEMR#

= 0

PA[14] ALE

= 0

PA[15] AEN WAIT# PA[16] BHE# OE# PA[17] MEMW#

= 0

PA[18] SMEMR# VCC3_E N PA[ 19] DREQ_MUX#[1:0] CE2#, CE1# PA[21:20]

Hi-Z Hi-Z

PA[22]

Hi-Z

VPP_VCC PA[23]

Hi-Z

WE# PA[24]

Hi-Z

REG# IOCS#[7]

Hi-Z

READY# IOCS#[6]

Hi-Z

CD1#, CD2# IOCS#[5], IOCS#[4]

ISAOE# = 1 ISAOE# = 0 ISAOE# = 0 IOCS#[3]

PIN DESCRIPTION

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Table 2-5.

Signal val ue on Reset

Signal Name SYSRSTI# active

SYSRSTI# inactive

SYSRSTO# active

release of SYSRSTO#

BASIC CLOCKS AND RESETS

XTALO 14MHz ISA_CLK Low 7MHz ISA_CLK2X 14MHz OSC14M 14MHz DEV_CLK 24MHz HCLK Oscillating at the speed defined by the strap options. PCI_CLKO HCLK divided by 2 or 3, depending on the strap options. DCLK 17MHz

MEMORY CONTROLLER

MCLKO 66MHz if asynchonous mode, HCLK speed if synchronized mode. CS#[3:1] High CS#[0] High

SDRAM init sequence: Write Cycles

MA[10:0], BA[0] 0x00 RAS#[1:0], CAS#[1:0] High MWE#, DQM[7:0] High MD[63:0] Input

PCI INTERFACE

AD[31:0] 0x0000

First prefetch cycles when not in Local Bus mode.

CBE[3:0], PAR Low FRAME#, TRDY#, IRDY# Input STOP#, DEVSEL# In put PERR#, SERR# Input PCI_GNT#[2:0 ] Hi gh

ISA BUS INTERFACE

ISAOE# High Low RMRTCCS# Hi-Z

First prefetch cycles when in ISA or PCMCIA mode.

Address start is 0xFFFFF0

LA[23:17] Unknown 0x00 SA[19:0] 0xFFFXX 0xFFF03 SD[15:0] Unknown 0xFF BHE#, MEMR# Unknown High MEMW#, SMEMR#, SMEMW#, IOR#, IOW# Unknown High REF# Unknown High ALE, AEN Low DACK_ENC[2:0] Input 0x04 TC Input Low GPIOCS# Hi-Z High RTCDS#, RTCRW#, KBCS# Hi-Z RTCAS Unknown Low

PCMCIA INTERFAC E

RESET Un know n High A[23:0] Unknown 0x00

First prefetch cycles using RMRTCCS#

D[15:0] Unknown 0xFF IORD#, IOWR#, OE# Unknown High WE#, REG# High CE2#, CE1#, VCC5_EN, VCC3_EN High VPP_PGM, VPP_VCC Low

LOCAL BUS INTERFACE

PA[24:0] Unknown

First prefetch cycles

PD[15:0] Unknown 0xFF PRD# Unknown High PBE#[1:0], FCS0#, FCS_0H# High

PIN DESCRIPTION

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FCS_0L#, FCS1#, FCS_1H#, FCS_1L# High PWR#, IOCS#[7:0] High

IDE CONTROLLER

DD[15:0] 0xFF DA[2:0] Unknown Low PCS1, PCS3, SCS1, SCS3 Unknown Low PDACK#, SDACK# High PDIOR#, PDIOW#, SDIOR#, SDIOW# High

VGA CONTROLLER

RED, GREEN, BLUE Black VSYNC, HSYNC Lo w COL_SEL Unknown

I2C INTERFACE

SCL / DDC[1] Input SDA / DDC[0] Input

TFT INTERFACE

TFT[R,G,B][5:0] 0x00,0x00,0x00 TFTLINE, TFTFRAME Low TFTDE, TFTENVDD, TFTENVCC, TFTPWM Low TFTDCLK Oscillating at DCLK speed

USB INTERFACE

USBDPLS[1:0]

Low

USBDMNS[1:0]

High

POWERON

Unknown Low

SERIAL CONTROLL ER

TXD0, RTS0#, DTR0# High TXD1, RTS1#, DTR1# High

KEYBOARD & MOUSE INTERFACE

KBCLK, MCLK Low KBDATA, MDATA Input

PARALLEL PORT

PDIR#, INIT# Low STROBE#, AUTOFD# High SLCTIN# Unknown Low PPD[7:0] Unknown 0x00

GPIO SIGNALS

GPIO[15:0] High

JTAG

TDO High

MISCELLANEOUS

SPKRD Low

Table 2-5.

Signal val ue on Reset

Signal Name SYSRSTI# active

SYSRSTI# inactive

SYSRSTO# active

release of SYSRSTO#

PIN DESCRIPTION

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Table 2-6.

Pinout

Pin# Pin Name

D15 SYSRSETI# C15 SYSRSETO# AF21 XTALI AF22 XTALO AF23 PCI_CLKI AF24 PCI_CLKO E15 ISA_CLK A16 ISA_CLK2X AB18 OSC14M AB24 HCLK AB25 DEV_CLK

/FCS1#

AC18 DCLK

AF20 MCLKI AF19 MCLKO U5 MA[0] V1 MA[1] V2 MA[2] V3 MA[3] V4 MA[4] V5 MA[5] W1 MA[6] W2 MA[7] W3 MA[8] W5 MA[9] Y1 MA[10] Y2 BA[0] U3 RAS#[0] U4 RAS#[1] R5 CAS#[0] T1 CAS#[1] R4 MWE# J4 MD[0] J2 MD[1] K5 MD[2] K3 MD[3] K1 MD[4] L4 MD[5] L2 MD[6] M5 MD[7] M3 MD[8] M1 MD[9] N4 MD[10] N2 MD[11] P1 MD[12] P3 MD[13] P5 MD[14] R2 MD[15] AA4 MD[16] AB1 MD[17]

Note

; This signal is multiplexed

see

Table 2-4

AB3 MD[18] AC1 MD[19] AC3 MD[20] AD2 MD[21] AF3 MD[2 2] AE4 MD[23] AF4 MD[2 4] AD5 MD[25] AF5 MD[2 6] AC6 MD[27] AF6 MD[2 8] AC7 MD[29] AE7 MD[30] AB8 MD[31] J3 MD[32] J1 MD[33] K4 MD[34] K2 MD[35] L5 MD[36] L3 MD[37] L1 MD[38] M4 MD[39] M2 MD[40] N5 MD[41] N3 MD[42] N1 MD[43] P2 MD[44] P4 MD[45] R1 MD[46] R3 MD[47] AA5 MD[48] AB2 MD[49] AB4 MD[50] AC2 MD[51] AD1 MD[52] AE3 MD[53] AD4 MD[54] AC5 MD[55] AB6 MD[56] AE5 MD[57] AB7 MD[58] AD6 MD[59] AE6 MD[60] AD7 MD[61] AF7 MD[6 2] AC8 MD[63] U1 CS#[0] U2 CS#[1] Y3 CS#[2]/MA[11] Y4 CS#[3]/MA[12]/BA[1 ] T2 DQM[0]

Table 2-6.

Pinout

Pin# Pin Name

Note

; This signal is multiplexed

see

Table 2-4

T4 DQM[1] Y5 DQM[2] AA2 DQM[3] T3 DQM[4] T5 DQM[5] AA1 DQM[6] AA3 DQM[7]

B3 AD[0] A3 AD[1] C4 AD[2] B4 AD[3] A4 AD[4] D5 AD[5] C5 AD[6] B5 AD[7] A5 AD[8] D6 AD[9] C6 AD[10] B6 AD[11] A6 AD[12] E7 AD[13] D7 AD[14] C7 AD[15] A9 AD[16] E10 AD[17] C10 AD[18] B10 AD[19] A10 AD[20] E11 AD[21] D11 AD[22] C11 AD[23] A11 AD[24] E12 AD[25] D12 AD[26] C12 AD[27] B12 AD[28] A12 AD[29] E13 AD[30] D13 AD[31] E6 CBE[0] B7 CBE[1] B9 CBE[2] B11 CBE[3] C9 FRAME# E9 TRDY# D9 IRDY# B8 STOP# A8 DEVSEL# A7 PAR D8 PERR#

Table 2-6.

Pinout

Pin# Pin Name

Note

; This signal is multiplexed

see

Table 2-4

PIN DESCRIPTION

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E8 SERR# C8 LOCK# C14 PCI_REQ#[0] B14 PCI_REQ#[1] A14 PCI_REQ#[2] A13 PCI_GNT#[0] B13 PCI_GNT#[1] C13 PCI_GNT#[2]

C20 LA[17]

B21 LA[18]

B20 LA[19]

E19 LA[20]

E18 LA[21]

C21 LA[22]

D19 LA[23]

P22 SA[0]

P23 SA[1]

P24 SA[2]

P25 SA[3]

P26 SA[4]

N26 SA[5]

N25 SA[6]

N24 SA[7]

N23 SA[8]

N22 SA[9]

M26 SA[10]

M25 SA[11]

M24 SA[12]

M23 SA[13]

M22 SA[14]

L26 SA[15]

L25 SA[16]

L24 SA[17]

L23 SA[18]

L22 SA[19]

K24 SD[0]

J26 SD[1]

J25 SD[2]

J24 SD[3]

K23 SD[4]

K22 SD[5]

H26 SD[6]

H25 SD[7]

H24 SD[8]

G26 SD[9]

G25 SD[10]

G24 SD[11]

J22 SD[12]

J23 SD[13]

F26 SD[14]

Table 2-6.

Pinout

Pin# Pin Name

Note

; This signal is multiplexed

see

Table 2-4

F25 SD[15]

F23 IOCHRDY

D20 ALE

K25 BHE#

F24 MEMR#

A22 MEMW#

G23 SMEMR#

E21 SMEMW#

H22 IOR#

E26 IOW#

E25 MASTER#

E24 MCS16#

C22 IOCS 16#

G22 REF#

E17 AEN

A23 IOCHCK#

U25 RTCR W#

U26 RTCD S#

U24 RTCA S1/FCS0# U23 RMRT CCS #

D22 GPIO CS#

D24 IRQ_M UX[ 0] E23 IRQ_MUX[1] C26 IRQ_M UX[ 2] F22 IRQ_MUX[ 3] A24 DACK_ENC[0] C23 DACK _ENC [1]

B23 DACK_ENC[2]

D26 DREQ _MU X[0]

D25 DREQ _MU X[1]

B24 TC

B15 PCI_INT#[0] A15 PCI_INT#[1] E14 PCI_INT#[2] D14 PCI_I NT#[3 ] B16 ISAOE#

B22 KBCS#

K26 ZWS#

R23 PIRQ R24 SIRQ T22 PDRQ T23 SDRQ R25 PDAC K# R26 SDAC K# T25 PDIOR# T24 PDIOW# R22 SDIO R# T26 SDIOW#

D18 PA[22 ]

Table 2-6.

Pinout

Pin# Pin Name

Note

; This signal is multiplexed

see

Table 2-4

C19 PA[23] B19 PA[24] A17 FCS_0H B17 FCS_0L C16 FCS_1H E16 FCS_1L D17 IOCS#[4] C18 IOCS#[5] B18 IOCS#[6] C17 IOCS#[7]

AD8 RED AF8 GREEN AC9 BLUE AB10 VSYNC AF9 HSYNC AB9 VREF_DAC AD9 RSET AE8 COMP AE9 VDD_DAC AC10 VSS_DAC

AB15 VCLK AF16 VIN[0] AE16 VIN[1] AC16 VIN[2] AB16 VIN[3] AF17 VIN[4] AE17 VIN[5] AD17 VIN[6] AB17 VIN[7] AD18 ODD_EVEN# AF18 VCS

AE10 TFTR0 AF10 TFTR1 AB11 TFTR2 AD11 TFTR3 AE11 TFTR4 AF11 TFTR5 AB12 TFTG0 AC12 TFTG1 AD12 TFTG2 AE12 TFTG3 AF12 TFTG4 AB13 TFTG5 AC13 TFTB0 AD13 TFTB1 AE13 TFTB2 AF13 TFTB3 AF14 TFTB4

Table 2-6.

Pinout

Pin# Pin Name

Note

; This signal is multiplexed

see

Table 2-4

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