SGS Thomson Microelectronics STPCI01 Datasheet
STPC INDUSTRIAL
PC Compatible Embedded Microprocessor
1/555/11/99
Issue 1.1
ISA
I/F
Figure 1. Logic Diagram
■ POWERFUL X86 PROCESSOR
■ 64-BIT BUS ARCHITECTURE
■ 64-BIT 66MHz DRAM CONTROLLER
■ SVGAGRAPHICS CONTROLLER
■ 135MHz RAMDAC
■ UMA ARCHITECTURE
■ TFT DISPLAY CONTROLLER
■ PCI MASTER / SLAVE / ARBITER
■ LOCAL BUS INTERFACE
■ ISA (MASTER/SLAVE) INTERFACE
-INCLUDING THE IPC
■ PC-CARD INTERFACE
- PCMCIA
- CARDBUS
■ I/O FEATURES
- PC/AT+ KEYBOARD CONTROLLER
- PS/2 MOUSE CONTROLLER
- 2 SERIAL PORTS
- 1 PARALLEL PORT
■ IPC
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
■ POWER MANAGEMENT
STPC INDUSTRIAL OVERVIEW
The STPC Industrial integrates a fully static x86
processor, fully compatiblewithstandardfifthgeneration x86 processors,and combines it with powerful chipset, graphics, TFT, PC-Card, Local Bus,
keyboard, mouse, serials andparallelinterfacesto
provide a single Industrial oriented PC compatible
subsystem ona single device.The performanceof
the device is comparable with the performance of
a typical P5 generation system.
The device is packaged in a 388 Plastic Ball Grid
Array (PBGA).
TFT
ext
x86
Core
Host I/F
Serial2
// Port
Serial1
Kbd
Mouse
DRAM
I/F
VGA
GE
PCI
m/s
Local
Bus I/F
PCMCIA
CARDBUS
PCI BUS
IPC
82C206
PCI
CONTROLLER
ISA BUS
CRTC
HW Cursor
Monitor
TFT Output
SYNC Output
TFT I/F
PBGA388
STPC INDUSTRIAL
2/55
Issue 1.1
■ X86 Processor core
■ Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.
■ Access up to 4GB of external memory.
■ 8Kbyte unified instruction and data cache
with write back capability.
■ Parallelprocessing integral floating point unit,
with automatic power down.
■ Clock core speeds up to 100 MHz.
■ Fully static design for dynamic clock control.
■ Low power and system management modes.
■ Optimized design for3.3V operation.
■ DRAM Controller
■ Integrated system memory and graphic frame
memory.
■ Supports up to 128-MByte system memory in
4 banks and down to as little as 2Mbytes.
■ Supports 4-MByte, 8-MByte, 16-MByte, and
32-MByte single-sided and double-sided
DRAM SIMMs.
■ Four quad-word write buffers for CPU to
DRAM and PCI to DRAM cycles.
■ Four quad-word read prefetch buffers for PCI
masters.
■ Supports Fast Page Mode & EDO DRAMs.
■ Programmable timing for DRAM parameters
including CAS pulse width, CAS pre-charge
time, and RAS to CAS delay.
■ 60, 70, 80 & 100ns DRAM speeds.
■ Memory hole between 1 MByte & 8 MByte
supported for PCI/ISA busses.
■ Hidden refresh.
■ Graphics Controller
■ 64-bit windows accelerator.
■ Complete backward compatibility to VGA and
SVGAstandards.
■ Hardware acceleration for text (generalized
bit map expansion), bitblts, transparent blts
and fills.
■ Up to 64 x 64 bit graphics hardware cursor.
■ Up to 4MB long linear frame buffer.
■ 8, 16, 24 and 32 bit pixels.
■ Drivers for Windows and other operating
systems.
■ CRT Controller
■ Integrated 135MHz triple RAMDAC allowing
for 1280 x 1024 x 75Hz display.
■ Requires external frequency synthesizer and
reference sources.
■ 8, 16,24 and 32-bit pixels.
■ Interlaced or non-interlaced output.
■ TFT Interface
■ Programmable panel size up to 1024 by 1024
pixels.
■ Support for 640 x 480, 800 x 600 & 1024 x
768 active matrix TFT flat panels with 9, 12,
18-bit interface.
■ Support 1 & 2 Pixels per Clock.
■ Programmable image positionning.
■ Programmable blank space insertion in text
mode.
■ Programmable horizontal and vertical image
expansion in graphic mode.
■ A fully programmable PWM (Pulse Width
Modulator) signals to adjust the flat panel
brightness and contrast.
■ Supports PanelLink
TM
high speed serial
transmitter externally for high resolution
panel interface.
■ PCI Controller
■ Fully compliant with PCI Version 2.1
specification.
■ Integrated PCI arbitration interface. Up to 3
masters can connect directly. External PAL
allows for greater than 3 masters.
■ Translation of PCI cycles to ISA bus.
■ Translation of ISA master initiated cycle to
PCI.
■ Support for burst read/write from PCImaster.
■ 0.33X and 0.5X CPU clock PCI clock.
■ Local Bus interface
■ 66MHz, low latency bus.
■ Asynchronous / synchronous.
■ 22-bit address and 16-bit data busses.
■ 2 Programmable Flash EPROM Chip Select.
■ 4 Programmable I/O Chip Select.
■ Separate memory and I/O address spaces.
■ Memory prefetch (improved performances).
STPC INDUSTRIAL
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Issue 1.1
■ ISA master/slave
■ Generation of the ISA clock from either
14.318MHz oscillator clock or system clock
■ Programmable extra wait state for ISA cycles
■ Supports I/O recovery time for back to back
I/O cycles.
■ Fast Gate A20 and Fast reset.
■ Supports the single ROM that C, D, or E.
blocks shares with F blockBIOS ROM.
■ Supports flash ROM.
■ Supports ISA hidden refresh.
■ Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host bus.
NSP compliant.
■ PC-Card interface
■ Support one PCMCIA 2.0 / JEIDA 4.1 68-pin
standard PC Card Socket.
■ Power Management support.
■ Support PCMCIA/ATA specifications.
■ Support I/O PC Card with pulse-mode
interrupts.
■ Provides an ExCA
TM
implementation to
PCMCIA 2.0 / JEIDA 4.1 standards.
■ DMA support.
■ Keyboard interface
■ Fully PC/AT&compatible
■ Mouse interface
■ Fully PS/2 compatible
■ Serial interface
■ 15540 compatible
■ Programmable word length, stop bits, parity.
■ 16-bit programmable baud rate generator.
■ Interrupt generator.
■ Loop-back mode.
■ 8-bit scratch register.
■ Two 16-bit FIFOs.
■ Two DMA handshake lines.
■ Parallel port
■ Standard Centronics mode supported.
■ Nibblemode supported.
■ Integrated Peripheral Controller
■ Two 8237/AT compatible 7-channel DMA
controllers.
■ Two 8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
■ Three 8254 compatible Timer/Counters.
■ Co-processor error support logic.
■ Power Management
■ Four power saving modes: On, Doze,
Standby, Suspend.
■ Programmable system activity detector
■ Supports SMM.
■ Supports IO trap & restart.
■ Independent peripheral time-out timer to
monitor hard disk, serial & parallel ports.
■ Supports APM
■ Supports RTC,interrupt and DMA wake ups
ExCA is a trademark of PCMCIA / JEIDA.
PanelLink is a trademark of SiliconImage, Inc
GENERAL DESCRIPTION
4/55
Issue 1.1
1 GENERAL DESCRIPTION
At the heart of the STPC Industrial is an
advanced 64-bit processor block, dubbed the
5ST86. The 5ST86 includes a powerful x86
processor core along with a 64-bit DRAM
controller, advanced 64-bit accelerated graphics
and video controller, a high speed PCI local-bus
controller and Industry standard PC chip set
functions (Interrupt controller, DMA Controller,
Interval timer and ISA bus).
The STPC Industrial has in addition to the 5ST86
a TFT output, a Local Bus interface, PC Card and
super I/O features.
The STPC Industrial makes use of a tightly
coupled Unified Memory Architecture (UMA),
where the same memory array is used for CPU
main memory and graphics frame-buffer. This
means a reduction in total system memory for
system performances that are equal to that of a
comparable frame buffer and system memory
based system, and generally much better, due to
the higher memory bandwidth allowed by
attaching the graphics engine directly to the 64-bit
processor host interface running at the speed of
the processor bus rather than the traditional PCI
bus.
The 64-bit wide memory array provides the
system with 320MB/s peak bandwidth, double
that of an equivalent system using 32 bits. This
allows for higher resolution screens and greater
color depth. The processor bus runs at 66Mhz
further increasing “standard” bandwidth by at
least a factor of two.
The ‘standard’ PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated together with the x86
processor core; additional functions such as
communication ports are accessed by the STPC
Industrial via an internal ISA bus.
The PCI bus is the main data communication link
to the STPC Industrial chip. The STPC Industrial
translates appropriate host bus I/O and Memory
cycles onto the PCI bus. It also supports the
generation of Configuration cycles on the PCI
bus. The STPC Industrial, as a PCI bus agent
(host bridge class), fully complies with PCI
specification 2.1. The chip-set also implements
the PCI mandatory header registers in Type0 PCI
configuration space for easy porting of PCI aware
system BIOS. The device contains a PCI
arbitration function for three external PCI devices.
Graphics functions are controlled through the onchip SVGA controller and the monitor display is
produced through the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include
hardware acceleration of text, bitblts, transparent
blts and fills. The results of these operations
change the contents of the on-screen or offscreen frame buffer areas of DRAM memory. The
frame buffer can occupy a space up to 4 Mbytes
anywhere in the physical main memory.
The maximum graphics resolution supported is
1280x1024 in 65536 colours at 75Hz refresh rate
and is VGA and SVGA compatible. Horizontal
timing fields areVGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.
To generate the TFT output, the STPC Industrial
extracts the digital video stream before the
RAMDAC and reformats it to the TFT format. The
height and width of the flat panel are
programmable through configuration registers up
to a size of 1024 by 1024.
By default, lower resolution images cover only a
part of the larger TFT panel. The STPC Industrial
allows to expand the image vertically and
horizontally in text mode by inserting
programmable blank pixels. It allows expantion of
the image vertically and horizontally in graphics
mode by replicating pixels. The replication of J
times every K pixel is independently
programmable in the vertical and horizontal
directions.
PanelLinkTMis a proprietary interconnect
protocol defined by Silicon Image, Inc. It consists
of a transmitter that takes parallel video/graphics
data from the host LCD graphics controller and
transmits it serially at high speed to the receiver
which controls the TFT panel. The TFT interface
is designed to support the connection of this
control signal to the PanelLinkTMtransmitter.
The STPC Industrial CARDBUS / PCMCIA
controller has been specifically designed to
provide the interface with PC-Cards which contain
additional memory or I/O and provides an
ExCATMimplementation to PCMCIA 2.0 / JEIDA
4.1 standards.
The power management control facilities include
socket power control, insertion/removal capability,
power saving with Windows inactivity, NCS
controlled Chip Power Down, together with further
controls for 3.3v suspend with Modem Ring
Resume Detection.
GENERAL DESCRIPTION
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Issue 1.1
The need for system configuration jumpers is
eliminated by providing address mapping support
for PCMCIA 2.0 / JEIDA 4.1 PC-Card memory
together with address windowing support for I/O
space.
Selectable interrupt steering from PC-Card to
internal system bus is also provided.
The STPC Industrial implements a multi-function
parallel port. The standard PC/AT compatible
logical address assignments for LPT1, LPT2 and
LPT3 are supported.
The parallel port can be configured for any of the
following 3 modes and supports the IEEE
Standard 1284 parallel interface protocol
standards as follow:
-Compatibility Mode (Forward channel, standard)
-Nibble Mode (Reverse channel, PC compatible)
-Byte Mode (Reverse channel, PS/2 compatible)
The STPC Industrial BGA package has 388 balls,
but this is not sufficient for all the integrated
functions, therefore some features are sharing the
same balls and can not be used at the same time.
The STPC Industrial configuration is done by
‘strap options’. It is a set of pull-up or pull-down
resistors on the memory data bus, checked on
reset, which auto-configure the STPC Industrial.
We can distinguish three main blocks
independently configurables
: The ISA / Local
Bus block, the Serial 1 / TFT block, and the PCI /
PC Card block.
From the first block,we can activateeither the ISA
bus and some IPC additionnal features, or the
Local bus, the parallel port and the second serial
interface.
From the second block, we can activate either the
first serial port, or the TFT extension to get from 4
bit per colour to 6 bit per colour.
From the third block, we can activate either the
PCI bus, or the PC Card interface (CardBus/
PCMCIA/ZoomVideo).
The STPC Industrial core is compliant with the
Advanced Power Management (APM)
specification to provide a standard method by
which the BIOS can control the power used by
personal computers. The Power Management
Unit module (PMU) controls the power
consumption providing a comprehensive set of
features that control the power usage and
supports compliance with the United States
Environmental Protection Agency’s Energy Star
Computer Program. The PMU provides following
hardware structures to assist the software in
managing the power consumption by the system.
- System Activity Detection.
- 3 power-down timers detecting system inactivity:
- Doze timer (short durations).
- Stand-by timer (medium durations).
- Suspend timer (long durations).
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of
house-keepingactivity while dozing or in stand-by
state.
- Peripheral activity detection.
- Peripheral timer detecting peripheral inactivity
- SUSP# modulation to adjust the system
performance in various power down states of the
system including full power on state.
- Power control outputs to disable power from
different planes of the board.
Lack of system activity for progressively longer
periods of time is detected by the three power
down timers. These timers can generate SMI
interrupts to CPU so that the SMM software can
put the system in decreasing states of power
consumption. Alternatively, system activity in a
power down state can generate SMI interrupt to
allow the software to bring the system back up to
full power on state. The chip-set supports up to
three power down states described above, these
correspond to decreasing levels ofpower savings.
Power down puts the STPC Industrial into
suspend mode. The processor completes
execution of the current instruction, any pending
decoded instructions and associated bus cycles.
During the suspend mode, internal clocks are
stopped. Removing power down, the processor
resumes instruction fetchingand begins execution
in the instruction stream at the point it had
stopped. Because of the static nature of the core,
no internal data is lost..
GENERAL DESCRIPTION
6/55
Issue 1.1
Figure 1.1. Functionnal description.
x86
Core
Host I/F
Serial 2
// Port
Serial 1
DRAM
I/F
VGA
GE
PCI m/s
Local
Bus I/F
PCMCIA
CARDBUS
PCI BUS
ISA
m/s
IPC
82C206
PCI m/s
ISA BUS
CRTC
HW Cursor
Monitor
TFT Output
SYNC Output
TFT I/F
TFT
extension
Kbd
Mouse
GENERAL DESCRIPTION
7/55
Issue 1.1
Figure 1.2. PCI, PCMCIA & CARDBUS modes:
PCI m/s
PCMCIA
CARDBUS
PCI BUS
PCI m/s
PCMCIA
CARDBUS
PCI BUS
PCI m/s
PCMCIA
CARDBUS
PCI BUS
GENERAL DESCRIPTION
8/55
Issue 1.1
Figure 1.3. Local Bus and ISA bus modes:
Figure 1.4. TFT in normal (serial 1 available) and extended modes (serial 1 unavailable).
Serial 2
// Port
Local
Bus I/F
ISA
m/s
IPC
82C206
ISA BUS
Serial 2
// Port
Local
Bus I/F
ISA
m/s
IPC
82C206
ISA BUS
Serial 1 TFT
extension
TFT
extension
TFT Output
TFT I/F
Kbd
Mouse
Serial 1Kbd
Mouse
TFT Output
TFT I/F
9-bit mode
12-bit mode
18-bit mode
2 x 9-bit mode
GENERAL DESCRIPTION
9/55
Issue 1.1
Figure 2. Typical PC oriented Application
ISA
PCI
4x 16-bit EDO DRAMs
Super I/O
Flash
IDE
Serial Ports
Parallel Port
Floppy
Monitor
TFT
SVGA
IRQ
DMA.REQ
DMA.ACK
DMUX
MUX
MUX
STPC Industrial
RTC
Mouse
Keyboard
GENERAL DESCRIPTION
10/55
Issue 1.1
Figure 3. Typical Embedded Application
STPC Industrial
PC-Card
4x 16-bit EDO DRAMs
Flash
Peripheral
IRQ
MUX
PCMCIA
CARDBUS
Monitor
TFT
SVGA
Mouse
Keyboard
Serial Ports
Parallel Port
STPC Local Bus
I/O
SRAM
STRAP OPTION
11/55
Issue 1.1
2 STRAP OPTION
This chapter defines the STPC Industrial Strap Options and their location
Memory
Data
Lines
Refer to Designation Location
Actual
Settings
Set to ’0’ Set to ’1’
MD0 - Reserved - - - MD1 - Reserved - - - MD2 DRAM Bank 1 Speed Index 4A,bit 2 User defined 70 ns 60 ns
MD3 Speed Index 4A,bit 3 Pull up
MD4 Type Index 4A,bit 4 User defined EDO FPM
MD5 DRAM Bank 0 Speed Index 4A,bit 5 User defined 70 ns 60 ns
MD6 Speed Index 4A,bit 6 Pull up
MD7 Type Index 4A,bit 7 User defined EDO FPM
MD8 - Reserved - - - -
MD9 - Reserved - - - MD10 DRAM Bank 3 Speed Index 4B,bit 2 User defined 70 ns 60 ns
MD11 Speed Index 4B,bit 3 Pull up
MD12 Type Index 4B,bit 4 User defined EDO FPM
MD13 DRAM Bank 2 Speed Index 4B,bit 5 User defined 70 ns 60 ns
MD14 Speed Index 4B,bit 6 Pull up
MD15 Type Index 4B,bit 7 User defined EDO FPM
MD16 Reserved Index 4C,bit 0
MD17 PCI Clock PCI_CLKO Divisor Index 4C,bit 1 User defined HCLK / 3 HCLK / 2
MD18 Host Clock HCLK Pad Direction Index 4C,bit 2 User defined External Internal
MD19 Graphics Clock GCLK2x Pad Direction Index 4C,bit 3 User defined External Internal
MD20 DOT Clock DCLK Pad Direction Index 4C,bit 4 User defined External Internal
MD21 Reserved Pull up
MD22 External IPC Debug Option Index 5F,bit 1 Pull up External IPC Internal IPC
MD23 - Reserved Index 5F,bit 2 Pull up - MD24 HCLK HCLK PLL Speed Index 5F,bit 3 User defined 000 25 MHz
MD25 Index 5F,bit 4 User defined 001 33 MHz
MD26 Index 5F,bit 5 User defined 010 40 MHz
011 50 MHz
100 60 MHz
101 66 MHz
110 75 MHz
111 80 MHz
MD27 Reserved Pull down
MD28 Reserved Pull down
MD29 Reserved Pull down
MD30 Reserved Pull down
MD31 Reserved Pull down
MD32 Reserved Pull down
MD33 Reserved Pull up
MD34 Reserved Pull down
MD35 Reserved Pull up
MD 36 Reserved Pull up
MD 37 Reserved Pull up
MD 38 Reserved Pull up
STRAP OPTION
12/55
Issue 1.1
2.1 STRAP OPTION REGISTER DESCRIPTION
2.1.1 STRAP REGISTER 0 INDEX 4AH (STRAP0)
Bits 7-0, This register reflect the status of pins MD[7:0] respectively. They are expected to be connected
on the system board to the SIMM configuration pins as follows:
Note that the SIMM speed and type information read here is meant only for the software and is not used
by thehardware. The software must program the Host and graphics DRAM controller configuration registers appropriately based on these bits.
This register defaults to the values sampled on MD[7:0] pins after reset.
MD 39 Reserved Pull up
MD 40 PCMCIA or PCI i/f 3C,bit 0 User defined PCI PCMCIA
MD 41 Local Bus or ISA i/f 3C,bit 1 User defined ISA Local Bus
MD 42 Key Board & Mouse 3C,bit 2 User defined External Internal
MD 43 Parallel Port 3C,bit 3 User defined External Internal
MD 44 Serial Port UART1 3C,bit 4 User defined External Internal
MD 45 UART2 3C,bit 5 User defined External Internal
MD 46 Reserved 3C,bit 6 Pull down
MD 47 Reserved 3C,bit 7 Pull down
MD 48 TFT Outputs on RFU pads 3D,bit 0 User defined Disable Enable
MD 49 Cardbus Socket 5V Availability 3D,bit 1 User defined
Not Availa-
ble
Available
MD 50 3.3V Availability 3D,bit 2 User defined
Not Availa-
ble
Available
MD 51 x.xV Available 3D,bit 3 User defined
Not Availa-
ble
Available
MD 52 y.yV Available 3D,bit 4 User defined
Not Availa-
ble
Available
MD 53 Reserved Pull uo
MD 56 Reserved Pull up
MD 57 Reserved Pull down
MD 58 Reserved Pull up
MD 59 Reserved Pull down
Bit Sampled Description
Bit 7 SIMM 0 DRAM type
Bits 6-5 SIMM 0 speed
Bit 4 SIMM 1 DRAM type
Bits 3-2 SIMM 1 speed
Bits 1-0 Reserved
Memory
Data
Lines
Refer to Designation Location
Actual
Settings
Set to ’0’ Set to ’1’
STRAP OPTION
13/55
Issue 1.1
2.1.2 STRAP REGISTER 1 INDEX 4BH (STRAP1)
Bits 7-0, This register reflect the status of pins MD[15:8] respectively. They are expected tobe connected
on the system board to the SIMM configuration pins as follows:
Note that the SIMM speed and type information read here is meant only for the software and is not used
by the hardware. The software must program the Host and graphics dram controller configuration registers appropriately based on these bits.
This register defaults to the values sampled on MD[15:8] pins after reset.
2.1.3 STRAP REGISTER 2 INDEX 4CH (STRAP2)
Bits 4-0of this register reflect the status of pins MD[20:16] respectively. Bit 5 ofthis register reflect the status of pin MD[23]. Bit 4 is writeable, writes to other bits in this register have no effect.
They are use by the chip as follows:
Bits 7-5, Reserved
Bit 4, This bit reflects the value sampled on MD[20] pin and controls the Dot clock (DCLK) source. Note
this bit is writeable as well as readable.
Bit 3, This bit reflects the value sampled on MD[19] pin and controls the Graphics clock source.
Bit 2, This bit reflects the value sampled on MD[18] pin and controls the Host/CPU clock source as follows: setting to’0’: External. HCLK pin is an input, setting to ’1’: Internal. HCLK pin is an output and is connected to the internal frequency synthesizer output.
Bit 1, This bit reflects the value sampled on MD[17] pin and controls the PCI clock output as follows:
Setting to ’0’, the PCI clock output = HCLK / 3
Setting to ’1’, the PCI clock output = HCLK / 2
Bit 0, Reserved.
This register defaults to the values sampled on MD[23] & MD[20:16] pins after reset.
Bit Sampled Description
Bit 7 SIMM 2 DRAM type
Bits 6-5 SIMM 2 speed
Bit 4 SIMM 3 DRAM type:
Bits 3-2 SIMM 3 speed
Bit 1-0 Reserved
STRAP OPTION
14/55
Issue 1.1
2.1.4 STRAP REGISTER 3 INDEX 3CH (STRAP3)
Bits 7-0 of this register reflect the status of pins MD[47:40] respectively.
They are use by the chip as follows:
Bit 7-6, Reserved.
Bit 5, UART2 internal or external. This bit reflects the value sampled on MD[45] pin and controls the
UART2 I/F as follows:
Setting to ’0’, UART2 is external.
Setting to ’1’, UART2 is internal.
Bit 4, UART1 internal or external and additional TFT outputs. This bit reflects the value sampled on
MD[44] pin and controls the UART1 I/F and the additional TFT I/F as follows:
Setting to ’0’, UART1 is external and anadditional 6 TFT outputs (lowest bits - 2 red, 2 green
and 2 blue) are enabled.
Setting to ’1’, UART1 is internal.
Note that when strap option testbus enabled (see Section 2.1.3 Strap Register 2 bit 0) is driven to 1 it
takes priority over this strap which becomes meaningless.
Bit 3, Parallel Port internal or external. This bitreflects the value sampled on MD[43] pin and controls the
Parallel Port i/f as follows:
Setting to ’0’, the Parallel Port is external
Setting to ’1’, the Parallel Port is internal
Bit 2, KB/Mouse internal or external. This bit reflects the value sampled on MD[42] pin and controls the
KB/Mouse controller i/f as follows:
Setting to ’0’, the KB/Mouse controller is external
Setting to ’1’, the KB/Mouse controller is internal
Bit 1, Local Bus i/for ISA I/F. This bit reflects thevalue sampled on MD[41] pin and sets whether the Local Bus i/f or the ISA i/f is available at the device i/f as follows:
Setting to ’0’, selectes the ISA I/F
Setting to ’1’, selectec the Local Bus I/F
Bit 0 PCMCIA I/F or PCI I/F. This bit reflects the value sampled on MD[40] pin and sets whether the
PCMCIA i/f or the PCI i/f is available at the device i/f as follows:
Setting to ’0’, selects the PCI I/F
Setting to ’1’, selects the PCMCIA I/F
This register defaults to the values sampled on MD[47:40] pins after reset.
STRAP OPTION
15/55
Issue 1.1
2.1.5 STRAP REGISTER 4 INDEX 3Dh (STRAP4)
Bits 5-0 of this register reflect the status of pins MD[53:48] respectively.
They are use by the chip as follows:
Bits 7-5 Reserved.
Bit 4, y.y V present on board. This bit reflects the value sampled on MD[52] pin and is used to notify the
Cardbus socket management unit if the y.y V vcc voltage (where y.y is less than x.x) is present on board
as follows
Setting to ’0’, y.y V Vcc voltage is not available
Setting to ’1’: y.y V Vcc voltage is available.
Bit 3, x.x V present on board. This bit reflects the value sampled on MD[51] pin and is used to notify the
Cardbus socket management unit if the x.x V vcc voltage (where x.x is less than 3.3) is present on board
as follows:
Setting to ’0’, x.x V Vcc voltage is not available.
Setting to ’1’: x.x V Vcc voltage is available.
Bit 2, 3.3 V present on board. This bit reflects the value sampled on MD[50] pin and is usedto notify the
Cardbus socket management unit if the 3.3 V vcc voltage is present on board as follows:
Setting to ’0’, 3.3 V vcc voltage is not available.
Setting to ’1’, 3.3 V vcc voltage is available.
Bit 1, 5 V present on board. This bit reflects the value sampled on MD[49] pin and is used to notify the
Cardbus socket management unit if the 5 V vcc voltage is present on board as follows:
Setting to ’0’, 5 V vcc voltage is not available.
Setting to ’1’, 5 V vcc voltage is available.
Bit 0, This bit reflects the value sampled on MD[48] pin and is used to enable the TFT controller outputs
on pads RFU0-RFU11 as follows:
RFU0 : R[2]
RFU1 : R[3]
RFU2 : R[4]
RFU3 : R[5]
RFU4 : G[2]
RFU5 : G[3]
RFU6 : G[4]
RFU7 : G[5]
RFU8 : B[2]
RFU9 : B[3]
RFU10 : B[4]
RFU11 : B[5]
This register defaults to the values sampled on MD[53:48] pins after reset.
STRAP OPTION
16/55
Issue 1.1
2.1.6 HCLK PLL STRAP REGISTER 0 INDEX 5FH (HCLK_STRAP0)
Bits 5-0 of this register reflect the status of pins MD[26:21] respectively.
They are use by the chip as follows:
Bits 7-6, Reserved.
Bits 5-3,These pins reflect the value sampled on MD[26:24] pinsrespectively and control the Host clock
frequency synthesizer.
Bit 2-1, Reserved.
Bit 0, Reserved.
This register defaults to the values sampled on above pins after reset.
PIN DESCRIPTION
17/55
Issue 1.1
3 PIN DESCRIPTION
3.1. INTRODUCTION
The STPC Industrial integrates most of the functionalities of the PC architecture. Therefore, many
of the traditional interconnections between the
host PC microprocessor and the peripheral devices are totally internal to the STPC Industrial. This
offers improved performance due to the tight coupling of theprocessor coreand it’s peripherals. As
a result many of the external pin connections are
made directly to the on-chip peripheral functions.
Figure 3-1 shows the STPC Industrial’s external
interfaces. It defines the main busses and their
function. Table 3-1 describes the physical implementation listing signal types and their functionalities. Table 3-2 provides a full pin listing and description.
Table 3-4 provides a full listing of theSTPC Industrial package pin location physical connection.
Please refer tothe pin allocation drawing for reference.
Due to the number of pins available for the package, and the number offunctional I/Os, some pins
have several functions, selectable by strap option
on Reset. Table 3-3 provides a summary of these
pins and their functions.
Table 3-1. Signal Description
Group name Qty
Basic Clocks, Reset & Xtal (SYS) 13
DRAM Controller(DRAM) 89
PCI Controller 55
64
PC Card Interface 64
Keyboard/Mouse Controller (SIO) 4
Local Bus I/F, Parallel I/F,Serial 2 75
75
ISA Interface/IPC extensions 73
Serial 1 (SIO) 8
26
TFT output 24
VGA Controller (VGA) 10
Grounds 74
V
DD
16
Analog specific V
CC/VDD
16
Reserved 1
TotalPin Count 388
Figure 3-1. STPC Industrial External Interfaces
PCI
x86 core
DRAM VGA TFT SYS SIO
89 10 24 12 55
13
75 38
STPC Industrial
CARD
PC
ISA/
LOCAL BUS
NORTH BRIDGE SOUTH BRIDGE
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