SGS Thomson Microelectronics STPCE1 Datasheet
STPC® ELITE
X86 Core General Pur pose PC Compat i ble System - on - Chip
Release 1.3 - January 29, 2002 1/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Logic Diagram
■
POWERFUL X86 PROCESSOR
■
64-BIT SDRAM CONTROLLER AT 100MHz
■
INTEGRATED PCI NORTH / SOUTH
BRIDGE CONTROLLER
■
ISA MASTER / SLAVE / DMA
■
16-BIT LOCAL BUS INTERFACE FOR LOW
COST AND EMBEDDED APPLICATIONS
■
EIDE CONTROLLER
■
INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
■
POWER MANAGEMENT UNIT
■
I²C INTERFACE
■
16 ENHANCED GENERAL PURPOSE I/Os.
■
JTAG IEEE1149.1
■
PROGRAMMABLE OUTPUT CLOCK UP TO
135MHz
■
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DESCRIPTION
The STPC Elite integrates a fully static x86
processor up to 133 MHz, fully compatible with
standard x86 processors, and combines it with
powerful chipset to provide a general purpose P C
compatible subsystem on a single device. The
device is packaged in a 388 Ball Grid Array
(PBGA).
The STPC Elite has a low voltage operation with
V
CORE
= 2.5V and has 5V tolerant I/Os (3.3V
output levels).
PBGA388
S
T
P
C
E
L
I
T
E
x86
Core
Host I/F
SDRAM
CONTROL
PCI
I/F
PCI
ISA
I/F
EIDE
ctrl
PCI
I/F
ISA BUS
EIDE
L.B.
I/F
LOCAL BUS
IPC
JTAGPMU
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■
X86 Processor core
■
Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatib l e .
■
Can access up to 4GB of external memory .
■
8KByte unified instruction and data cache
with write back and write through capability.
■
Parallel processing integral floating point unit,
with automatic power down.
■
Clock core speeds up to of 100 MHz in x1
clock mode and 133MHz in x2 mode.
■
Fully static design for dynamic clock control.
■
Low power and system management modes.
■
SDRAM Controller
■
64-bit data bus.
■
Up to 100MHz SDRAM clock speed.
■
Supports up to 128 MB system memory .
■
Support s 16-, 64- and 128-Mbit memorie s.
■
Supports up to 4 memory banks.
■
Supports buffered, non buffered, registered
DIMMs
■
4-line write buffers f or CPU to DRAM and PCI
to DRAM cycles.
■
4-line read prefetch buffers for PCI masters.
■
Programmable latency
■
Programmable timing for DRAM parameters.
■
Support s -8, -10, -12, -13, -15 memory par t s
■
Supports memory hole between 1MB and
8MB for PCI/ISA busses.
■
PCI Controller
■
Compliant with PCI 2.1 specification.
■
Integrated PCI arbitration interface. Up to 3
masters can connect directly. External logic
allows for greater than 3 masters.
■
Translation of PCI cycles to ISA bus.
■
Tr a n slation of ISA master ini ti a te d cycle to
PCI.
■
Support for burst read/write from PCI master.
■
0.25X, 0.33X and 0.5X Host clock PCI clock.
■
ISA master/slave
■
Generates the ISA clock from either
14.318 MH z o s c illator clock or PCI c lo ck
■
Support s programmable extra wait state for
ISA cycles
■
Supports I/O recovery time for back to back
I/O cycles.
■
Fast Gate A20 and Fast reset.
■
Support s the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
■
Support s flash ROM.
■
Support s ISA hidden re fresh.
■
Buffered DMA & ISA master cycl es t o reduce
bandwidth utilization of the PCI and Host
bus. NSP compliant.
■
16-bit I/O decoding.
■
Local Bus interface
■
Multiplexed with ISA/DMA/Timer functions.
■
High speed, low latency bus.
■
Support s 32-bit Flash burst.
■
16-bit data bus with word steering capability.
■
Separate memory and I/O addres s spac es.
■
Programmable timing (Host clock granularity)
■
Supports 2 cachable banks of 16MB flash
devices with boot block shadowed to
0x000F0000.
■
2 Programmable Flash/EPROM Chip Select.
■
4 Programmable I/O Chip Select.
■
2-level hardware ke y protection for Flash boot
block protection.
■
24 bit address bus.
■
EIDE Controller
■
Compatible with EIDE (ATA-2).
■
Backward compatibilit y wit h ID E (ATA-1).
■
Supports up to 4 IDE devices
■
Support s PIO and Bu s Master IDE
■
Concurrent channel operation (PIO & DMA
modes) - 4 x 32-Bit Buffer FIFO per channel
■
Support for 11.1/16.6 MB/s, I/O Channel
Ready PIO data transfers.
■
Bus Master with scatter/gather capability.
■
Multi-word DMA suppor t for fast IDE drives.
■
Individual drive timing for all four IDE devices.
■
Support s both legacy & native IDE modes.
■
Supports hard drives larger than 528MB.
■
Support for CD-ROM and tape peripherals.
■
Integrated Peripheral Controller
■
2X8237/AT compatible 7-channel DMA
controller.
■
2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
■
Three 8254 compatible Timer/Counters.
■
Co-processor error support logic.
■
Support s external RTC.
■
Power Management
■
Four power saving modes: On, Doze,
Standby, Suspend.
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■
Programmable system activity detector
■
Supports SMM.
■
Supports STOPCLK.
■
Support s IO trap & restart .
■
Independent peripheral time-out timer to
monitor hard disk, serial & parallel ports.
■
Supports RTC, interrupts and DMAs wake-up
■
GPIOs
■
16 Enhanced General Purpose IO.
■
JTAG Function
■
Programmable GP-Clock
■
This clock is programmable to frequencies up
to 135 MHz.
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GENERAL DESCRIPTION
Release 1.3 - January 29, 2002 5/87
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1. GENERAL DESCRIPTION
At the heart of the STPC Elite is an advanced
processor block that includes a powerful x86
processor core along with a 64-bit SDRAM
controller, a high speed PCI local-bus controller
and Industry standard PC chip set functions
(Interrupt controller, DMA Controller, Interval timer
and ISA bus) and EIDE controller.
The processor bus runs at the speed of the
processor (x1 mode) or half the speed (x2 mode).
The STMicroelectronics x86 processor core is
embedded with standard and app lication specific
peripheral modules on the sa me silicon die. The
core has all the functionality of the ST standard
x86 processor products, including the low power
System Management Mode (SMM).
System Management Mode (SMM) provides an
additional interrupt and address space that can be
used for system power management or software
transparent emulation of peripherals. While
running in isolated SMM address space, the SMM
interrupt routine can execute without interfering
with the operating system or application
programs.
The ‘standard’ PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated with the x86 processor core.
The PCI bus is the ma in data comm unication link
to the STPC Elite chip. The STPC Elite translates
appropriate host bus I/O an d M em ory cycles onto
the PCI bus. It also supports generation of
Configuration cycles on the PCI bus. The STPC
Elite, as a PCI bus agent (host bridge class), f ully
complies with PCI specificat ion 2.1. The chip-set
also implements the PCI mandatory header
registers in Type 0 PCI configuration space for
easy porting of PCI aware system BIOS. The
device contains a PCI arbitration function for three
external PC I dev i ces.
The STPC Elite integrates an ISA bus controller.
Peripheral modules such as parallel and serial
communications ports, keyboard controllers and
additional ISA devices can be accessed by the
STPC Elite chip set through this bus.
An industry standard EIDE (ATA 2) controller is
built in to the STPC Elite and connected internally
via the PCI bus.
1.1. MEMORY CONTROLLER
The STPC handles the mem ory data (DATA) bus
directly, controlling from 8 to 128 MBytes. The
SDRAM controller supports accesses to the
Memory Banks to/from the CPU (via the host).
Parity is not supported.
The SDRAM controller only supports 64 bit wide
Memory Banks.
Four Memory Banks (if DIMMS are used; Single
sided or two double-sided DIMMs) are s upported
in the following configurations (see Table 1-1)
The SDRAM Controller supports buffered or
unbuffered SDRAM but not EDO o r FPM modes.
SDRAMs must support Full Page Mode Type
access.
The STPC Memory Controller provides various
programmable SDRAM parameters to allow the
SDRAM interface to be optimized for different
processor bus speeds SDRAM speed grades and
CAS Latency.
1.2. POWER MANAGEMENT
The STPC Elite core is compliant with the
Advanced Power Management (APM)
specification to provide a standard method by
which the BIOS can control the power used by
personal computers. The Power Management
Unit (PMU) module controls the power
consumption, providing a comprehensive set of
features that controls the power usage and
supports compliance with the United States
Environmental Protection Agency's Energy Star
Computer Program. The PMU provides the
following hardware structures to assist the
software in managing the system power
consumption:
- System Activity Detection.
Table 1-1. Memory configurations
Memory
Bank size
Number
Organisa
tion
Device
Size
1Mx64 4 1Mx16
16Mbits2Mx64 8 2Mx8
4Mx64 16 4Mx4
4Mx64 4 2Mx16x2
64Mbits
8Mx64 8 4Mx8x2
16Mx64 16 8Mx4x2
4Mx64 4 1Mx16x4
8Mx64 8 2Mx8x4
32Mx64 16 4Mx4x4
16Mx64 8 2Mx16x2
128Mbits
32Mx64 16 4Mx8x4
GENERAL DESCRIPTION
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- 3 power-down timers detecting system inactivity:
- Doze timer (short durations).
- Stand-by timer (medium durations).
- Suspend timer (long durations).
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
state.
- Peripheral activity detection.
- Peripheral timer detecting peripheral inactivity
- SUSP# modulation to adjust the system
performance in various power down state s of the
system including full power-on state.
- Power control outputs to disable power from
different planes of the board.
Lack of system activity for progressively longer
periods of time is detected by the three power
down timers. These timers can generate SMI
interrupts to CPU so that the SMM software can
put the system in decreasing states of power
consumption. Alternatively, system activity in a
power down state can g enerate an SMI interrupt
to allow the software to bring the system back up
to full power-on state. The chip-set supports up to
three power down states described above; these
correspond to decreasing levels of power savings.
Power down puts the STPC Elite into suspend
mode. The processor completes execution of the
current instruction, any pending decoded
instructions and associated bus cycles. During the
suspend mode, internal clocks are stopped.
Removing power-down, the processor resumes
instruction fetching and begins execution in the
instruction stream at the point it had stopped.
Because of the static nature of the core, no
internal data is lost.
1.3. JTAG
JT A G stands for Joint Test Action Group and is the
popular name for IEEE Std. 1149.1, Standard T est
Access Port and Boundary-Scan Architec-ture.
This built-in circuitry is used to assist in the test,
maintenance and support of functional circuit
blocks. The circuitry includes a standard interface
through which instructions and test data are
communicated. A set of test features is defined,
including a boundary-scan registe r so that a
component is able to respond to a minimum set of
test instructions.
GENERAL DESCRIPTION
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Figure 1-1. Functional description.
PCI North
Bridge
Host I/F
X86
Core
SDRAM
Controller
ISA
m/s
EIDE
PCI South
Bridge
ISA BUS
IPC
82C206
EIDE
GPIO
x16
Local
Bus I/F
JTAG
LOCAL BUS
GPCLK
GENERAL DESCRIPTION
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1.4. CLOCK TREE
The STPC Elite integrates many features and
generates all its clocks from a single 14MHz
oscillator. This results in multiple clock domains as
described in Figure 1-2.
The speed of the PLLs is either fixed (DE VCLK),
either programmable by strap option (HCLK)
either programmable by software (GPCLK,
MCLK). When in synchronized mode, MCLK
speed is fixed to HCLKO speed and HCLKI is
generated from MCLKI.
Figure 1-2. STPC Elite clock architecture
IPC
SDRAM controller
North Bridge
14.31818 MHz
XTALO XTALI
OSC14M ISACLK
1/4
GPCLK
GPCLK
PLL
(14MHz)
1/2
HCLK
PLL
PCICLKI PCICLKO
South Bridge
1/2
1/3
HCLK
MCLK
PLL
MCLKIMCLKO
CPU
x1
x2
Local Bus
Host
ISA
HCLKI
HCLKO
GENERAL DESCRIPTION
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Figure 1-3. Typical ISA-based Application.
STPC Elite
ISA
PCI
4x 16-bit SDRAMs
Super I/O
2x EIDE
Flash
Keyboard / Mouse
Serial Ports
Parallel Port
Floppy
IRQ
DMA.REQ
DMA.ACK
DMUX
DMUX
MUX
MUX
RTC
GPIOs
GPCLK
GENERAL DESCRIPTION
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PIN DESCRIPTION
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2. PIN DESCRIPTION
2.1. INTRODUCTION
The STPC Elite integrates most of the
functiona lities of the PC archite cture. A s a resu lt,
many of the traditional interconnections between
the host PC microprocessor and the peripheral
devices are totally internal to the STPC Elite. This
offers improved performance due to the tight
coupling of the processor core and these
peripherals. As a result many of the external pin
connections are made directly to the on-chip
peripheral functions.
Figure 2-1 shows the STPC Elite external
interfaces. It defines the main buses and their
function. Table 2-1 describes the physical
implementation listing signals type and their
functionality. Table 2-2 provides a full pin listing
and description of pins. Table 2-7 provides a full
listing of pin locations of the STPC Elite package
by physical connection.
Note:
Several interface pins are multiplexed with
other functions, refer to Table 2-4 and Table 2-5
for further details
Table 2-1. Signal Description
Group name Qty
Basic Clocks reset & Xtal 6
Memory Interface 96
PCI interface 56
ISA 79
90IDE 34
Local Bus 50
Grounds 69
V
DD
22
Miscellaneous 8
GPIO 16
Unconnected 25
Total Pin Count 388
Figure 2-1. STPC Elite External Interfaces
SOUTHNORTH PCI
x86
SDRAM I/F
SYS
ISA/IDE/LB
96 56
6
90
STPC Elite
PIN DESCRIPTION
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Table 2-2 . Def i ni t io n of Si gn a l Pin s
Signal Name Dir Buffer Type
2
Description Qty
BASIC CLOCKS AND RESETS
SYSRSETI# I SCHMITT_FT System Power Good Input 1
SYSRSTO# O BD8STRP_FT System Reset Output 1
XTALI I ANA
14.3 MHz Crystal Input - External
Oscillator Input
1
XTALO I/O OSCI13B 14.3 MHz Crystal Output 1
HCLK I/O BD4STRP_FT Host Clock (Test) 1
GP_CLK O BT8TRP_TC General Purpose Clock 1
V
DD
_xxx_PLL
1
Power Supply for PLL Clocks
MEMORY INTERFACE
MCLKI I TLCHT_TC Memory Clock Input 1
MCLKO O BT8TRP_TC Memory Clock Output 1
CS#[1:0] O BD8STRP_TC DIMM Chip Select 2
CS#[3]/MA[13]/BA[1] O BD16STARUQP_TC
DIMM Chip Select/ Memory Address/
Bank Address
1
CS#[2]/MA[12] O BD16STARUQP_TC DIMM Chip Select/ Bank Address 1
MA[10:0] O BD16STARUQP_TC Memory Row & Column Address 12
MD[48:10], [7:2] I/O BD8TRP_TC Memory Data 45
MD[63:49], [9:8], [1:0] I/O BD8STRUP_FT Memory Data 19
RAS#[1:0] O BD16STARUQP_TC Row Address Strobe 2
CAS#[1:0] O BD16STARUQP_TC Column Address Strobe 2
MWE# O BD16STARUQP_TC Write Enable 1
DQM[7:0] O BD8STRP_TC Data Input/Output Mask 8
PCI INTERFACE
PCI_CLKI I TLCHT_FT 33 MHz PCI Input Clock 1
PCI_CLKO O BT8TRP_TC
33 MHz PCI Output Clock (from internal
PLL)
1
AD[31:0] I/O BD8PCIARP_FT PCI Address / Data 32
CBE[3:0] I/O BD8PCIARP_FT Bus Commands / Byte Enables 4
FRAME# I/O BD8PCIARP_FT Cycle Frame 1
IRDY# I/O BD8PCIARP_FT Initiator Ready 1
TRDY# I/O BD8PCIARP_FT Target Ready 1
LOCK# I TLCHT_FT PCI Lock 1
DEVSEL# I/O BD8PCIARP_FT Device Select 1
STOP# I/O BD8PCIARP_FT Stop Transaction 1
PAR I/O BD8PCIARP_FT Parity Signal Transactions 1
SERR# O BD8PCIARP_FT System Error 1
PCI_REQ#[2:0] I BD8PCIARP_FT PCI Request 3
PCI_GNT#[2:0] O BD8PCIARP_FT PCI Grant 3
PCI_INT[3:0] I BD4STRUP_FT PCI Interrupt Request 4
ISA CONTROL
Note
1
: These pins must be connected to the 2.5 V power supply. They
must not
be connected to the 3.3V supply.
Note
2
: See Table 2-3 for buffer type descriptions.
PIN DESCRIPTION
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ISA_CLK O BT8TRP_TC
ISA Clock Output - Multiplexer Select
Line For IPC
1
ISA_CLK2X O BT8TRP_TC
ISA Clock x2 Output - Multiplexer Select
Line For IPC
1
OSC14M O BD8STRP_FT Buffered 14MHz clock 1
LA[23:17] O BD8STRUP_FT Unlatched Address 7
SA[19:0] I/O BD8STRUP_FT Latched Address 20
SD[15:0] I/O BD8STRP_FT Data Bus 16
ALE O BD4STRP_FT Address Latch Enable 1
MEMR#, MEMW# I/O BD8STRUP_FT Memory Read and Memory Write 2
SMEMR#, SMEMW# O BD8STRUP_FT
System Memory Read and Memory
Write
2
IOR#, IOW# I/O BD8STRUP_FT I/O Read and Write 2
MCS16#, IOCS16# I BD4STRUP_FT Memory/IO Chip Select16 2
BHE# O BD8STRUP_FT System Bus High Enable 1
ZWS# I BD4STRP_FT Zero Wait State 1
REF# O BD8STRP_FT Refresh Cycle. 1
MASTER# I BD4STRUP_FT Add On Card Owns Bus 1
AEN O BD8STRUP_FT Address Enab le 1
IOCHCK# I BD4STRUP_FT I/O Channel Check. 1
IOCHRDY I/O BD8STRUP_ FT
I/O Channel Ready (ISA) - Busy/Ready
(IDE)
1
ISAOE# O B D4ST RP_F T ISA /IDE Selec tion 1
GPIOCS# I/O BD4STRP_FT General Purpose Chip Select 1
IRQ_MUX[3:0] I BD4STRP_FT Time-Multiplexed Interrupt Request 4
DREQ_MUX[1:0] I BD4STRP_FT Time-Multiplexed DMA Request 2
DACK_ENC[2:0] O BD4STRP_FT Encoded DMA Acknowledge 3
TC O BD4STRP_FT ISA Terminal Count 1
RTCAS O BD4STRP_FT Real Time Clock Address Strobe 1
RMRTCCS# I/O BD4STRP_FT ROM/RTC Chip Select 1
KBCS# I/O BD4STRP_FT Keyboard Chip Select 1
RTCRW# I/O BD4STRP_FT RTC Read/Write 1
RTCDS# I/O BD4STRP_FT RTC Data Strobe 1
LOCAL BUS
PA[23:20], [15], [8], [3:0] O BD4STRP_FT Address Bus 10
PA[19:16], [14:12],[7:4] O BD8STRUP_FT Address Bus 11
PA[11] O BD8STRP_F T Address Bus 1
PA[10:9] O BD4STRUP_FT Address Bus 2
PD[15:0] I/O BD8STRP_FT Data Bus 16
PRD1#,PRD0# O BD4STRUP_FT Peripheral Read Control 2
PWR1# O BD8STRUP_FT Peripheral Write Control 1
PWR0# O BD4STRUP_FT Peripheral Write Control 1
PRDY I BD8STRUP_FT Data Ready 1
FCS1#, FCS0# O BD4STRP_FT Flash Chip Select 2
IOCS#[3] O BD4STRP_FT I/O Chip Select 1
IOCS#[2:0] O BD8STRUP_FT I/O Chip Select 3
Table 2-2 . Def i ni t io n of Si gn a l Pin s
Signal Name Dir Buffer Type
2
Description Qty
Note
1
: These pins must be connected to the 2.5 V power supply. They
must not
be connected to the 3.3V supply.
Note
2
: See Table 2-3 for buffer type descriptions.
PIN DESCRIPTION
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IDE CONTROL
DA[2:0] O BD8STRUP_ FT Add ress Bus 3
DD[15:12] I/O BD4STRP_FT Data Bus 4
DD[11:0] I/O BD8STRUP_FT Data Bus 12
PCS3#,PCS1#,SCS3#,SCS1# O BD8STRUP_FT Primary & Secondary Chip Selects 4
DIORDY O BD8STRUP_FT Data I/O Ready 1
PIRQ, SIRQ I BD4STRP_FT Primary & Secondary Interrupt Request 2
PDRQ, SDRQ I BD4STRP_FT Primary & Secondary DMA Request 2
PDACK#, SDACK# O BD8STRP_FT
Primary & Secondary DMA
Acknowledge
2
PDIOR#, SDIOR# O BD8STRUP_FT Primary & Secondary I/O Channel Read 2
PDIOW#, SDIOW# O BD8STRP_FT Primary & Secondary I/O Channel Write 2
MISCELLANEOUS
GPIO[15:0] I/O BD4ST RP_F T General Purpose I/Os 16
SPKRD O BD4STRP_FT Speaker Device Output 1
SCL I/O BD4STRUP_FT
I²C Interface - Clock / Can be used for
VGA DDC[1] signal
1
SDA I/O BD4STRUP_FT
I²C Interface - Data / Can be used for
VGA DDC[0] signal
1
SCAN_ENABLE I TLCHTD_TC Reserved (Test pin) 1
TCLK I BD4STRP_FT Test clock 1
TDI I BD4STRP_FT Test data input 1
TMS I BD4STRP_FT Test mode input 1
TDO O BD4STRP_FT Test data output 1
Table 2-2 . Def i ni t io n of Si gn a l Pin s
Signal Name Dir Buffer Type
2
Description Qty
Note
1
: These pins must be connected to the 2.5 V power supply. They
must not
be connected to the 3.3V supply.
Note
2
: See Table 2-3 for buffer type descriptions.
PIN DESCRIPTION
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Table 2-3. Buffer Type Descriptions
Buffer Description
ANA Analog pad buffer
OSCI13B Oscillator, 13 MHz, HCMOS
BT8TRP_TC LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger
BD4STRP_FT LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, 5V tolerant
BD4STRUP_FT LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant
BD8STRP_FT LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, 5V tolerant
BD8STRUP_FT LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant
BD8STRP_TC LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger
BD8TRP_TC LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger
BD8PCIARP_FT LVTTL Bi-Directional, 8 mA drive capability, PCI compatible, 5V tolerant
BD16STARUQP_TC LVTTL Bi-Directional, 16 mA drive capability, Schmitt trigger
SCHMITT_FT LVTTL Input, Schmitt trigger, 5V tolerant
TLCHT_FT LVTTL Input, 5V tolerant
TLCHT_TC LVTTL Input
TLCHTD_TC LVTTL Input, Pull-Down
PIN DESCRIPTION
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2.2. SIGNAL DESCRIPTIONS
2.2.1. BASIC CLOCKS AND RESETS
SYSRSTI#
System Reset/Power good.
This input
is low when the reset switch is depressed.
Otherwise, it reflects the power supply’s power
good signal. This input is asynchronous to all
clocks, and acts as a negative active reset. The
reset circuit initiates a hard reset on the rising
edge of this signal.
SYSRSTO#
Rese t Outpu t to System .
This is the
system reset signal and is used to r eset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted
buffered version of this output and the PCI bus
reset is an externally buffered version of this
output.
XTALI
14.3 MHz Crystal Input
XTALO
14.3 MHz Crystal Output.
These pins are
provided for the connection of an external 14.318
MHz crystal to provide the reference clock for the
internal frequency synthesizer, from which all
other clock signals are generated.
The 14.318 MHz series-cut fundamental (not
overtone) mode quartz crystal must have an
Equivalent Series Resistance (ESR, sometimes
referred to as Rm) of less then 50 Ohms (typically
8 Ohms) and a shunt capacitance (Co) of less
than 7 pF. Balance capacitors of 16 pF should
also be added, one connected to each pin.
In the event of an ext ernal o scillat or pr ovidin g the
master clock signal to the STPC Elite device, the
TTL signal should be connected to XTALI.
HCLK
Host Clock.
This clock supplies the CPU
and the host related blocks. This clock can e
doubled inside the CPU and is intended to operate
in the range of 25 to 100 MHz. This clock in
generated internally from a PLL bu t can be driven
directly from the extern a l syst e m.
GP_CLK
General Purpose clock.
This clock is
programmable and its frequency can be as high
as 135 MHz.
2.2.2. MEMORY INTERFACE
MCLKI
Memory Clock Input.
This clock is driving
the SDRAM controller. This input should be a
buffered version of the MCLKO when more than 4
SDRAM chips are used. Go to section 6.3 for
more details.
MCLKO
Memory Clock Output.
This clock is
driving the SDRAM devices and is generated from
an internal PLL. The default value is 66 MHz.
CS#[2]/MA[11]
Chip Select/ Bank Address
This
pin is CS#[2] in the case when 16 Mbit devices are
used. For all other densities, it becomes MA[11].
CS#[3]/MA[12]/BA[1]
Chip Select/ Memory
Address/ Bank Address
This pin is CS#[3] in the
case when 16Mbit devices are used. For all other
densities, it becomes MA[12] when 2 internal
banks devices are used and BA[1] when 4 internal
bank devices are used.
MA[10:0]
Memory Address.
Multiplexed row and
column address lines.
BA[0]
Memory Bank Address.
CS#[1:0]
Chip Se lect.
These signals a re used to
disable or enable device operation by masking or
enabling all SDRAM inputs except MCLK, CKE,
and DQM.
MD[63:0]
Memory Dat a.
This is the 64-bit memory
data bus. MD[40-0] are read by the device strap
option registers during rising edge of SYSRSTI#.
RAS#[1:0]
Row Address Strobe.
There are two
active-low row address strobe output signals. The
RAS# signals drive the memory devices directly
without any external buffering.
CAS#[1:0]
Column Address Strobe.
There are
two active-low column address strobe output
signals. The CAS# signals drive the memory
devices directly without any external buffering.
MWE#
Write Enable.
Write enable specifies
whether the memory access is a read (MWE# = H)
or a write (MWE# = L).
DQM#[7:0]
Data Mask.
Makes data output Hi-Z
after the clock and masks the SDRAM outputs.
Blocks SDRAM data input when DQM active.
2.2.3. PCI INTERFACE
PCI_CLKI
33 MHz PCI Input Clock .
This signal is
the PCI bus clock input and should be driven from
the PCI_CLKO pin.
PCI_CLKO
33 MHz PCI Output Clock .
This is t h e
master PCI bus clock output.
AD[31:0]
PCI Address/Data.
This is the 32-bit
multiplexed address and data bus of the PCI. This
bus is driven by the master during the address
phase and data phase of write transactions. It is
driven by the target during data phase of read
transactions.
CBE#[3:0]
Bus Commands/Byte Ena bles.
These
are the multiplexed command and byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
PIN DESCRIPTION
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phase they carry the byte enable information.
These pins are inputs when a PCI master other
than the STPC Elite owns the bus and outputs
when the STPC Elite owns the bus.
FRAME#
Cycle Frame.
This is the frame signal of
the PCI bus. It is an input when a PCI master owns
the bus and is an output when STPC Elite owns
the PCI bus.
IRDY#
Initiator Ready.
This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Elite initiates a bus cycle on the PCI
bus. It is used as an input during the PCI cycles
targeted to the STP C Eli te to determine when the
current PCI master is ready to complete the
current transact i o n.
TRDY#
Target Ready.
This is the target ready
signal of the PCI bus. It is driven as an output
when the STPC Elite is the target of the current
bus transaction. It is used as an input when STPC
Elite initiates a cycle on the PCI bus.
LOCK#
PCI Lock.
This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
DEVSEL#
I/O Device Select.
This signal is used
as an input when the STPC E lite initiates a bus
cycle on the PCI bus to determine if a PCI slave
device has decoded itself to be the target of the
current transaction. It is asserted as an output
either when the STPC Elite is the target of the
current PCI transaction or when no other device
asserts DEVSEL# prior to the subtractive decode
phase of the current PCI transaction.
STOP#
Stop Transaction.
Stop is used to
implement the disconnect, retry and abort protocol
of the PCI bus. It is used as an input for the bus
cycles initiated by the S TPC Elite and is used as
an output when a PCI master cycle is t argeted to
the STPC Elite .
PAR
Parity Signal Transactions.
This is the pa rity
signal of the PCI bus. This signal is used to
guarantee even parity across AD[31:0],
CBE#[3:0], and PAR. Thi s signal is driven by the
master during the address phase and data phase
of write transactions. It is driven by the target
during data phase of read transactions. (Its
assertion is identical to that of the AD bus delayed
by one PCI clock cycle)
SERR#
System Error.
This is the system error
signal of the PCI bus. It may, if enabled, be
asserted for one PCI clock cycle if target aborts a
STPC Elite in itiated PCI t ransaction. I ts assertion
by either the STPC Elite or by another PCI bus
agent will trigger the assertion of NMI to the host
CPU. This is an open drain output.
PCI_REQ#[2:0]
PCI Request.
This pin are the
three external PCI master request pins. They
indicates to the PCI arbiter that the external
agents desire use of the bus.
PCI_GNT#[2:0]
PCI Grant.
These pins indicate
that the PCI bus has been g ranted to the master
requesting it on its PCIREQ#.
PCI_INT[3:0]
PCI Interrupt Request.
These are
the PCI bus interrupt signals.
2.2.4. ISA INTERFACE
ISA_CLK, ISA_CLKX2
ISA Clock x1, x2.
These
pins generate the Clock signal for the ISA bus and
a Doubled Clock signal. They are also used as the
multiplexer control lines for the Interrupt Controller
Interrupt input lines. ISA_CLK is generated from
either PCICLK/4 or OSC14M/ 2.
OSC14M
ISA bus synchronisation clock Output.
This is the buffered 14.318 MHz clock for the ISA
bus.
LA[23:17]
Unlatched Address.
When the ISA bus
is active, these pins are ISA Bus unlatched
address for 16-bit devices. When ISA bus is
accessed by any cycle initiated from PCI bus,
these pins are i n o utput mode. When an ISA bus
master owns the bus, these pins are in input
mode.
SA[19:0]
ISA Address Bus.
System address bus
of ISA on 8-bit slot. These pins are used as an
input when an ISA bus master o wns the bus and
are outputs at all other times.
SD[15:0]
I/O Data Bus.
These pins are the
external databus to the ISA bus.
ALE
Address Latch En able.
This is the address
latch enable output of the ISA bus and is asserted
by the STPC Elite to indicate that LA23-17, SA190, AEN and SBHE# signals are valid. The ALE is
driven high during refresh, DMA master or an ISA
master cycles by the STPC Elite. ALE is driven
low after re se t.
MEMR#
Memory Read.
This is the memory read
command signal of the IS A bus. It is used as an
input when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
MEMW#
Memory Write.
This is the memory write
command signal of the IS A bus. It is used as an
input when an ISA master owns the bus and is an
output at all other times.
SMEMR#
System Memory Read.
The STPC Elite
generates SMEMR# signal of the ISA bus only
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when the address is bel ow one megabyte or the
cycle is a refresh cycle.
SMEMW#
System Me mory Write.
The STPC Eli te
generates SMEMW# signal of the ISA bus only
when the address is below one megabyte.
IOR#
I/O Read.
This is the IO read command
signal of the ISA bus. It is an input when an ISA
master owns the bus an d is an out put at al l other
times .
IOW#
I/O Write.
This is the IO write command
signal of the ISA bus. It is an input when an ISA
master owns the bus an d is an out put at al l other
times .
MCS16#
Memory Chip Select16.
This is the
decode of LA23-17 address pins of the ISA
address bus without any qualification of the
command signal lines. MCS16# is always an
input. The STPC Elite ignores this signal during IO
and refresh cycles.
IOCS16#
IO Chip Select16.
This signal is the
decode of SA15-0 address pins of the ISA
address bus without any qualification of the
command signals. The STPC Elite doe s not drive
IOCS16# (similar to PC-AT design). An ISA
master access to an internal registe r of the S TPC
Elite is executed as an extended 8-bit IO cycle.
BHE#
System Bus High Enable.
This signal, when
asserted, indicates that a data byte is being
transferred on SD15-8 lines. It is used as an input
when an ISA master owns the bus and is an
output at all other times.
ZWS#
Zero Wait Stat e.
This signal, when asserted by addressed device, indicates that current cycle can be shortened.
REF#
Refresh Cycle.
This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Elite perf orms a refresh cycle on
the ISA bus. It is used as an input when an ISA
master owns the bus and is used to trigger a
refresh cycle.
The STPC Elite performs a pseudo hidden
refresh. It requests the host bus for two host
clocks to drive the refresh address and capture it
in external buffers. The host bus is then
relinquished while the refresh cycle continues on
the ISA bus.
MASTER#
Add On Card Owns Bus.
This signal is
active when an ISA device h as been granted bus
ownership.
AEN
Address Enable.
Address Enable is enabl ed
when the DMA controller is the bus owner to
indicate that a DMA transfer will occur. The
enabling of the signal indicat es to IO devices to
ignore the IOR#/IOW# signal during DMA
transfers.
IOCHCK#
IO Channel Che ck.
IO Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal
becomes active upon seeing IOCHCK# active if
the corresponding bit in Port B is enabled.
IOCHRDY
Channel Ready.
IOCHRDY is the IO
channel ready signal of the ISA bus and is driven
as an output in response to an ISA master cycle
targeted to the host bus or an internal register of
the STPC Elite. The STPC Elite monitors this
signal as an input when performing an ISA cycle
on behalf of the host CPU, DMA master or refresh.
ISA masters which do not monitor IOCHRDY are
not guaranteed to work with the STPC Elite since
the access to the system memory can be
considerably delayed due UMA architecture.
ISAOE#
Bidirectional OE Control.
This signal
controls the OE
signal of the external transceiver
that connects the IDE DD bus and ISA SA bus.
GPIOCS#
I/O General Purpo se Chip Select .
This
output signal is used by the external la tch on ISA
bus to latch the data on the SD[7:0] bus. The latch
can be use by PMU unit to control the external
peripheral devices or any other desired function.
IRQ_MUX[3:0]
Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They
have to be encoded before connection to the
STPC Elite using ISACLK and ISACLKX2 as the
input selection strobes.
Note that IRQ8B, which by convention is
connected to the RTC, is inverted before being
sent to the interrupt c ontroller, so that it may be
connected directly to the IRQ
pin of the RTC.
DREQ_MUX[1:0]
ISA Bus Multiplexed DMA
Request.
These are the ISA bus DMA request
signals. They are to be encoded before
connection to the STPC Elite us ing ISACLK and
ISACLKX2 as the input selection strobes.
DACK_ENC[2:0]
DMA Acknowledge.
These are
the ISA bus DMA ac knowledge sig nals. They are
encoded by the STPC Elite before output and
should be decoded ext ernally using ISACLK and
ISACLKX2 as the control strobes.
TC
ISA Terminal Count.
This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the byte count expires.
2.2.5. X- BUS IN TERFACE PINS
RTCAS
Real time clock address strobe.
This
signal is asserted for any I/O write to port 70H.
PIN DESCRIPTION
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RMRTCCS#
ROM/Real Time clock chip select.
This signal is asserted if a ROM access is
decoded during a memory cycle. It should be
combined with MEMR# or MEMW# signals to
properly access the ROM. During a IO cycle, this
signal is asserted if access to the Real Time Clock
(RTC) is decoded. It should be combined with IOR
or IOW# signals to properly acces s the real time
clock.
KBCS#
Keyboard Chip Select.
This signal is
asserted if a keyboard access is decoded during a
I/O cycle.
RTCRW#
Real Time Clock RW.
This pin is a multifunction pin. When ISAOE# is active, this signal is
used as RTCRW#. This signal is asserted for any
I/O write to port 71H.
RTCDS#
Real Time Clock DS
. This pin is a multifunction pin. When ISAOE# is active, this signal is
used as RTCDS# This signal is asserted for any I/
O read to port 71H. Its polarity complies with the
DS pin of the MT48T86 RTC device when
configured with Intel timings.
Note: RMRTCCS#, KBCS#, RTCRW# and
RTCDS# signals must be ORed externally with
ISAOE# and then connected to the external
device. An LS244 or equivalent function can be
used if OE# is connected to ISAOE# and the
output is provided with a weak pull-up resistor as
shown in Design Guidelines chapter.
2.2.6. LOCAL BUS
PA[23:0]
Address Bus Output.
PD[15:0]
Data Bus.
This is the 16-bit data bus.
D[7:0] is the LSB and PD[15:8] is the MSB.
PRD#[1:0]
Read Control output.
PRD0# is used to
read the LSB and PRD1# to read the MSB.
PWR#[1:0]
Write Control output.
PWR0# is used
to write the LSB and PWR1# to write the MSB.
PRDY
Data Ready input.
This signal is used to
create wait states on the bus. When high, it
completes the current cycle.
FCS#[1:0]
Flash Chip Select output.
These are
the Programmable Chip Select signals for up to 2
banks of Flash memory.
IOCS#[3:0]
I/O Chip Select output.
These are the
Programmable Chip Select signals for up to 4
external I/O devices.
2.2.7. IDE INTERFACE
DA[2:0]
Address.
These signals are connected to
DA[2:0] of IDE devices directly or through a buffer.
If the toggling of sign als are t o be m asked du ring
ISA bus cycles, they can be externally ORed with
ISAOE# before being connected to the IDE
devices.
DD[15:0]
Databus.
When the IDE bus is active,
they serve as IDE signals D D[11:0]. IDE devices
are connected to SA[19:8] directly and ISA bus is
connected to these pins through two LS245
transceivers as described in Design Guidelines
chapter.
PCS1#, PCS3#
Primary Chip Select.
These
signals are used as the active high primary master
& slave IDE chip select signals. These signals
must be externally ANDed with the ISAOE
#
signal
before driving the I DE devices to guarantee it is
active only when ISA bus is idle.
SCS1#, SCS3#
Secondary Chip Select.
These
signals are used as the active high secondary
master & slave IDE chip select signals. These
signals must be externally ANDed with the
ISAOE
#
signal before driving the IDE devices to
guarantee it is active only when ISA bus is idle.
DIORDY
Busy/Ready.
This pin serves as IDE
signal DIORDY.
PIRQ
Primary Interrupt Request.
SIRQ
Secondary Interrupt Request.
Interrupt request from IDE channels.
PDRQ
Primary DMA Request.
SDRQ
Secondary DMA Request.
DMA request from IDE channels.
PDACK#
Primary DMA Acknowledge.
SDACK#
Secondary DMA Acknowledge.
DMA acknowledge to IDE channels.
PDIOR#, PDIOW#
Primary I/O Read & Write.
SDIOR#, SDIOW#
Secondary I/O Read & Write
.
Primary & Secondary channel read & write.
2.2.8. JTAG INTERFACE
TCLK
Test clock
TDI
Test data input
TMS
Test mode input
TDO
Test data output
2.2.9. MISCELLANEOUS
GPIO[15:0]
General Purpose I/Os
SPKRD
Speaker Drive.
This the output to the
speaker and is an AND of the counter 2 output
with bit 1 of Port 61, and dri ves an external speak-
PIN DESCRIPTION
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er driver. This output should be connected to 7407
type high voltage driver.
SCL, SDA
I²C Interface
.
These bidirectional pins
are connected to register 22h/23h index 97h. They
confo rm to I
2
C electrical specifications, they hav e
open-collector output drivers which are internally
connected to V
DD
through pull-up resistors.
SCAN_ENABLE
Reserved
. The pin is reserved
for Test and Miscellaneous functions.
VDD_CORE
2.5V Core Power Supply.
VDD
3.3V I/O Power Supply.
VDD_PLL
PLL Power Supplies.
CPUCLK PLL,
DEVCLK PLL, MCKLI PLL, MCLKO PLL, HCLK
PLL.
VSS
Connected to GND.
PIN DESCRIPTION
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..
Table 2-4. ISA / IDE Dynamic Multiplexing
ISA BUS
(ISAOE# = 0)
IDE
(ISAOE# = 1)
RMRTCCS# DD[15]
KBCS# DD[14]
RTCRW# DD[13]
RTCDS# DD[12]
SA[19:8] DD[11:0]
LA[23] SCS3#
LA[22] SCS1#
SA[21] PCS3#
SA[20] PCS1#
LA[19:17] DA[2:0]
IOCHRDY DIORDY
Table 2-5. ISA / Local Bus Pin Sharing
ISA / IPC LOCAL BUS
SD[15:0] PD[15:0]
DREQ_MUX[1:0] PA[21:20]
SMEMR# PA[19]
MEMW# PA[18]
BHE# PA[17]
AEN PA[16]
ALE PA[15]
MEMR# PA[14]
IOR# PA[13]
IOW# PA[12]
REF# PA[11]
IOCHCK# PA[10]
GPIOCS# PA[9]
ZWS# PA[8]
SA[7:4] PA[7:4]
TC, DACK_ENC[2:0] PA[3:0]
SA[3] PRDY
ISAOE#,SA[2:0] IOCS#[3:0]
DEV_CLK, RTCAS FCS#[1:0]
IOCS16#, MASTER# PRD#[1:0]
SMEMW#, MCS16# PWR#[1:0]
Table 2-6. Signal value on Reset
Signal Name SYSRSTI# active
SYSRSTI# inactive
SYSRSTO# active
release of SYSRSTO#
BASIC CLOCKS AND RESETS
XTALO 14MHz
ISA_CLK Low 7MHz
ISA_CLK2X, OSC14M 14MHz
GPCLK 24MHz
HCLK Oscillating at the speed defined by the strap options.
PCI_CLKO HCLK divided by 2 or 3, depending on the strap options.
MEMORY CONTROLLER
MCLKO 66MHz if asynchonous mode, HCLK speed if synchronized mode.
CS#[3:1] High
CS#[0] High
SDRAM init sequence:
Write Cycles
MA[10:0], BA[0] 0x00
RAS#[1:0], CAS#[1:0] High
MWE#, DQM[7:0] High
MD[63:0] Input
PCI INTERFACE
AD[31:0] 0x0000
First prefetch cycles
when not in Local Bus mode.
CBE[3:0], PAR Low
FRAME#, TRDY#, IRDY# Input
STOP#, DEVSEL# Input
SERR# Input
PCI_GNT#[2:0 ] High
ISA BUS INTERFACE
PIN DESCRIPTION
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ISAOE# High Low
RMRTCCS# Hi-Z
First prefetch cycles
when in ISA or PCMCIA mode.
Address start is 0xFFFFF0
LA[23:17] Unknown 0x00
SA[19:0] 0xFFFXX 0xFFF03
SD[15:0] Unknown 0xFF
BHE#, MEMR# Unknown High
MEMW#, SMEMR#, SMEMW#, IOR#, IOW# Unknown High
REF# Unknown High
ALE, AEN Low
DACK_ENC[2:0] Input 0x04
TC Input Low
GPIOCS# Hi-Z High
RTCDS#, RTCRW#, KBCS# Hi-Z
RTCAS Unknown Low
LOCAL BUS INTERFACE
PA[24:0] Unknown
First prefetch cycles
PD[15:0] Unknown 0xFF
PRD# Unknown High
PBE#[1:0], FCS0#, FCS_0H# High
FCS_0L#, FCS1#, FCS_1H#, FCS_1L# High
PWR#, IOCS#[7:0] High
IDE CONTROLLER
DD[15:0] 0xFF
DA[2:0] Unknown Low
PCS1, PCS3, SCS1, SCS3 Unknown Low
PDACK#, SDACK# High
PDIOR#, PDIOW#, SDIOR#, SDIOW# High
I2C INTERFACE
SCL / DDC[1] Input
SDA / DDC[0] Input
GPIO SIGNALS
GPIO[15:0] High
JTAG
TDO High
MISCELLANEOUS
SPKRD Low
Table 2-6. Signal value on Reset
Signal Name SYSRSTI# active
SYSRSTI# inactive
SYSRSTO# active
release of SYSRSTO#
PIN DESCRIPTION
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Table 2-7. Pinout.
Pin # Pin name
AF3 SYSRSETI#
AE4 SYSRSETO#
A3 XTALI
C4 XTALO
G23 HCLK
2
H24 GP_CLK
AF15 MCLKI
AB23 MCLKO
AE16 MA[0]
AD15 MA[1]
AF16 MA[2]
AE17 MA[3]
AD16 MA[4]
AF17 MA[5]
AE18 MA[6]
AD17 MA[7]
AF18 MA[8]
AE19 MA[9]
AE20 MA[10]
AC19 BA[0]
AF22 CS#[0]
AD21 CS#[1]
AE24 CS#[2]/MA[11]
AD23 CS#[3]/MA[12]/BA[1]
AF23 RAS#[0]
AD22 RAS#[1]
AE21 CAS#[0]
AC20 CAS#[1]
AF20 DQM#[0]
AD19 DQM#[1]
AF21 DQM#[2]
AD20 DQM#[3]
AE22 DQM#[4]
AE23 DQM#[5]
AF19 DQM#[6]
AD18 DQM#[7]
AC22 MWE#
R1 MD[0]
3
T2 MD[1]
3
R3 MD[2]
T1 MD[3]
R4 MD[4]
U2 MD[5]
T3 MD[6]
U1 MD[7]
For Note definition see Table 2-2
Definition of Signal Pins
U4 MD[8]
3
V2 MD[9]
3
U3 MD[10]
V1 MD[11]
W2 MD[12]
V3 MD[13]
Y2 MD[14]
W4 MD[15]
Y1 MD[16]
W3 MD[17]
AA2 MD[18]
Y4 MD[19]
AA1 MD[20]
Y3 MD[21]
AB2 MD[22]
AB1 MD[23]
AA3 MD[24]
AB4 MD[25]
AC1 MD[26]
AB3 MD[27]
AD2 MD[28]
AC3 MD[29]
AD1 MD[30]
AF2 MD[31]
AF24 MD[32]
AE26 MD[33]
AD25 MD[34]
AD26 MD[35]
AC25 MD[36]
AC24 MD[37]
AC26 MD[38]
AB25 MD[39]
AB24 MD[40]
AB26 MD[41]
AA25 MD[42]
Y23 MD[43]
AA24 MD[44]
AA26 MD[45]
Y25 MD[46]
Y26 MD[47]
Y24 MD[48]
W25 MD[49]
3
V23 MD[50]
3
W26 MD[51]
3
W24 MD[52]
3
V25 MD[53]
3
V26 MD[54]
3
Pin # Pin name
For Note definition see Table 2-2
Definition of Signal Pins
U25 MD[55]
3
V24 MD[56]
3
U26 MD[57]
3
U23 MD[58]
3
T25 MD[59]
3
U24 MD[60]
3
T26 MD[61]
3
R25 MD[62]
3
R26 MD[63]
3
F24 PCI_CLKI
2
D25 PCI_CLKO
B20 AD[0]
C20 AD[1]
B19 AD[2]
A19 AD[3]
C19 AD[4]
B18 AD[5]
A18 AD[6]
B17 AD[7]
C18 AD[8]
A17 AD[9]
D17 AD[10]
B16 AD[11]
C17 AD[12]
B15 AD[13]
A15 AD[14]
C16 AD[15]
B14 AD[16]
D15 AD[17]
A14 AD[18]
B13 AD[19]
D13 AD[20]
A13 AD[21]
C14 AD[22]
B12 AD[23]
C13 AD[24]
A12 AD[25]
C12 AD[26]
A11 AD[27]
D12 AD[28]
B10 AD[29]
C11 AD[30]
A10 AD[31]
D10 CBE[0]
C10 CBE[1]
A9 CBE[2]
Pin # Pin name
For Note definition see Table 2-2
Definition of Signal Pins
PIN DESCRIPTION
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B8 CBE[3]
A8 FRAME#
B7 TRDY#
D8 IRDY#
A7 STOP#
C8 DEVSEL#
B6 PAR
D7 SERR#
A6 LOCK#
D20 PCI_REQ#[0]
C21 PCI_REQ#[1]
A21 PCI_REQ#[2]
C22 PCI_GNT#[0]
A22 PCI_GNT#[1]
B21 PCI_GNT#[2]
A5 PCI_INT[0]
C6 PCI_INT[1]
B4 PCI_INT[2]
D5 PCI_INT[3]
F2 LA[17]/DA[0]
G4 LA[18]/DA[1]
F3 LA[19]/DA[2]
F1 LA[20]/PCS1#
G2 LA[21]/PCS3#
G1 LA[22]/SCS1#
H2 LA[23]/SCS3#
J4 SA[0]
H1 SA[1]
H3 SA[2]
J2 SA[3]
J1 SA[4]
K2 SA[5]
J3 SA[6]
K1 SA[7]
K4 SA[8]
L2 SA[9]
K3 SA[10]
L1 SA[11]
M2 SA[12]
M1 SA[13]
L3 SA[14]
N2 SA[15]
M4 SA[16]
M3 SA[17]
P2 SA[18]
P4 SA[19]
Pin # Pin name
For Note definition see Table 2-2
Definition of Signal Pins
K25 SD[0]
L24 SD[1]
K26 SD[2]
K23 SD[3]
J25 SD[4]
K24 SD[5]
J26 SD[6]
H25 SD[7]
H26 SD[8]
J24 SD[9]
G25 SD[10]
H23 SD[11]
D24 SD[12]
C26 SD[13]
A25 SD[14]
B24 SD[15]
AD4 ISA_CLK
AF4 ISA_CLK2X
C9 OSC14M
P25 ALE
AE8 ZWS#
R23 BHE#
P26 MEMR#
R24 MEMW#
N25 SMEMR#
N23 SMEMW#
N26 IOR#
P24 IOW#
N24 MCS16#
M26 IOCS16#
M25 MASTER#
L25 REF#
M24 AEN
L26 IOCHCK#
T24 IOCHRDY
M23 ISAOE#
A4 RTCAS
P3 RTCDS#
R2 RTCRW#
P1 RMRTCCS#
AE3 GPIOCS#
G26 PA[22]
2
A20 PA[23]
B1 PIRQ
Pin # Pin name
For Note definition see Table 2-2
Definition of Signal Pins
C2 SIRQ
C1 PDRQ
D2 SDRQ
D3 PDACK#
D1 SDACK#
E2 PDIOR#
E4 PDIOW#
E3 SDIOR#
E1 SDIOW#
E23 IRQ_MUX[0]
D26 IRQ_MUX[1]
E24 IRQ_MUX[2]
C25 IRQ_MUX[3]
A24 DREQ_MUX[0]
B23 DREQ_MUX[1]
C23 DACK_ENC[0]
A23 DACK_ENC[1]
B22 DACK_ENC[2]
D22 TC
N3 KBCS#
AE5 GPIO[0]
AC5 GPIO[1]
AD5 GPIO[2]
AF5 GPIO[3]
AE6 GPIO[4]
AC7 GPIO[5]
AD6 GPIO[6]
AF6 GPIO[7]
AE7 GPIO[8]
AF7 GPIO[9]
AD7 GPIO[10]
AD8 GPIO[11]
AE9 GPIO[12]
AF9 GPIO[13]
AE10 GPIO[14]
AD9 GPIO[15]
C5 SPKRD
B5 SCL
C7 SDA
B3 SCAN_ENABLE
G3 TCLK
N1 TMS
W1 TDI
AC2 TDO
Pin # Pin name
For Note definition see Table 2-2
Definition of Signal Pins
PIN DESCRIPTION
Release 1.3 - January 29, 2002 25/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
G24 VDD_CPUCLK_PLL
1
F25 VDD_DEVCLK_PLL
1
AC17 VDD_MCLKI_PLL
1
AC15 VDD_MCLKO_PLL
1
F26 VDD_HCLK_PLL
1
D11 VDD_CORE
1
L23 VDD_CORE
1
T4 VDD_CORE
1
AC6 VDD_CORE
1
D6 VDD
D16 VDD
D21 VDD
F4 VDD
F23 VDD
L4 VDD
T23 VDD
AA4 VDD
AA23 VDD
AC11 VDD
AC16 VDD
AC21 VDD
E25 VDD_PLL_SKEW
A1:2 VSS
A26 VSS
B2 VSS
B25:26 VSS
C3 VSS
C24 VSS
D4 VSS
D9 VSS
D14 VSS
D19 VSS
D23 VSS
H4 VSS
J23 VSS
L11:16 VSS
M11:16 VSS
N4 VSS
N11:16 VSS
P11:16 VSS
P23 VSS
R11:16 VSS
T11:16 VSS
V4 VSS
W23 VSS
AC4 VSS
Pin # Pin name
For Note definition see Table 2-2
Definition of Signal Pins
AC8 VSS
AC13 VSS
AC18 VSS
AC23 VSS
AD3 VSS
AD14 VSS
AD24 VSS
AE1:2 VSS
AE25 VSS
AF1 VSS
AF25 VSS
AF26 VSS
A16
Unconnected
B9
Unconnected
B11
Unconnected
C15
Unconnected
D18
Unconnected
E26
Unconnected
AC9
Unconnected
AC10
Unconnected
AC12
Unconnected
AC14
Unconnected
AD10
Unconnected
AD11
Unconnected
AD12
Unconnected
AD13
Unconnected
AE11
Unconnected
AE12
Unconnected
AE13
Unconnected
AE14
Unconnected
AE15
Unconnected
AF8
Unconnected
AF10
Unconnected
AF11
Unconnected
AF12
Unconnected
AF13
Unconnected
AF14
Unconnected
Pin # Pin name
For Note definition see Table 2-2
Definition of Signal Pins
PIN DESCRIPTION
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STRAP OPTION
Release 1.3 - January 29, 2002 27/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
3. STRAP OPTION
Thi s ch apter de f i nes t h e S TPC El i t e S t ra p Op ti o ns
and their location. Some strap opt ions have been
left programmable for future versions of silicon..
Table 3-1. Strap Options
Signal Designation Actual Settings
1
Set to’0’ Set to’1’
MD2
HCLK_PLL speed
User defined see Section 3.1.4. bit 6
MD3
User defined see Section 3.1.4. bit 7
MD4
PCI_CLKO divisor User defined see Section 3.1.1. bit 4
MD5
MCLK/HCLK Sync (see Section 3.1.1. ) User defined Async Sync
MD6
PCI_CLKO setup User defined see Section 3.1.1. bit 6
MD7
Reserved Pull down - -
MD10
Reserved Pull down - -
MD11
Reserved Pull down - -
MD16
Reserved Pull up - -
MD17
PCI_CLKO divisor User defined see Section 3.1.3. bit 1
MD18
Reserved Pull Up - -
MD19
Reserved Pull Up - -
MD20
Reserved Pull Up - -
MD21
Reserved Pull Up - -
MD22
Reserved Pull up - -
MD23
Reserved Pull up - -
MD24
HCLK PLL speed
User defined see Section 3.1.4. bit 3
MD25
User defined see Section 3.1.4. bit 4
MD26
User defined see Section 3.1.4. bit 5
MD27
Reserved Pull down
MD28
Reserved Pull down
MD29
Reserved Pull down
MD30
Reserved Pull down
MD40
CPU clock multiplication factor User defined X1 X2
MD41
Reserved Pull down - -
MD42
Reserved Pull up - -
MD43
Reserved Pull down - -
MD44
Bus select User defined ISA Local Bus
MD45
Reserved Pull down - -
MD46
Reserved Pull up - -
MD47
Reserved Pull down - -
MD48
Reserved Pull up - -
TC
Reserved Pull up
DACK_ENC[2:0] Reserved Pull up
Note1: Where a strap is represented by a ’Pull up’ or ’Pull down’, these have to be adhered to. If it is represented as a ’’ it can be left unconnected. Where ’User defined’, the strap is set by the user.
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