SGS Thomson Microelectronics ST62T28CM6, ST62T28CM3, ST62T28CB6, ST62T28CB3, ST62P28CM6 Datasheet

November 1999 1/84

Rev. 2.8

ST62T28C/E28C

8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD

TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHzMaximum Clock Frequency

■ -40 to+125°C Operating TemperatureRange

■ Run, Wait and Stop Modes

■ 5 InterruptVectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 192 bytes

■ User Programmable Options

■ 20 I/O pins, fully programmable as:

– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input

■ 8 I/Olinescan sink up to 20mA todrive LEDs or

TRIACs directly

■ 8-bit Timer/Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timer with 7-bit programmable

prescaler (AR Timer)

■ Digital Watchdog

■ 8-bit A/D Converter with 12 analog inputs

■ 8-bit Asynchronous Peripheral Interface

(UART)

■ 8-bit Synchronous Peripheral Interface (SPI)

■ On-chip Clock oscill ator can be driven by

Quartz Crystal, Ceramic resonator or RC
network

■ Oscillator SafeGuard

■ Low Voltage Detector for safe Reset

■ One external Non-Maskable Interrupt

■ ST623x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a
parallel port).

DEVICE SUMMARY

DEVICE

OTP

(Bytes)

EPROM

(Bytes)

I/O Pins

ST62T28C 7948 - 20
ST62E28C 7948 20

(See end of Datasheet for Ordering Information)

PDIP28

PS028

CDIP28W

SS0P28

1

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Page

2

ST62T28C/E28C . ....................................1

1 GENERAL DESCRIPTION . .. . . . ................................................ 5

1.1 INTRODUCTION . . . . . . . . . . . . . ............................................ 5

1.2 PIN DESCRIPTIONS . . . . . . ................................................6

1.3 MEMORY MAP . . . . . . . . . . ................................................7

1.3.1 Introduction . . . ..................................................... 7

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . .................................. 7

1.3.3 Data Space . . . . . . . . .. . . . . . . . .. . . . . . . ............................... 9

1.3.4 Stack Space . . .. . . . . . . . ............................................. 9

1.3.5 Data Window Register (DWR) . ........................................10

1.3.6 Data RAM Bank Register (DRBR) . . . . .................................. 11

1.4 PROGRAMMING MODES . . . . . .. . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . 12

1.4.1 Option Bytes . . .. . . . . . . . . . . . . .. . . . . . . .............................. 12

2 CENTRAL PROCESSING UNIT . . ............................................... 13

2.1 INTRODUCTION . . . . . . . . . . . . . ...........................................13

2.2 CPU REGISTERS . . . .................................................... 13

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . .................... 15

3.1 CLOCK SYSTEM . . . . . . . . . . . . . ........................................... 15

3.1.1 Main Oscillator . .. . . . . . . .. . .. . . . . . . ................................. 15

3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . 16

3.1.3 Oscillator Safe Guard . . . . . ...........................................16

3.2 RESETS . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 19

3.2.1 RESET Input . . .................................................... 19

3.2.2 Power-on Reset .................................................... 19

3.2.3 Watchdog Reset . . . . . . . .. . .. . . . . . . ................................. 20

3.2.4 LVD Reset . . . . .. . . . ...............................................20

3.2.5 Application Notes . . . ................................................ 20

3.2.6 MCU Initialization Sequence . . . . . . . . ..................................21

3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . .................................. 23

3.3.1 Digital Watchdog Register (DWDR) . . . . . . .. . . . . .. . .. . . .. . . . . . . . . . . . . . . . . 25

3.3.2 Application Notes . . . ................................................ 25

3.4 IINTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................... 27

3.4.1 Interrupt request . ................................................... 27

3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . ................................. 28

3.4.3 Interrupt Option Register(IOR) . . . . . . . . . . . . . . . . . . . . . . .. . ............... 29

3.4.4 Interrupt sources . . . . . . . . . . . ........................................29

3.5 POWER SAVING MODES . .. . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . ........ 32

3.5.1 WAIT Mode ....................................................... 32

3.5.2 STOP Mode . .. . . .. . ...............................................32

3.5.3 Exit from WAIT and STOP Modes . . . . .................................. 33

4 ON-CHIP PERIPHERALS . . . .. . . . . . . ........................................... 34

4.1 I/O PORTS . . . . . . . . . . .. . .. . . ............................................ 34

4.1.1 Operating Modes . . . . . . .. . . . . . . . . . . . . . . . . ........................... 35

4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 36

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4.1.3 ARTimer alternate functions . . . . .. . .. . . . . . . ........................... 38

4.1.4 SPI alternate functions . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 38

4.1.5 UART alternate functions . . . . .. . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . .. . . . . 38

4.1.6 I/O Port Option Registers . . . . .. . . . . . .................................. 40

4.1.7 I/O Port Data Direction Registers . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 40

4.1.8 I/O Port Data Registers . . . . . . ........................................40

4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ................................. 41

4.2.1 Timer Operating Modes . . .. . .. . . .. . .................................. 42

4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . ................................42

4.2.3 Application Notes . . . ................................................ 43

4.2.4 Timer Registers . . . . . ...............................................43

4.3 AUTO-RELOAD TIMER . . . . . . . . . .. . . .. . .. . . ............................... 44

4.3.1 AR Timer Description . . . . . . . . ........................................44

4.3.2 Timer Operating Modes . . .. . .. . . .. . .................................. 44

4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . ................................. 48

4.4 A/D CONVERTER (ADC) . . ............................................... 50

4.4.1 Application Notes . . . ................................................ 50

4.5 U. A. R. T. (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) . . . . . . . . . . . 52

4.5.1 Ports Interfacing .................................................... 52

4.5.2 Clock Generation . . . . . . . . . . . . . . . . .. . . ............................... 53

4.5.3 Data Transmission . . . ...............................................53

4.5.4 Data Reception .. . . . ...............................................54

4.5.5 Interrupt Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 54

4.5.6 Registers . . . . . . . . . . ...............................................54

4.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . .. . . . . . . . . . . . . .. . . ............ 56

5 SOFTWARE . . . . . . . . . . . . . . . . . ............................................... 58

5.1 ST6 ARCHITECTURE . ................................................... 58

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . .................................. 58

5.3 INSTRUCTION SET . . . . . . . ............................................... 59

6 ELECTRICAL CHARACTERISTICS . .. . . . . . . . . . . . . ............................... 64

6.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................64

6.2 RECOMMENDED OPERATING CONDITIONS . . . .............................. 65

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . .. . .. . . . . . . . . . . . . .. . . ............ 66

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . 67

6.5 A/D CONVERTERCHARACTERISTICS . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 68

6.6 TIMER CHARACTERISTICS . . . . ........................................... 68

6.7 SPI CHARACTERISTICS . . ...............................................68

6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . ........................... 68

7 GENERAL INFORMATION . . .. . . . . . . ...........................................74

7.1 PACKAGE MECHANICALDATA . . . . . . .. . . . . . . . . . ........................... 74

7.2 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 76

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Page

ST62P28C . . . . . . . . . . . . . . . . . . . . . . . . . ................77

1 GENERAL DESCRIPTION . .. . . . ............................................... 78

1.1 INTRODUCTION . . . . . . . . . . . . . ...........................................78

1.2 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 78

1.2.1 Transfer of Customer Code . . . . . . . . . . ................................. 78

1.2.2 Listing Generation and Verification . . . . ................................. 78

ST6228C ...........................................81

1 GENERAL DESCRIPTION . .. . . . ............................................... 82

1.1 INTRODUCTION . . . . . . . . . . . . . ...........................................82

1.2 ROM READOUT PROTECTION .. . .. . . . . . . . ................................82

1.3 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 84

1.3.1 Transfer of Customer Code . . . . . . . . . . ................................. 84

1.3.2 Listing Generation and Verification . . . . ................................. 84

4

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ST62T28C/E28C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST62T28C and ST62E28C devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which are targeted at low to
medium complexity applications. All ST62xx de­vices are based on a building block approach: a
common core is surrounded by a number of on­chip peripherals.

The ST62E28C isthe erasableEPROM versionof
the ST62T28C device, which may be used to em­ulate theST62T28C device, as well as the respec­tive ST6228C ROM devices.

OTP and EPROM devices are functionally identi­cal. The ROM basedversions offer the same func­tionality selecting as ROM options the options de-

fined in the programmable option byte of the OTP/
EPROM versions.OTP devices offerall theadvan­tages of user programmability at low cost, which
make them the ideal choice in a wide range of ap­plications where frequent code changes, multiple
code versions or last minute programmability are
required.

These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program­mable prescaler, an 8-bit Auto-Reload Timer, with
1 input capture channel, capability, a serial asyn­chronous port interface (UART), a synchronous
serial port interface, an 8-bit A/D Converterwith 12
analog inputs and a Digital Watchdog timer, mak­ing them well suited for a wide range of automo-

Figure 1. Block Diagram

TEST

NMI

INTERRUPT

PROGRAM

PC

STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6

POWER

SUPPLY

OSCILLATOR

RESET

DATA ROM

USER

SELECTABLE

DATA RAM

PORT A

PORT B

TIMER

DIGITAL

8 BIT CORE

TEST/V

PP

8-BIT

A/D CONVERTER

V

DDVSS

OSCin OSCout RESET

WATCHDOG

Memory

PORT C

AUTORELOAD

TIMER

192 Bytes

7948 bytes

PB4..PB6/Ain

PC4..PC5/Ain

PORT D

PD6,PD7/Ain

PD1/Ain/Scl
PD2/Ain/Sin
PD3/Ain/Sout
PD4/Ain/RXD1
PD5/Ain/TXD1

(V

PP

on EPROM/OTP versionsonly)

TIMER

VR01823F

UART

PC6..PC7/20 mA Sink

SPI

PA0..PA1 / 20 mA Sink
PA2/ARTIMout / 20 mA Sink
PA3/ARTIMin/ 20 mA Sink
PA4..PA5/20 mASink

5

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ST62T28C/E28C

1.2 PIN DESCRIPTIONS
VDDand VSS. Power is supplied to the MCU via

these two pins. VDDis the power connection and
VSSis the ground connection.

OSCin and OSCout. These pins are internally
connected tothe on-chip oscillatorcircuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.

RESET. The active-low RESET pin is used to re­start themicrocontroller.

TEST/VPP. The TEST must be held at VSSfor nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM/
OTP programming Mode is entered.

NMI. TheNMI pinprovides the capability for asyn­chronous interruption,by applying anexternal non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive with Schmitt trigger charac­teristics. The user can select as optionthe availa­bility of an on-chip pull-up at this pin.

PA0-PA5. These 6 lines are organised as one I/O
port (A). Each line may be configured under soft­ware controlas inputs with or without internal pull­up resistors, input with interrupt generation and
pull-up resistor, open-drain or push-pull outputs.
PA2/ARTIMout and PA3/ARTIMin can beused re­spectively as output and input pins for the embed­ded 8-bitAuto-Reload Timer.

In addition, PA0-PA5 can sink 20mAfor direct LED
or TRIAC drive.

PB4...PB6. These 3 lines areorganised asone I/O
port (B). Each line may be configured under soft­ware controlas inputs with or without internal pull­up resistors, input with interrupt generation and
pull-up resistor, open-drain or push-pull outputs,
analog inputsfor the A/D converter.

PC4-PC7. These 4 lines are organised as one I/O
port (C). Each line may be configured under soft­ware control as input with or without internal pull­up resistor, input with interrupt generation and
pull-up resistor, open-drain or push-pull output.

PC4 and PC5 can also beused as analog input for
the A/D converter, while PC6 and PC7 can sink
20mA for direct LED or TRIAC drive.

PD1...PD7. These7 lines are organised asoneI/O
port (portD). Each line may be configured under
software control as input with or without internal
pull-up resistor, input with interruptgeneration and
pull-up resistor, analog input open-drain or push­pull output. In addition, the pins PD5/TXD1 and
PD4/RXD1 can be used as UART output (PD5/
TXD1) or UARTinput (PD4/RXD1). Thepins PD3/
Sout, PD2/Sin and PD3/Scl can also be used re­spectively as data out, data in and clock pins for
the on-chip SPI.

TIMER.This is the TIMER 1 I/O pin. In input mode,
it is connected to the prescaler and acts as ex­ternal timer clockor ascontrol gate for the internal
timer clock.In output mode, the TIMERpin outputs
the data bit when a time-out occurs.The user can
select as option the availability of an on-chip pull­up at this pin.

Figure 2. ST62T28C/E28C Pin Configuration

1
2
3
4
5
6
7
8
9
10
11
12
13

14

15

16

17

18

19

20

V

DD

TIMER

OSCin

OSCout

NMI

TEST/V

PP

(1)

RESET

PC7*

PC6*

Ain/PC5

V

SS

PA0*
PA1*
PA2*/ARTIMout
PA3*/ARTIMin

PD3/Ain/Sout
PD4/Ain/RXD1
PD5/Ain/TXD1
PD6/Ain

PD7/Ain

28
27
26
25
24
23
22
21

Ain/PC4

Ain/PB6
Ain/PB5
Ain/PB4

PA4*
PA5*
PD1/Ain/Scl
PD2/Ain/Sin

(1) VPPon EPROM/OTP only

VR01804B

(*) 20 mA Sink

6

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ST62T28C/E28C

1.3 MEMORY MAP

1.3.1 Introduction

The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in thesethree memory spacesis
described in the following paragraphs.

Briefly, Program space contains user program
code in Program memory and user vectors; Data
space contains user data in RAM and in Program
memory, andStack space accommodates six lev­els of stack for subroutine and interrupt service
routine nesting.

1.3.2 Program Space

Program Space comprises the instructions to be
executed, the data required for immediate ad­dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed viathe 12-bit ProgramCounter register
(PC register).

Program Space is organised in 4K pages. 4 of
them are addressed in the 000h-7FFh locations of
the Program Space by the Program Counter and
by writing the appropriate code in the Program
ROM Page Register (PRPR register). A common

(STATIC) 2K pageis available all the time for inter­rupt vectors and common subroutines, independ­ently of the PRPR register content. This “STATIC”
page is directly addressed in the 0800h-0FFFh by
the MSB of the Program Counter register PC 11.
Note this page can also be addressed in the 000­7FFh range. It is two different ways of addressing
the same physical memory.

Jump from a dynamic page to another dynamic
page is achieved by jumping back to the static
page, changing contents of PRPR and then jump­ing to the new dynamic page.

Figure 3. 8Kbytes Program SpaceAddressing

Figure 4. Memory Addressing Diagram

PC
SPACE

000h

7FFh
800h

FFFh

0000h

1FFFh

Page 0

Page 1

Static
Page

Page 2

Page 1

Static
Page

ROM SPACE

Page 3

PROGRAM SPACE

PROGRAM

INTERRUPT &

RESET VECTORS

ACCUMULATOR

DATA RAM

BANK SELECT

WINDOW SELECT

RAM

X REGISTER
Y REGISTER
V REGISTER

W REGISTER

DATA READ-ONLY

WINDOW

RAM / EEPROM
BANKING AREA

000h

03Fh
040h

07Fh
080h
081h
082h
083h
084h

0C0h

0FFh

0-63

DATA SPACE

0000h

0FF0h

0FFFh

MEMORY

MEMORY

DATA READ-ONLY

MEMORY

VR01568

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ST62T28C/E28C

MEMORY MAP(Cont’d)
Table 1. ST62E28C/T28C Program Memory Map

Note: OTP/EPROM devices can be programmed

with thedevelopment toolsavailable fromSTMicro­electronics (ST62E3X-EPB or ST623X-KIT).

1.3.2.1 Program ROM Page Register (PRPR)

The PRPR register can be addressed like a RAM
location in the Data Space at the address CAh;
nevertheless it is a write only register that cannot
be accessed with single-bit operations. Thisregis­ter is used to select the 2-Kbyte ROM bank of the
Program Space that will be addressed. The
number ofthe page has to be loaded in the PRPR
register. Refer to the Program Space description
for additional information concerning the use of
this register. The PRPR register is not modified
when an interrupt or a subroutine occurs.

Care isrequired whenhandling the PRPR register
as it is write only. For this reason, it is not allowed
to change the PRPR contents while executing in­terrupt service routine, as the service routine
cannot save and then restore its previous content.
This operation may be necessary if common rou­tines andinterrupt service routines take morethan
2K bytes; in this case it could be necessary to di­vide the interrupt service routineinto a (minor) part
in the static page (start and end) and to a second
(major) part in one of the dynamic pages. Ifit isim­possible to avoid the writing of this register ininter­rupt service routines, an image of this register
must be saved in a RAM location, and each time
the program writes to the PRPR it must write also
to the image register. The image register must be
written before PRPR, so if an interrupt occurs be­tween the two instructions the PRPR is not af­fected.

Program ROM Page Register (PRPR)

Address: CAh — Write Only

Bits 2-7= Not used.
Bit 5-0 = PRPR1-PRPR0:

Program ROM Select.

These two bits select the corresponding page to
be addressed in the lower part of the 4K program
address space as specified in Table 2.

This register is undefined on Reset. Neither read
nor single bit instructions may be used to address
this register.

Table 2. 6Kbytes Program ROM Page Register

Coding

1.3.2.2 Program Memory Protection

The Program Memory in OTP or EPROM devices
can be protected againstexternal readout of mem­ory by selecting the READOUT PROTECTION op­tion in the option byte.

In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.

Note: Once the Readout Protectionis activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the Program memory contents.
Returned parts with a protection set can therefore
not be accepted.

ROM Page Device Address Description

Page 0

0000h-007Fh
0080h-07FFh

Reserved

User ROM

Page 1
“STATIC”

0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Vector

Reset Vector

Page 2

0000h-000Fh

0010h-07FFh

Reserved

User ROM

Page 3

0000h-000Fh

0010h-07FFh

Reserved

User ROM

70

- - - - - - PRPR1 PRPR0

PRPR1 PRPR0 PC bit 11 Memory Page

X X 1 Static Page (Page1)

0 0 0 Page 0
0 1 0 Page 1 (Static Page)
1 0 0 Page 2
1 1 0 Page 3

8

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ST62T28C/E28C

MEMORY MAP(Cont’d)

1.3.3 Data Space

Data Spaceaccommodates all the data necessary
for processingthe user program. This space com­prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in Program
memory.

1.3.3.1 Data ROM

All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con­tains the program code to be executed, as well as
the constants and look-up tables required by the
application.

The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in Program memory.

1.3.3.2 Data RAM

In ST6228C and ST62E28C devices, the data
space includes 60 bytes of RAM, the accumulator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the pe­ripheral data and control registers, the interrupt
option register andthe Data ROM Window register
(DRW register).

Additional RAM pages can also be addressed us­ing banks of 64 byteslocated between addresses
00h and3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as wellas thecurrent program counter
contents.

Table 3. Additional RAM Banks

Table 4. ST62T28C/E28C Data Memory Space

Device RAM

ST62T28C/E28C 2 x 64bytes

DATA RAM BANKS

000h
03Fh

DATA ROM WINDOWAREA

040h

07Fh
X REGISTER 080h
Y REGISTER 081h
V REGISTER 082h

W REGISTER 083h

DATA RAM

084h

0BFh
PORT A DATAREGISTER 0C0h
PORT B DATAREGISTER 0C1h
PORT C DATAREGISTE R 0C2h
PORT D DATAREGISTE R 0C3h

PORT A DIRECTION REGISTER 0C4h

PORT B DIRECTION REGISTER 0C5h
PORT C DIRECTION REGISTE R 0C6h
PORT D DIRECTION REGISTE R 0C7h

INTERRUPT OPTION REGISTER 0C8h*

DATA ROM WINDOW REGISTER 0C9h*

ROM BANK SELECT REGISTER 0CAh*

RAM BANK SELECT REGISTER 0CBh*

PORT A OPTION REGISTER 0CCh
PORT B OPTION REGISTER 0CDh
PORT C OPTION REGISTER 0CEh
PORT D OPTION REGISTER 0CFh

A/D DATA REGISTER 0D0h

A/D CONTROL REGISTER 0D1h

TIMER 1 PRESCALER REGISTER 0D2h

TIMER 1 COUNTERREGISTER 0D3h

TIMER 1 STATUS/CONTROL REGISTER 0D4h

RESERVED 0D5h

UARTDATA SHIFT REGISTER 0D6h

UARTSTATUS CONTROL REGISTER 0D7h

WATCHDOGREGISTER 0D8h

RESERVED 0D9h

I/O INTERRUPT POLARITY REGISTER 0DAh

SPI INTERRUPT DISABLE REGISTER 0DCh*

SPI DATASHIFT REGISTER 0DDh

RESERVED

0DEh
0E4h

ARTIMER MODE/CONTROL REGISTER 0E5h
ARTIMER STATUS/CONTROLREGISTER ARSC0 0E6h
ARTIMER STATUS/CONTROLREGISTER ARSC1 0E7h

RESERVED 0E8h

ARTIMER RELOAD/CAPTURE REGISTER 0E9h

ARTIMER COMPARE REGISTER 0EAh

. ARTIMER LOAD REGISTER 0EBh

RESERVED 0ECh

ACCUMULATOR OFFh

* WRITE ONLYREGISTER

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ST62T28C/E28C

MEMORY MAP(Cont’d)

1.3.5 Data Window Register (DWR)

TheData read-only memorywindowislocatedfrom
address 0040h toaddress 007Fh in Data space. It
allows directreading of 64consecutive bytes locat­ed anywhere in program memory, between ad­dress 0000h and 1FFFh (top memory address de­pends on the specific device). All the program
memory can therefore be used to store either in­structions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro­gram memorybywriting theappropriatecode inthe
Data Window Register (DWR).

The DWR can beaddressed like any RAMlocation
in theData Space,it is however a write-only regis­ter andtherefore cannotbe accessed using single­bit operations. This register is used to position the
64-byte read-onlydata window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the registeraddress given in the instruction
(as least significant bits) and the content of the
DWR register (asmost significant bits), as illustrat­ed in Figure 5 below. For instance, when address­ing location 0040h of the Data Space, with 00h
loaded in the DWR register, the physical location
addressed in program memory is 00h. The DWR
register is not cleared on reset, therefore it must
be written to prior to the first access to the Data
read-only memory window area.

Data Window Register (DWR)

Address: 0C9h — Write Only

Bits 7 = Not used.
Bit 6-0 = DWR6-DWR0:

Data read-only memory

Window Register Bits.

These are the Data read­only memory Window bits that correspond to the
upper bits of the dataread-only memory space.

Caution:

This register is undefined on reset. Nei­ther read nor single bit instructionsmay beused to
address this register.

Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe­cuting an interrupt service routine, as the service
routine cannot saveand then restore the register’s
previous contents. If it is impossible to avoid writ­ing to the DWRduring the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also writeto the image register. The
image register must be written first so that, if anin­terrupt occurs between the two instructions, the
DWR is not affected.

Figure 5. Data read-only memory Window Memory Addressing

70

- DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

DATA ROM

WINDOW REGISTER

CONTENTS

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

PROGRAM SPACE ADDRESS

765432 0

543210

543210

READ

1

67891011

01

VR01573A

12

1

0

DATA SPACE ADDRESS

59h

0000

01001

11

Example:

(DWR)

DWR=28h

11

00000000

1

ROM

ADDRESS:A19h

11

13

0

1

10

11/84

ST62T28C/E28C

MEMORY MAP(Cont’d)

1.3.6 Data RAM Bank Register (DRBR)

Address: CBh — Write only

Bit 7-5= These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM

Page 2.
Bit 3 - DRBR3. This bit, when set, selects RAM

Page 1.
Bit 2.0 These bits are not used.
The selection of the bank is madeby programming

the Data RAM Bank Switch register (DRBR regis­ter) located at address CBh of the Data Space ac­cording to Table 1.No more than onebank should
be set at a time.

The DRBR register can be addressed like a RAM
Data Space location at the address CBh; never­theless itis awrite only register that cannot be ac­cessed with single-bit operations. This register is
used to select the desired 64-byte RAM bank of
the Data Space. The number of banks has to be
loaded in the DRBR register and the instruction
has to point to the selected location as if it was in
bank 0 (from 00h address to 3Fh address).

This registeris not cleared during the MCU initiali­zation, therefore it must be written before the first
access to the Data Space bank region. Refer to

the Data Space description for additional informa­tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.

Notes:
Care is requiredwhen handling the DRBR register

as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in­terrupt service routine, as the service routine can­not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Other­wise two or more pages are enabled in parallel,
producing errors.

Table 5. Data RAM Bank Register Set-up

70

- - - DRBR4 DRBR3 - - -

DRBR ST62T28C/E28C

00h None
01h Reserved
02h Reserved
08h RAM Page 1
10h RAM Page 2

other Reserved

11

12/84

ST62T28C/E28C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configurationcapabili­ty to the MCUs. Option byte’s content is automati­cally read, and the selected options enabled,when
the chipreset is activated.

It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING modeof the pro­grammer.

The option bytes are located in a non-user map.
No address has to bespecified.

EPROM Code Option Byte (LSB)

EPROM Code Option Byte (MSB)

D15-D13. Reserved. Must be cleared.
ADC SYNCHRO. When set, an A/D conversion is

started upon WAIT instruction execution, in order
to reduce supply noise.When this bit is low, an A/
D conversion is started as soon as the STA bit of
the A/D Converter Control Registeris set.

D11.

UART Frame.

When set, UARTtransmission
and reception are based on a 11-bit frame. When
cleared, a 10-bit frame isused.

D10. Reserved

.

EXTCNTL.

External STOP MODE control.

. When

EXTCNTL is high, STOP mode is available with

watchdog active by setting NMI pin to one. When
EXTCNTL is low, STOP mode is not available with
the watchdog active.

LVD.

LVDRESET enable.

When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESETare active.

PROTECT.

Readout Protection.

This bitallows the
protection of the software contents against piracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user program can be read.

OSCIL.

Oscillator selection

. When this bit is low,
the oscillator must be controlled by a quartz crys­tal, a ceramic resonator or an external frequency.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.

D5.

Port Pull.

This bit must be set high to disable
pull-up at reset on the I/O port. When this bit is
low,I/O ports are in input with pull-up.

D4. Reserved. Must be clearedto zero.
NMI PULL.

NMI Pull-Up

. This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided.

TIM PULL.

TIM Pull-Up

. This bit must be set high
to configure the TIMER pin with a pull-up resistor.
When it is low, no pull-up is provided.

WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The software activation is selected when WDACT
is low.

OSGEN.

Oscillator Safe Guard

. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.

The Option byte is written during programming ei­ther by using the PC menu (PC driven Mode) or
automatically (stand-alone mode).

70

PRO­TECT

OSCIL

PORT

PULL

-

NMI

PULL

TIM

PULL

WDACT

OS-

GEN

15 8

---

ADC

SYNCHRO

UART

FRAME

-

EXTC-

NTL

LVD

12

13/84

ST62T28C/E28C

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPUCoreof ST6 devicesis independentofthe
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe­ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while thecore is linkedto thededicated on-chip pe­ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.

2.2 CPU REGISTERS

TheST6FamilyCPUcorefeaturessixregisters and
three pairs of flags available to the programmer.
These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal­culations, logical operations, and data manipula­tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.

Indirect Registers (X, Y). These two indirect reg­isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad­dressed in the data space as RAM locations at ad­dresses 80h (X) and 81h (Y). They canalso be ac­cessed with the direct, shortdirect, orbit direct ad­dressing modes. Accordingly, the ST6 instruction
set can usethe indirect registers as any other reg­ister of the data space.

Short Direct Registers (V, W). These two regis­ters are used to save a byte in short direct ad­dressing mode. They can be addressed in Data
space as RAM locationsat addresses 82h (V) and
83h (W). They can also be accessed using the di­rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis­ters as any other register of the data space.

Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper­and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.

Figure 6. ST6 Core Block Diagram

PROGRAM

RESET

OPCODE

FLAG

VALUES

2

CONTROLLER

FLAGS

ALU

A-DATA

B-DATA

ADDRESS/READ LINE

DATA SPACE

INTERRUPTS

DATA

RAM/EEPROM

DATA

ROM/EPROM

RESULTS TO DATA SPACE (WRITE LINE)

ROM/EPROM

DEDICATIONS

ACCUMULATOR

CONTROL

SIGNALS

OSCin

OSCout

ADDRESS

DECODER

256

12

Program Counter

and

6 LAYER STACK

0,01 TO 8MHz

VR01811

13

14/84

ST62T28C/E28C

CPU REGISTERS (Cont’d)

However, if theprogram space contains morethan
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.

The PC value is incremented after reading the ad­dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC.The program counter can
be changed in the following ways:

- JP (Jump) instructionPC=Jump address

- CALL instructionPC= Call address

- Relative Branch Instruction.PC= PC +/- offset

- Interrupt PC=Interrupt vector

- Reset PC= Reset vector

- RET & RETIinstructionsPC= Pop (stack)

- Normal instructionPC= PC + 1

Flags (C, Z). TheST6 CPU includes three pairs of
flags (Carryand Zero), eachpair beingassociated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation,another pair is useddur­ing Interrupt mode (CI, ZI), anda third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN­MI).

The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI in­struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou­tine). The flags are not cleared during context
switching andthus retain their status.

The Carry flag is set when a carry or a borrow oc­curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction;it also partici­pates inthe rotate left instruction.

The Zero flag isset ifthe result of the lastarithme­tic or logical operation was equal to zero; other­wise itis cleared.

Switching between the three sets of flags is per­formed automatically when an NMI, an interruptor
a RETI instructions occurs. As the NMI mode is

automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.

Stack. The ST6 CPU includes a true LIFO hard­ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When asubroutine call (or inter­rupt request)occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumula­tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou­tine. The stack will remain in its “deepest” position
if morethan 6 nested calls orinterrupts are execut­ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET orRETI is executed.
In this case the nextinstruction will be executed.

Figure 7. ST6 CPU Programming Mode

l

SHORT

DIRECT

ADDRESSING

MODE

VREGISTER

W REGISTER

PROGRAMCOUNTER

SIX LEVELS

STACKREGISTER

CZNORMAL FLAGS

INTERRUPTFLAGS

NMI FLAGS

INDEX

REGISTER

VA000 4 23

b7

b7

b7

b7

b7

b0

b0

b0

b0

b0

b0b11

ACCUM ULATOR

Y REG. POINTER

X REG. POINTER

CZ

CZ

14

15/84

ST62T28C/E28C

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillatorwhich can be
driven byan external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita­ble ceramic resonator, or with an external resistor
(R

NET

). In addition, a Low FrequencyAuxiliary Os­cillator (LFAO)can be switched in for security rea­sons, to reduce powerconsumption, orto offerthe
benefits of a back-up clock system.

The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automati­cally limits the internal clock frequency (f

INT

)asa
function of VDD, inorder toguarantee correct oper­ation. These functions are illustrated in Figure 2,
Figure 3, Figure 4 and Figure 5.

Figure 1 illustrates various possible oscillator con­figurations using anexternal crystal or ceramicres­onator, an external clock input, anexternal resistor
(R

NET

), or the lowest cost solution using only the
LFAO. CL1anCL2shouldhave acapacitance in the
range 12 tST6_CLK1o 22 pF for an oscillator fre­quency in the 4-8 MHz range.

The internal MCU clock frequency (f

INT

) is divided
by 12to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 4.

With an 8MHz oscillator frequency, the fastest ma­chine cycle is therefore 1.625µs.

A machine cycleis the smallest unit of time needed
to executeanyoperation(for instance,toincrement
the Program Counter). An instruction may require
two, four, or five machine cycles forexecution.

3.1.1 Main Oscillator

The oscillatorconfigurationmay bespecified byse­lectingtheappropriate option.When theCRYSTAL/
RESONATORoptionisselected,itmustbeusedwith
a quartz crystal,a ceramic resonator oran external
signalprovidedontheOSCinpin.WhentheRCNET­WORK option isselected, thesystem clock is gen­erated by an external resistor.

The main oscillator can be turned off (when the
OSG ENABLED option isselected) by setting the
OSCOFF bit of the ADC Control Register. The
Low Frequency Auxiliary Oscillator isautomatical­ly started.

Figure 8. Oscillator Configurations

INTEGRATED CLOCK

CRYSTAL/RESONATOR option

OSG ENABLED option

OSC

in

OSC

out

C

L1n

C

L2

ST6xxx

CRYSTAL/RESONATOR CLOCK

CRYSTAL/RESONATOR option

OSC

in

OSC

out

ST6xxx

EXTERNAL CLOCK

CRYSTAL/RESONATOR option

NC

OSC

in

OSC

out

ST6xxx

NC

OSC

in

OSC

out

R

NET

ST6xxx

RC NETWORK

RC NETWORK option

NC

15

16/84

ST62T28C/E28C

CLOCK SYSTEM (Cont’d)

Turning on the main oscillator is achieved by re­setting the OSCOFF bit of the A/DConverter Con­trol Register or by resetting the MCU. Restarting
the main oscillator implies a delay comprising the
oscillator start up delay period plus the duration of
the softwareinstruction at f

LFAO

clock frequency.

3.1.2 Low Frequency Auxiliary Oscillator

(LFAO)

The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without anyexternal components.Lastly, itacts as
a safetyoscillator in caseof main oscillator failure.

This oscillator is available when the OSG ENA­BLED option is selected. In this case, it automati­cally startsone of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillatordefective, no clock circuitry provid­ed, main oscillator switched off...).

User code,normal interrupts, WAIT and STOP in­structions, are processed as normal, at the re­duced f

LFAO

frequency.The A/D converter accura­cy is decreased, since the internal frequency is be­low 1MHz.

At power on, the Low Frequency Auxiliary Oscilla­tor starts faster than the Main Oscillator. It there­fore feeds the on-chip counter generating the POR
delay untilthe Main Oscillator runs.

The Low Frequency Auxiliary Oscillator is auto­matically switched off as soon as the main oscilla­tor starts.

ADCR

Address: 0D1h — Read/Write

Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:

ADC ControlRegister

. These bits are not used.

Bit 2 = OSCOFF. When low, this bit enables main
oscillator torun. The mainoscillator isswitched off
when OSCOFF is high.

3.1.3 Oscillator Safe Guard

The Oscillator Safe Guard (OSG) affordsdrastical­ly increasedoperational integrity in ST62xx devic­es. The OSG circuit provides three basic func-

tions: it filtersspikes from theoscillator lines which
would result inover frequency to the ST62 CPU; it
gives access to the Low Frequency Auxiliary Os­cillator (LFAO), used to ensure minimum process­ing in case of main oscillator failure, to offer re­duced power consumptionor to provide afixed fre­quency low cost oscillator; finally, it automatically
limits the internal clock frequency as a function of
supply voltage, in order to ensure correct opera­tion even if the power supply should drop.

The OSG is enabled or disabled by choosing the
relevant OSG option. It may be viewed as a filter
whose cross-over frequency is device dependent.

Spikes on the oscillatorlines result in an effectively
increased internal clock frequency.In the absence
of an OSG circuit, this may lead to an over fre­quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure

2). In all cases, when the OSG isactive, the maxi­mum internal clock frequency, f

INT

, is limited to

f

OSG

, which is supply voltage dependent. This re-

lationship is illustrated in Figure 5.
When the OSG is enabled, the Low Frequency

Auxiliary Oscillator maybe accessed. This oscilla­tor starts operating after the first missing edge of
the main oscillator (see Figure 3).

Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock fre­quency of the device is kept within the range the
particular device can stand (depending on VDD),
and below f

OSG

: the maximum authorised frequen-

cy with OSG enabled.
Note. The OSGshould be used wherever possible

as it provides maximumsafety. Care must be tak­en, however, as it can increase power consump­tion and reduce the maximum operating frequency
to f

OSG

.

Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and amaximum value and is not accu­rate.

For precise timing measurements, it is not recom­mended to use the OSG and it should not be ena­bled in applications that use the SPI or the UART.

It should also be noted that power consumption in
Stop mode is higher when the OSG is enabled
(around 50µA at nominal conditions and room
temperature).

70

ADCR7ADCR6ADCR5ADCR4ADCR3OSC

OFF

ADCR1ADCR

0

16

17/84

ST62T28C/E28C

CLOCK SYSTEM (Cont’d)
Figure 9. OSG Filtering Principle

Figure 10. OSG Emergency Oscillator Principle

(1)

VR001932

(3)

(2)

(4)

(1)
(2)

(3)
(4)

Maximum Frequency for the device to work correctly
Actual Quartz Crystal Frequency at OSCin pin
Noise from OSCin

Resulting Internal Frequency

Main

VR001933

Internal

Emergency

Oscillator

Frequency

Oscillator

17

18/84

ST62T28C/E28C

CLOCK SYSTEM (Cont’d)
Figure 11. Clock Circuit Block Diagram

Figure 12. Maximum Operating Frequency (f

MAX

) versus Supply Voltage (VDD)

Notes:

1. In this area, operation is guaranteed at the
quartz crystal frequency.

2. When the OSG is disabled, operation in this
area isguaranteed at the crystal frequency. When
the OSGis enabled, operation in this area isguar­anteed at a frequency of at least f

OSG Min.

3. When the OSG is disabled, operation in this

area is guaranteed at the quartz crystalfrequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a f

OSG.

4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at f

OSG.

MAIN

OSCILLATOR

OSG

LFAO

M

U
X

Core

:13

:12

:1

TIMER 1

Watchdog

POR

f

INT

Main Oscillator off

1

2.5 3.6 4 4.5 5 5.5 6

8

7

6

5

4

3

2

Maximum FREQUENCY (MHz)

SUPPLY VOLTAGE (V

DD

)

FUNCTIONALITY IS NOT

3

4

3

2

1

f

OSG

f

OSG

Min (at 85°C)

GUARANTEED

IN THIS AREA

VR01807J

f

OSG

Min (at 125°C)

18

19/84

ST62T28C/E28C

3.2 RESETS

The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-onReset;
– by the digital Watchdog peripheral timing out.
– by LowVoltage Detection (LVD)

3.2.1 RESET Input

The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used toreset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET pin are acceptable, provided VDDhas
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is keptin the Reset state as long as the
RESET pin is held low.

If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN modeonly), the Inputs and Outputs are con­figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se­quence is executed following expiry of the internal
delay period.

If RESET pinactivation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit consists in waking
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the Reset state: all I/O ports are configured as
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon aninternal delayis initiated, inorder to
allow the oscillator to fully stabilize before execut­ing the first instruction. The initialization sequence

is executed immediately following the internal de­lay.

To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi­cient level for the chosen frequency (see recom­mended operation) before the reset signal is re­leased. In addition, supply rising must start from
0V.

As a consequence, the POR does not allow to su­pervise static, slowly rising, or falling, or noisy
(presenting oscillation) VDD supplies.

An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performances.

Figure 13. Reset and Interrupt Processing

INT LATCH CLEARED

NMI MASK SET

RESET

( IF PRESENT )

SELECT

NMI MODE FLAGS

IS RESET STILL

PRESENT?

YES

PUT FFEH

ON ADDRESS BUS

FROM RESET LOCATIONS

FFE/FFF

NO

FETCH INSTRUCTION

LOAD PC

VA000427

19

20/84

ST62T28C/E28C

RESETS (Cont’d)

3.2.3 Watchdog Reset

The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth­er things, resets the watchdog counter.

The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.

3.2.4 LVD Reset

The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
in power supply drop with different reference val-

ues, allowing hysteresiseffect. Referencevalue in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start’s running and
sinking current on the supply.

As long as the supply voltage is below the refer­ence value, there is a internal and static RESET
command. The MCU can start only when the sup­ply voltage rises over the reference value. There­fore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figure 14, that represents a power­up, power-down sequence.

Note: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage De­tector, Watchdog, Power on Reset), the RESET
pin is tied to low logiclevel.

Figure 14. LVD Reset on Power-on and Power-down (Brown-out)

3.2.5 Application Notes

No external resistor is required between VDDand
the Reset pin, thanks to the built-in pull-up device.

Direct external connection of the pin RESET to
VDDmust be avoided in order to ensure safe be­haviour of the internal reset sources (AND.Wired
structure).

RESET

RESET

VR02106A

time

V

Up

V

dn

V

DD

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ST62T28C/E28C

RESETS (Cont’d)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat­ed in programROM starting at address 0FFEh). A
jump tothe beginning of the user program must be
coded at this address. Following a Reset, the In­terrupt flag is automatically set, so that the CPU is
in NonMaskable Interrupt mode; thisprevents the
initialisation routinefrom being interrupted. The in­itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. Ifno pending interrupt
is present at theend of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETIinstruction. If, how­ever, a pending interrupt is present, it will be serv­iced.

Figure 15. Reset and Interrupt Processing

Figure 16. Reset Block Diagram

RESET

RESET

VECTOR

JP

JP:2 BYTES/4 CYCLES

RETI

RETI: 1 BYTE/2 CYCLES

INITIALIZATION

ROUTINE

VA00181

V

DD

RESET

R

PU

R

ESD

1)

POWER

WATCHDOG RESET

CK

COUNTER

RESET

ST6
INTERNAL
RESET

f

OSC

RESET

ON RESET

LVD RESET

VR02107A

AND. Wired

1) Resistive ESD protection. Value not guaranteed.

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ST62T28C/E28C

RESETS (Cont’d)
Table 6. Register Reset Status

Register Address(es) Status Comment

Port Data Registers
Port Direction Register
Port Option Register
Interrupt Option Register
TIMER Status/Control

AR TIMER Mode/Control Register
AR TIMER Status/Control Register 0
AR TIMER Status/Control Register 1

0C0h to0C3h
0C4h to0C7h
0CCh to 0CFh
0C8h
0D4h

0E5h
0E6h
0E7h

00h

I/O are Input with or without pull-up
depending on PORT PULL option

Interrupt disabled
TIMER disabled

AR TIMER disabled

X, Y,V,W, Register
Accumulator
Data RAM
Data RAM Page Register
Data ROMWindow Register
A/D Result Register
ARTIMER Reload/Capture Register
ARTIMER Compare Registers
ARTIMER Load Registers

080H TO083H
0FFh
084h to 0BFh
0CBh
0C9h
0D0h
0E9h
0EAh
0EBh

Undefined

TIMER Counter Register
TIMER Prescaler Register
Watchdog Counter Register
A/D Control Register

0D3h
0D2h
0D8h
0D1h

FFh
7Fh

FEh

40h

Max count loaded

A/D in Stand-by

UART Status Control 0D7h UARTdisabled

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ST62T28C/E28C

3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recoveryfrom software upsets.

The Watchdog circuitgenerates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. Inthe eventof a software mishap (usual­ly caused by externally generated interference),
the userprogram will no longerbehave in its usual
fashion and the timer register will thus not be re­loaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In or­der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.

Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table7).

In the SOFTWARE option, the Watchdog is disa­bled until bit Cof the DWDR registerhas been set.

When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.

In the HARDWARE option, the Watchdog is per­manently enabled. Sincethe oscillator willrun con­tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc­tion, and the Watchdog continues to countdown.

However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.

Execution of the STOP instruction is then gov­erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in­struction is encountered when the NMIpin is high,
the Watchdog counter is frozen and the CPU en­ters STOP mode.

When the MCU exits STOPmode (i.e. when anin­terrupt is generated), the Watchdog resumes its
activity.

Table 7. Recommended Option Choices

Functions Required Recommended Options

Stop Mode & Watchdog “EXTERNAL STOP MODE” &“HARDWARE WATCHDOG”

Stop Mode “SOFTWARE WATCHDOG”

Watchdog “HARDWARE WATCHDOG”

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ST62T28C/E28C

DIGITAL WATCHDOG (Cont’d)

The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca­tion 0D8h) which is described in greater detail in
Section 3.3.1Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are allset to“1”, thus selecting the longest Watch­dog timer period. This time period can be set to the
user’s requirements by setting the appropriate val­ue for bits T0 to T5 in the DWDR register. The SR
bit mustbe set to “1”, since itis this bit which gen­erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re­set.

It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as­sociated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 toT5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physicalcounter bits when writing to this regis­ter. The relationship between the DWDR register
bits and the physical implementation ofthe Watch­dog timerdowncounter is illustrated in Figure 17.

Only the 6 most significant bitsmay be usedto de­fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of8MHz, this is equivalent to timer peri­ods ranging from 384µs to 24.576ms).

Figure 17. Watchdog Counter Control

WATCHDOG CONTROL REGISTER

D0

D1

D3

D4

D5

D6

D7

WATCHDOG COUNTER

C

SR

T5

T4

T3

T2

T1

D2

T0

OSC÷12

RESET

VR02068A

÷2

8

24

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ST62T28C/E28C

DIGITAL WATCHDOG (Cont’d)

3.3.1 Digital Watchdog Register (DWDR)

Address: 0D8h — Read/Write
Reset status:1111 1110b

Bit 0 = C:

Watchdog Control bit

If thehardware option is selected, this bit is forced
high andthe user cannot change it (the Watchdog
is always active). When the software option is se­lected, the Watchdog function is activated by set­ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).

When C is kept low the counter can be used as a
7-bit timer.

This bitis cleared to “0” on Reset.
Bit 1 = SR:

Software Reset bit

This bittriggers a Reset when cleared.
When C =“0” (Watchdog disabled) it is the MSB of

the 7-bit timer.
This bitis set to “1” on Reset.
Bits 2-7= T5-T0:

Downcounter bits

It should be noted that the register bits are re­versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.

These bits are set to “1” on Reset.

3.3.2 Application Notes

The Watchdog plays an important supporting role
in the highnoise immunityof ST62xx devices, and
should be used wherever possible. Watchdog re­lated options should be selected on the basis of a
trade-off between application security and STOP
mode availability.

When STOP mode is not required, hardware acti­vation without EXTERNAL STOP MODE CON­TROL should be preferred, as it provides maxi­mum security,especially during power-on.

When STOP mode is required, hardware activa­tion and EXTERNAL STOP MODE CONTROL
should be chosen. NMI should be high by default,
to allow STOP modeto beentered when the MCU
is idle.

The NMI pin can be connected to an I/O line (see
Figure 18)to allow its state to becontrolled by soft­ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O line is released and
the device placed in STOP mode for lowest power
consumption.

When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).

The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure theWatchdog has not been un­expectedly activated, the following instructions
should be executed within the first 27 instructions:

jrr 0, WD, #+3
ldi WD, 0FDH

70

T0 T1 T2 T3 T4 T5 SR C

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ST62T28C/E28C

DIGITAL WATCHDOG (Cont’d)

These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.

In all modes, a minimum of 28 instructions are ex­ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed followinga Reset (hardware activation).

It shouldbe notedthat when the GENbit is low (in­terrupts disabled), the NMI interrupt is active but
cannot cause a wake up fromSTOP/WAIT modes.

Figure 18. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature

Figure 19. Digital Watchdog Block Diagram

NMI

SWITCH

I/O

VR02002

RSFF

8

DATA BUS

VA00010

-2

-12

OSCILLATOR

RESET

WRITE

RESET

DB0

R

S

Q

DB1.7 SETLOAD

7

8

-2

SET

CLOCK

26