SGS Thomson Microelectronics ST25W02, ST25C02, ST24W02, ST24C02 Datasheet

ST24/25C02, ST24C02R

ST24/25W02

SERIAL 2K (256 x 8) EEPROM

NOT FOR NEW DESIGN

November 1997 1/16

This is information on a product still in production but not recommended for new design

AI00788D

E0-E2 SDA

ST24x02 ST25x02

ST24C02R

MODE/WC*

SCL

Figure 1. Logic Diag ra m

1 MILLION ERASE /WRI T E CYCLES with 40 YEARS DATA RETENTION

SINGL E SUPPLY VOLTAGE: – 3V to 5.5V for ST24x02 v ersions – 2.5V to 5.5V for ST25x02 versions – 1.8V to 5.5V for ST24C02R version only HARDWARE WRITE CONTROL VERSIONS:

ST24W02 and ST25W02 TWO WIRE SERIAL INTERFACE, FULLY I2C

BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 4

BYTES) PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQ UE NTIA L READ

MODES SELF TIME D PRO G RA MM ING CY C LE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATC H-UP

PERFORMA NCES

ST24C/W02 are replaced by the M24C02 ST25C/W02 are replaced by the M24C02-W ST24C02R is replaced by the M24C02-R

DESCRIP TION

This specification cov ers a range of 2K bits I

C bus EEPROM products, the ST24/25C02, the ST24C02R and ST24/25W02. In the text, products are referred t o as ST24/25x02, where " x" is: " C" for Standard version and "W" for hardware Write Control version.

E0-E2 Chip Enable Inputs SDA Serial Data Address Input/Output SCL Serial Clock

MODE

Multibyte/Page Write Mode

(C version) WC Write Control (W version) V

Supply Voltage V

Ground

T able 1. Signal Names

SO8 (M)

150mil Width

PSDIP8 (B)

0.25mm Frame

Note: WC signal is only available for ST24/25W02 products.

The ST24/25x02 are 2K bit electrically erasable programmable memories (EEPROM), organized as 256 x 8 bits. They are manufactured in SGSTHOMSON’s Hi-Endurance Advanced CMOS technology which guarantees an endurance of one million erase/write cycles with a data retention of 40 years. The memories operate with a power supply value as low as 1.8V for the ST24C02R only .

Both Plastic Dual- in-Line and Plastic Small Out line packages are available.

The memories are compatible with the I

C stand-

ard, two wire serial interface whic h uses a bi- direc-

tional data bus and serial clock. The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I

C bus definition. This is used t ogether with 3 chip enable inputs (E2, E1, E0) so that up to 8 x 2K devices may be attached to the I

C bus and selected individually.

The memories behave as a s lave devic e in the I

C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master . The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit.

SDAV

SCL

MODE/WCE1

E0 V

AI00789D

ST24x02 ST25x02

ST24C02R

1 2 3 4

8 7 6 5

Figure 2A. DIP Pin Connect io ns

AI00790E

2 3 4

8 7 6 5

SDAV

SCL

MODE/WCE1

E0 V

ST24x02 ST25x02

ST24C02R

Figure 2B. SO Pin Connecti ons

DESCRIP TION (co nt’d)

Symbol Parameter Value Unit

Ambient Operating Temperature –40 to 125 °C

STG

Storage Temperature –65 to 150 °C

LEAD

Lead Temperature, Soldering (SO8 package)

(PSDIP8 package)

40 sec 10 sec

215 260

°C

Input or Output Voltages –0.6 to 6.5 V

Supply Voltage –0.3 to 6.5 V

ESD

Electrostatic Discharge Voltage (Human Body model)

(2)

4000 V

Electrostatic Discharge Voltage (Machine model)

(3)

500 V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicat ed in the Operati ng sections of this specific ati on is not implied. Expos ure to Absolut e Maximum Rating conditions for extended periods may affect device rel i abi lity. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

T ab le 2. Absolut e Maximu m Ra t ings

(1)

2/16

ST24/25C02, ST24C02R, ST24/25W02

Mode RW bit MODE Bytes Initial Sequence

Current Address Read ’1’ X 1 START, Device Select, R

W = ’1’

Random Address Read

’0’

START, Device Select, R

W = ’0’, Address,

’1’ reSTART, Device Select, R

W = ’1’ Sequential Read ’1’ X 1 to 256 Similar to Current or Random Mode Byte Write ’0’ X 1 START, Device Select, R

W = ’0’

Multibyte Write

(2)

’0’ V

4 START, Device Select, RW = ’0’

Page Write ’0’ V

8 START, Device Select, RW = ’0’

Notes: 1. X = VIH or V

2. Multibyte Write not available in ST24/25W02 versions.

T ab le 4. Operating Modes

(1)

Device Code Chip Enable RW

Bit b7 b6 b5 b4 b3 b2 b1 b0 Device Select 1 0 1 0 E2 E1 E0 R

Note: The MSB b7 is sent first.

T ab le 3. Device Select Co de

When writing data to the mem ory it responds to th e 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master , it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition.

Power On Reset: V

lock out write protect. In

order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the V

voltage has reached the POR threshold v alue, th e internal reset is active, all operations are disabled and the device will not respond to any command. In the same way, when V

drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable V

must be applied before applying any logic signal.

SIGNAL DES CRIPTIONS Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A resistor can be connected from the SCL line to V

to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory . It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A res istor must be connected from the SDA bus line to V

to act as pull up (see Figure 3).

Chip Enable (E2 - E0). These chip enable inputs are used to set the 3 least significant bits (b3, b2, b1) of the 7 bit device select code. These inputs may be driven dynamically or t ied to V

or VSS to

establish the device select code. Mode (MO DE). T he MODE input is available on pin

7 (see also

WC feature) and may be driven dynami-

cally. It must be at V

or VIH for the Byte Write

mode, V

for Multibyte Write mode or VIL for Page Write mode. When unconnected, the MODE input is internally read as a V

(Multibyte Write mode).

Write Control (

WC). An hardware Write Control

feature (

WC) is offered only for ST24W02 and ST25W02 versions on pin 7. This feature is usefull to protect the contents of the memory from any erroneous erase/write cy cle. The W rite Control s ignal is used to enable (

WC = VIH) or disable (WC =

) the internal write protection. When uncon-

nected, the

WC input is internally read as VIL and

the memory area is not write protected.

3/16

ST24/25C02, ST24C02R, ST24/25W02

AI01100

BUS

SDA

MASTER

SCL

BUS

100 200 300 400

BUS

(pF)

max (kΩ)

VCC = 5V

Figure 3. Maximum RL Value versus Bus Capacitance (C

BUS

) for an I2C Bus

The devices with this Write Control feature no longer support the Multibyte Write mode of operation, however all other write modes are fully supported.

Refer to the AN404 Application Note for more detailed information about Write Contr ol feature.

DEVICE OPER ATION I

C Bus Background

The ST24/25x02 support the I

C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device t hat reads the data as a receiver . The device that c ontrols th e data transfer is known as the master and the other as the slave. The master will alway s initiate a dat a transfer and will provide the serial clock for synchronisation. The ST24/25x02 are always slave devices in all communications.

Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25x02 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given.

Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24/25x02 and the bus master. A STOP condition at the end of a Read command, after and only after a No Acknowledge, forces the standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successfull data transfer. The bus transmitter , either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse period the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data.

Data Input. During data input the ST24/25x02 sample the SDA bus signal on the rising edge of the clock SCL. Note that for correct device operation the SDA signal must be stable during the c lock low to high transition and the data must change ONLY when the SCL line is lo w.

Memory Addressi ng. To start com munic ation between the bus master and the slave ST24/25x02, the master must initiate a ST ART co ndition. Following this, the master sends onto the SDA bus line 8 bits (MSB first) corresponding to the device select code (7 bits) and a READ or WRITE bit.

SIGNAL DES CRIPTIONS (cont’d)

4/16

ST24/25C02, ST24C02R, ST24/25W02

Symbol Parameter Test Condition Min Max Unit

Input Capacitance (SDA) 8 pF

Input Capacitance (other pins) 6 pF

WCL

WC Input Impedance (ST24/25W02) VIN ≤ 0.3 V

520kΩ

WCH

WC Input Impedance (ST24/25W02) VIN ≥ 0.7 V

500 kΩ

Low-pass filter input time constant (SDA and SCL)

100 ns

Note: 1. Sampled only, n ot 100% tested.

T able 5. Input Parameters

(1)

(TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit

Input Leakage Current 0V ≤ VIN ≤ V

±2 µA

Output Leakage Current

0V ≤ V

OUT

≤ VCC

SDA in Hi-Z

±2 µA

Supply Current (ST24 series)

= 5V, fC = 100kHz

(Rise/Fall time < 10ns)

2mA

Supply Current (ST25 series) V

= 2.5V, fC = 100kHz 1 mA

CC1

Supply Current (Standby) (ST24 series)

= VSS or VCC,

= 5V

100 µA

= VSS or VCC,

= 5V, fC = 100kHz

300 µA

CC2

Supply Current (Standby) (ST25 series)

= VSS or VCC,

= 2.5V

5 µA

= VSS or VCC,

= 2.5V, fC = 100kHz

50 µA

CC3

Supply Current (Standby) (ST24C02R)

= VSS or VCC,

= 3.6V

20 µA

= VSS or VCC,

= 3.6V, fC = 100kHz

60 µA

CC4

Supply Current (Standby) (ST24C02R)

= VSS or VCC,

= 1.8V

10 µA

= VSS or VCC,

= 1.8V, fC = 100kHz

20 µA

Input Low Voltage (SCL, SDA) –0.3 0.3 V

Input High Voltage (SCL, SDA) 0.7 V

VCC + 1 V

Input Low Voltage (E0-E2, MODE,

WC)

–0.3 0.5 V

Input High Voltage (E0-E2, MODE,

WC)

– 0.5 VCC + 1 V

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V Output Low Voltage (ST25 series) I

= 2.1mA, VCC = 2.5V 0.4 V

Output Low Voltage (ST24C02R)

= 1mA, VCC = 1.8V 0.3 V

T ab le 6. DC Characteristics (T

= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)

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ST24/25C02, ST24C02R, ST24/25W02

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