SGS Thomson Microelectronics ST25E16, ST24E16 Datasheet

16 Kbit Serial I2C EEPROM with Ex tende d Addressin g

COMPATIBLE with I2C EXTENDED
ADDRESSING

TWO WIRE SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL

1 MILLION ERASE/WRI T E CYCLES, O VER
the FULL SUPPLY VOLTAGE RANG E

40 YEARS DA TA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST24E16 version
– 2.5V to 5.5V for ST25E16 version
WRITE CONTROL FEATURE
BYTE and PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ

MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCE D ESD/LATCH UP

PERFORMANCES

8

1

PSDIP8 (B)

0.25mm Frame

Figure 1. Logic Diagram

ST24E16

ST25E16

8

1

SO8 (M)

150mil Width

DESCRIPTION

V

CC

The ST24/25E16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. It is manufactured in
STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur­ance of one million erase/write cycles over the full
supply voltage range, and a data retention of over

E0-E2 SDA

SCL

3

ST24E16
ST25E16

40 years. The ST25E16 operates with a power
supply value as low as 2.5V.

WC

T ab le 1. Signal Names

V

E0 - E2 Chip Enable Inputs
SDA Serial Data Address Input/Output
SCL Serial Clock
WC Write Control
V

CC

V

SS

February 1999 1/16

Supply Voltage
Ground

SS

AI01102B

ST24E16, ST25E16

Figure 2A. DIP Pin Connections

ST24E16
ST25E16

1

E0 V

2
3

E2

4

SS

T ab le 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

Ambient Operating Temperature –40 to 125
Storage Temperature –65 to 150

8
7
6
5

AI01103B

CC

WCE1
SCL
SDAV

(1)

Figure 2B. SO Pin Connections

ST24E16
ST25E16

1

E0 V

2
3

E2

SS

4

8
7
6
5

AI01104C

CC

WCE1
SCL
SDAV

C

°

C

°

T

LEAD

V

IO

V

CC

V

ESD

Notes:

1. Except for the rating "Operating T emperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.

2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

3. 200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d) the I

Lead T e mperature, Soldering (SO8)

Input or Output Voltages –0.6 to 6.5 V
Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

(PSDIP8)

(3)

2

C bus definition. The ST24/25E16 behave as

slave devices in the I
Both Plastic Dual-in-Line and Plastic Small Out line
packages are available.

2

Each memory is compatible with the I

C extended
addressing standard, two wire serial interface
which uses a bi-directional data bus and serial
clock. The ST24/25E16 carry a built-in 4 bit, unique
device identification code (1010) corresponding to

operations synchronized by the serial clock. Read
and write operations are initiated by a START
condition generated by the bus master. The ST ART
condition is followed by a stream of 4 bits (identifi­cation code 1010), 3 bit Chip Enable input to form
a 7 bit Device Select, plus one r ead/write bit and
terminated by an acknowledge bit.

40 sec
10 sec

(2)

2

C protocol with all memory

215
260

4000 V

500 V

C

°

2/16

ST24E16, ST25E16

T ab le 3. Device Select Code

Device Code Chip Enable RW

Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 E2 E1 E0 R

Note:

The MSB b7 is sent first.

T ab le 4. Operating Modes

Mode RW bit Bytes Initial Sequence

Current Address Read ’1’ 1 START, Device Select, R

Random Address Read

Sequential Read ’1’ 1 to 2048 As CURRENT or RANDOM Mode
Byte Write ’0’ 1 START, Device Select, R
Page Write ’0’ 16 START, Device Select, R

’0’
’1’ reSTART, Device Select, R

1

When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way.

Data transfers are terminated with a STOP condi­tion. In this way, up to 8 ST24/25E16 may be
connected to the same I

2

C bus and selected indi­vidually, allowing a total addressing field of 128
Kbit.

Power On Reset: V

lock out write protect . In

CC

order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V

CC

voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any c ommand.
In the same way, when V

drops down from the

CC

operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V

CC

must be applied before applying any logic signal.

START, Device Select, R

Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V

to act as pull up (see Figure 3).

CC

Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits of the 7
bit device select code. They may be driven dynami­cally or tied to V

CC

select code. Note that the V
inputs are CMOS, not TTL compatible.

Write Control (

WC). The Write Control feature

WC is useful to protect the contents of the memory
from any erroneous erase/write cycle. The Write
Control signal is used to enable (
disable (

WC at VIL) the internal write protection.
The devices with this Write Control feature no
longer supports the multibyte mode of oper ation.
When unconnected, the

(see Table 5).

as V

IL

When

WC = ’1’, Device Select and Address bytes

W = ’1’
W = ’0’, Address,

W = ’1’

W = ’0’
W = ’0’

or VSS to establish the device

and VIH levels for the

IL

WC at VIH) or

WC input is internally read

are acknowledged; Data bytes are not acnowl-

SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V

CC

edged.
Refer to the AN404 Application Note for more de-

tailed information about Write Control feature.

to act as a pull up (see Figure 3)

W

3/16

ST24E16, ST25E16

Figure 3. Maximum RL Value versus Bus Capacitance (C

20

16

12

max (kΩ)

L

R

8

4

0

VCC = 5V

25 50 75 100

C

(pF)

BUS

) for an I2C Bus, fC = 400kHz

BUS

V

CC

R

L

SDA

MASTER

SCL

C

BUS

R

L

C

BUS

AI01115

DEVICE O PERATION

2

I

C Bus Background

The ST24/25E16 support the extended addr essing

2

C protocol. This protocol defines any device that

I
sends data onto the bus as a transmitter and any
device that reads the data as a rec eiver.The device
that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The ST24/25E16
are always slave devices in all communications.

Start Condition . START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A ST AR T condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25E16 con­tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.

Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi­nates communication between the ST24/25E16
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A

STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a suc cessful data transfer. The
bus transmitter, eit her master or s lave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse the receiver pulls the SDA bus low
to acknowledge the receipt of the 8 bits of data.

Data Input. During data input the ST24/25E16
sample the SDA bus signal on the rising edge of
the clock SCL. For correct device operation the
SDA s ignal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL line is low.

Device Selection. To start communication be­tween the bus master and the slave ST24/25E16,
the master must initiate a START condition. The 8
bits sent after a STA RT c ondition are made up of a
device select of 4 bits that identifies the device type,
3 Chip Enable bits and one bit for a READ (R

1) or WRITE (R

W = 0) operation. There are two

W =

modes both for read and write. These are summa­rised in T able 4 and described hereafter. A commu­nication between the master and the slave is ended
with a STOP condition.

4/16

ST24E16, ST25E16

Table 5. Input Parameters

(1)

(TA = 25 °C, f = 400 kHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IN

Z

WCL

Z

WCH

t

LP

Note:

1. Sampled only, not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance VIN ≤ 0.3 V
WC Input Impedance VIN ≥ 0.7 V
Low-pass filter input time constant

(SDA and SCL)

CC

CC

520k

500 k

100 ns

T ab le 6. DC Characteristics

(T

= 0 to 70 ° or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)

A

Symbol Parameter Test Condition Min Max Unit

I

LI

I

LO

I

CC

Input Leakage Current
(SCL, SDA, E0-E2)

Output Leakage Current

0V ≤ V

0V ≤ V

Supply Current (ST24 series)
Supply Current (ST25 series) 1 mA

(Rise/Fall time < 30ns)

≤ V

IN

≤ VCC

OUT

SDA in Hi-Z
f

= 400kHz

C

CC

2

±

2

±

2mA

Ω
Ω

A

µ

A

µ

I

CC1

I

CC2

V

V

V

V

V

OL

VIN = VSS or VCC,

= 5V

V

Supply Current (Standby)
(ST24 series)

V

CC

V

= VSS or VCC,

IN

= 5V, fC = 400kHz

CC

VIN = VSS or VCC,

= 2.5V

V

Supply Current (Standby)
(ST25 series)

V

IL

IH

IL

IH

Input Low Voltage (SCL, SDA) –0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage (E0-E2, WC) –0.3 0.5 V
Input High Voltage (E0-E2, WC) VCC – 0.5 VCC + 1 V

CC

V

= VSS or VCC,

IN

= 2.5V, fC = 400kHz

CC

CC

100

300

5

50

CC

µ

µ

µ

µ

VCC + 1 V

A

A

A

A

V

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
Output Low Voltage (ST25 series) I

= 2.1mA, VCC = 2.5V 0.4 V

OL

5/16