SGS Thomson Microelectronics M48T513Y-70PL1, M48T513Y, M48T513V Datasheet

1/23June 2000

M48T513Y
M48T513V

3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPERSRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY, andCRYSTAL

■ YEAR 2000 COMPLIANT

■ BCD CODED CENTURY, YEAR, MONTH,

DAY, DATE, HOURS, MINUTES, and
SECONDS

■ BATTERY LOW WARNING FLAG

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ TWO WRITE PROTECT VOLTAGES:

(V

PFD

= Power-fail Deselect Voltage)

– M48T513Y: 4.2V ≤ V

PFD

≤ 4.5V

– M48T513V: 2.7V ≤ V

PFD

≤ 3.0V

■ CONVENTIONAL SRAM OPERATION;

UNLIMITED WRITE CYCLES

■ SOFTWARE CONTROLLED CLOCK

CALIBRATION for HIGH ACCURACY
APPLICATIONS

■ 10 YEARS of DATA RETENTION and CLOCK

OPERATION in the ABSENCE of POWER

■ SELF CONTAINED BATTERY and CRYSTAL

in DIP PACKAGE

■ MICROPROCESSOR POWER-ON RESET

(Valid even during battery back-up mode)

■ PROGRAMMABLE ALARM OUTPUT ACTIVE

in BATTERY BACK-UP MODE

■ SURFACE MOUNT CHIP SET PACKAGING

INCLUDES a 44-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY and CRYSTAL

■ SNAPHAT



HOUSING (BATTERY/CRYSTAL)

IS REPLACEABLE

Figure 1. Logic Diagram

AI02308

19

A0-A18 DQ0-DQ7

V

CC

M48T513Y
M48T513V

G

V

SS

8

E

W RST

IRQ/FT

RSTIN

WDI

32

1

SOH44

Surface Mount Chip Set Solution (CS)

SNAPHAT (SH)

Battery

PMDIP32(PM)

Module

32

1

TSOP II 32

(10 x 20mm)

M48T513Y, M48T513V

2/23

Figure 2. DIP Connections

V

SS

V

CC

AI02307

M48T513Y
M48T513V

10

1
2

5
6
7
8
9

11
12
13

16
17
18

30
29

26
25
24
23
22
21
20
19

3
4

28
27

32
31

14
15

34
33

36
35

A1
A0

DQ0

A7

A4
A3
A2

A6
A5

A13

A10

A8
A9

DQ7

A15

A11
G

E

DQ5DQ1

DQ2

DQ3

DQ4

DQ6

A16

A18

A12

A14

W

A17

RSTIN

RST

IRQ/FT

WDI

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. Thisis a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature 0 to 70 °C

T

STG

Storage Temperature (VCCOff, Oscillator Off)

–40 to 85 °C

V

IO

Input or Output Voltages –0.3 to VCC+0.3 V

V

CC

Supply Voltage

M48T513Y –0.3 to 7.0 V
M48T513V –0.3 to 4.6 V

I

O

Output Current 20 mA

P

D

Power Dissipation 1 W

DESCRIPTION

The M48T513Y/VTIMEKEEPER RAM is a 512Kb
x 8 non-volatile static RAM and real time clock,
with programmable alarms and a watchdog timer.
The special DIP package provides a fully integrat­ed battery back-up memoryand real time clock so­lution. TheM48T513Y/V directly replaces industry
standard 512Kb x 8 SRAM. It also provides the
non-volatility of Flash without any requirement for
special write timing or limitations on the number of
writes that can be performed.

Table 1. Signal Names

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs / Outputs
E Chip Enable Input

G Output Enable Input

W Write Enable Input

WDI Watchdog input

RST Reset Output (open drain)

RSTIN Reset Input

IRQ/FT

Interrupt / Frequency Test
Output (open drain)

V

CC

Supply Voltage

V

SS

Ground

For surface mount environments ST provides a
Chip Set solution consisting of a 44 pin 330mil
SOIC TIMEKEEPER Supervisor (M48T201V/Y)
and a 32 pin TSOP Type II (10 x 20mm) LPSRAM
(M68Z512/W) packages.

The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con­nection to a separate SNAPHAT housing contain­ing the battery.

3/23

M48T513Y, M48T513V

Figure 3. Block Diagram

AI02584

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

V

PFD

V

CC

V

SS

32,768

Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

16 x

8

TIMEKEEPER

REGISTERS

524,272 x

8

SRAM ARRAY

A0-A18

DQ0-DQ7

E
W
G

POWER

RST
IRQ/FT

WDI
RSTIN

The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack­age after the completion of the surface mount pro­cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the hightemperatures required for device surface­mounting. The SNAPHAT housing is keyed to pre­vent reverse insertion.

The SNAPHAT battery package is shipped sepa­rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Txx-BR12SH1”.

Figure 3 illustratesthestaticmemoryarray andthe
quartz controlled clock oscillator. The clock loca­tions contain the century, year, month, date, day,
hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year), 30, and 31 day
months are made automatically. The nine clock
bytes (7FFFFh-7FFF9h and 7FFF1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT read/write memory cells
within the static RAM array.

The M48T513Y/V includes a clock control circuit
which updates the clock bytes with current infor­mation once per second. The information can be
accessed by the user in the same manner as any

other location in the static memory array. Byte
7FFF8his the clock control register.Thisbyte con­trols user access to the clock information and also
stores the clock calibration setting.

Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch­dogSteering bit(WDS).Bytes 7FFF6h-7FFF2h in­clude bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century informa­tion.Byte 7FFF0h contains additionalflaginforma­tion pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T513Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
VCCis out of tolerance, the circuit write protects
the TIMEKEEPER register data and external
SRAM, providing data security in the midst of un­predictable system operation. As VCCfalls, the
control circuitry automatically switches to the bat­tery, maintaining data and clock operation until
valid power is restored.

M48T513Y, M48T513V

4/23

Figure 4. Hardware Hookup for SMT Chip Set

(1)

Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z512/W atwww.st.com.

2. For 5V, M48T129Y (M48T201Y + M68Z512). For 3.3V, M48T129V (M48T201V + M68Z512W).

3. SNAPHAT Top ordered separately.

AI03633

32,768

Hz

CRYSTAL

LITHIUM

CELL

A0-A18

DQ0-DQ7

E

V

CC

W
G
WDI
RSTIN1
RSTIN2
V

SS

E
W
G

V

CC

V

SS

A0-A18

DQ0-DQ7

0.1µF

0.1µF

5V

ECON

GCON

RST

IRQ/FT

SQW

M48T201Y/V

(2)

M68Z512/W

(2)

V

OUT

SNAPHAT

(3)

BATTERY/CRYSTAL

READ MODE

The M48T513Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad­dress Inputs defines which one of the 524,272
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within t

AVQV

(Ad­dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latterof the Chip Enable Access Times (t

ELQV

)

or Output Enable Access Time (t

GLQV

).

The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat­ed before t

AVQV

, the data lines will be driven to an

indeterminate state until t

AVQV

. If the Address In­puts are changed while E and G remain active,
output data will remain valid for t

AXQX

(Output

Data Hold Time) but will go indeterminate until the
next Address Access.

WRITE MODE

The M48T513Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable.

The start of a write is referencedfrom the latter oc­curring falling edgeof W orE. A write is terminated
by the earlierrisingedge of W or E. The addresses
must be held valid throughout the cycle. E or W
must return high for a minimum of t

EHAX

fromChip

Enable or t

WHAX

from Write Enable prior to the ini­tiation of another read or write cycle. Data-in must
be valid t

DVWH

prior to the end of write and remain

valid for t

WHDX

afterward. G should be kept high
during write cycles to avoid bus contention; al­though, if the output bus has been activated by a
low on E and G a low on Wwill disable the outputs
t

WLQZ

after W falls.

5/23

M48T513Y, M48T513V

Table 3. Operating Modes

(1)

Note: 1. X = VIHor V

IL;VSO

= Battery Back-up Switchover Voltage.

2. See Table 7 for details.

Mode V

CC

E G W DQ0-DQ7 Power

Deselect

4.5V to 5.5V
or

3.0V to 3.6V

V

IH

X X High Z Standby

Write V

IL

XVILD

IN

Active

Read

V

IL

V

IL

V

IH

D

OUT

Active

Read

V

IL

V

IH

V

IH

High Z Active

Deselect

V

SO

to V

PFD

(min)

(2)

X X X High Z CMOS Standby

Deselect

≤ V

SO

(2)

X X X High Z Battery Back-up Mode

Table 4. AC Measurement Conditions

Note thatOutput Hi-Z is defined as the point wheredata is no longer
driven.

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

referred to as BiPORT TIMEKEEPER cells).
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD.

DATA RETENTION MODE

With valid VCCapplied, the M48T513Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati­cally deselect, write protecting itself when V

CC

falls between V

PFD

(max), V

PFD

(min) window. All
outputs become high impedance and all inputsare
treated as ”don’t care”.

Note: Apower failureduring a write cycle may cor­rupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below V

PFD

(min), the memory will be
in a write protected state, provided the VCCfall
time is not less than tF. The M48T513Y/V may re­spond to transient noise spikes on VCCthat cross
into the deselect window during the time the de­vice issampling VCC. Therefore, decouplingof the
power supply lines is recommended.

When VCCdrops below VSO, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T513Y/V for
an accumulated period of at least 10 years atroom
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Deselect continues for
t

REC

after VCCreaches V

PFD

(max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.

TIMEKEEPER REGISTERS

The M48T513Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations which contain external (user
accessible) andinternal copies ofthe data (usually

Figure 5. AC Testing Load Circuit

Note: Excluding open drain output pins.

AI01803C

CL= 100pF

CLincludes JIG capacitance

650Ω

DEVICE
UNDER

TEST

1.75V

M48T513Y, M48T513V

6/23

CLOCK OPERATIONS
Reading the Clock

Updates to the TIMEKEEPER registers should be
halted beforeclock data is read to prevent reading
data in transition. Because the BiPORT TIME­KEEPER cellsin the RAM array are only data reg­isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.

Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register (7FFF8h). As
long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count;thatis,the day,date, and time that were
current at the moment the halt command was is­sued. All ofthe TIMEKEEPER registers are updat­ed simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second af­ter the READ bit is reset to a’0’.

Setting the Clock

Bit D7 of the Control Register (7FFF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER reg­isters. The user can then load them with the cor­rect day, date, and time data in 24 hour BCD
format (see Table 11).

Resetting the WRITE bit to a ’0’then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to theactual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE bit isreset, thenextclockupdate willoccur
approximately one second later.

Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ’0’.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is located at Bit D7 within 7FFF9h. Setting it to
a ’1’ stops the oscillator. When reset to a ’0’, the
M48T513Y/V oscillator starts within one second.

Note: It is not necessary to set the WRITE bit
when setting orresetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).

SETTING ALARM CLOCK

Registers 7FFF6h-7FFF2h contain the alarm set­tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every month, day,
hour, minute, or second. It can also be pro­grammed to go off while the M48T513Y/V is in the
battery back-upto serveasa systemwake-upcall.

Bits RPT5-RPT1 putthe alarm in the repeat mode
of operation. Table 12 shows the possible config­urations.Codes not listedin the tabledefaultto the
once per second mode toquickly alert the user of
an incorrect alarm setting.

Note: User must transition address (or toggleChip
Enable) to see Flag Bit change.

When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag)is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi­tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm Date register and RPT1-4.
The IRQ/FT output is cleared by a read to the
Flags register as shown in Figure 12. A subse­quent read of the Flags register will reset the
Alarm Flag (D6; Register 7FFF0h).

The IRQ/FT pin can also be activated in the bat­tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable)and AFE areset. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. Theuser can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T513Y/V was in the deselect mode
during power-up. Figure 13 illustratesthe back-up
mode alarm timing.

WATCHDOG TIMER

The watchdog timer can be used to detect an out­of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
7FFF7h. BitsBMB4-BMB0 store abinarymultiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec­ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).

Note: Accuracy of timer is within ± the selected
resolution.

7/23

M48T513Y, M48T513V

Table 5. Capacitance

(1)

(TA=25°C, f = 1 MHz)

Note: 1. Effective capacitance measured with power supply at 5V (M48T513Y) or 3.3V (M48T513V). Sampled only, not 100% tested.

2. Outputs deselected.

Table 6A. DC Characteristics - M48T513Y

(TA= 0 to 70 °C; VCC= 4.5V to 5.5V)

Note: 1. Outputs deselected.

Table 6B. DC Characteristics - M48T513V

(TA= 0 to 70 °C; VCC= 3.0V to 3.6V)

Note: 1. Outputs deselected.

Symbol Parameter Test Condition Min Max Unit

C

IN

Input Capacitance

V

IN

=0V

20 pF

C

IO

(2)

Input / Output Capacitance

V

OUT

=0V

20 pF

Symbol Parameter Test Condition Min Max Unit

I

LI

(1)

Input Leakage Current 0V ≤ VIN≤ V

CC

±2 µA

I

LO

(1)

Output Leakage Current

0V ≤ V

OUT

≤ V

CC

±2 µA

I

CC

Supply Current Outputs open 115 mA

I

CC1

Supply Current (Standby) TTL

E=V

IH

8mA

I

CC2

Supply Current (Standby) CMOS

E=V

CC

– 0.2V

4mA

V

IL

Input Low Voltage –0.3 0.8 V

V

IH

Input High Voltage 2.2

V

CC

+ 0.3

V

V

OL

Output Low Voltage

I

OL

= 2.1mA

0.4 V

V

OH

Output High Voltage

I

OH

= –1mA

2.4 V

Symbol Parameter Test Condition Min Max Unit

I

LI

(1)

Input Leakage Current

0V ≤ V

IN

≤ V

CC

±2 µA

I

LO

(1)

Output Leakage Current

0V ≤ V

OUT

≤ V

CC

±2 µA

I

CC

Supply Current Outputs open 60 mA

I

CC1

Supply Current (Standby) TTL E = V

IH

4mA

I

CC2

Supply Current (Standby) CMOS

E=V

CC

– 0.2V

3mA

V

IL

Input Low Voltage –0.3 0.4 V

V

IH

Input High Voltage 2.2

V

CC

+ 0.3

V

V

OL

Output Low Voltage IOL= 2.1mA 0.4 V

V

OH

Output High Voltage

I

OH

= –1mA

2.2 V