SGS Thomson Microelectronics M48T512V, M48T512Y-70PM1, M48T512Y Datasheet

3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPER® SRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY, and CRYSTAL

■ BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES, and SECONDS

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES:

(V

= Power-fail Deselect Voltage)

PFD

– M48T512Y: 4.2V ≤ V
– M48T512V: 2.7V ≤ V

■ CONVENTIONAL SRAM OPERATION;

UNLIMITED WRITE CYCLES

■ SOFTWARE CONTROLLED CLOCK

CALIBRATION FOR HIGH ACCURACY
APPLICATIONS

■ 10 YEARS of DATA RETENTION and CLOCK

OPERATION in the ABSENCE OF POWER

■ PIN and FUNCTION COMPATIBLE with

INDUSTRY STANDARD 512K X 8 SRAMS

■ SELF-CONTAINED BATTERY and CRYSTA L

in DIP PACKAGE

PFD
PFD

≤ 4.5V
≤ 3.0V

32

1

PMDIP32 (PM)

Module

Figure 1. Logic Diagram

V

CC

M48T512Y
M48T512V

DESCRIPTION

The M48T512Y/V TIMEKEEPER RAM is a 512Kb
x 8 non-volatile static RAM and real time clock or­ganized as 524,288 words by 8 bits. The spe cial
DIP package provides a fully integrated battery
back-up memory and real time clock solution.

Table 1. Signal Names

A0-A18 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
W
V
V

CC

SS

Chip Enable Input
Output Enable Input
Write Enable Input
Supply Voltage
Ground

19

A0-A18 DQ0-DQ7

W

E

G

M48T512Y
M48T512V

V

SS

8

AI02262

1/14December 1999

M48T512Y, M48T512V

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

T

SLD

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoo ts bel ow –0.3V ar e not al l owed on any pin wh i l e i n the Batter y Back-up mod e.

Ambient Operating Temperature 0 to 70 °C
Storage Temperature (VCC Off, Oscillator Off)

(2)

Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages

Supply Voltage

Output Current 20 mA
Power Dissipation 1 W

rating only and functional opera tion of the dev i ce at these or any other conditions above thos e i ndi cated in th e operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.

Figure 2. DIP C on ne ctions

(1)

–40 to 85 °C

–0.3 to V
M48T512Y –0.3 to 7.0 V
M48T512V –0.3 to 4.6 V

CC

+0.3

V

The 32 pin 600 mil DIP Hybrid houses a controller
chip, SRAM, quartz crystal, and a long life lithium
button cell in a single package. Figure 3 illustrates
the static memory array and the quartz con trolled
clock oscillator. The clock locations contain the
year, month, date, day, hour, minute, and second

A18 V

1

A16

2
3

A14

4

A12

5

A7

6

A6

7

A5

8

A4
A3
A2
A1
A0

DQ0

M48T512Y
M48T512V

9
10
11
12
13
14
15

DQ2

16

SS

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

AI02263

CC

A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

in 24 hour BCD format. Corrections for 28, 29
(leap year - compliant until the year 2100), 30, and
31 day months are made automatically. Byte
7FFF8h is the clock control register. This byte con­trols user access to the clock information and also
stores the clock calibration setting. The seven
clock bytes (7FFFFh-7FFF9h) are not the actual
clock counters, they are memory locations consist-

ing of BiPORT™ read/write memory cells within
the static RAM array. The M48T512Y/V includes a
clock control circuit which updates the clock bytes
with current information once per second. Th e in­formation can be accessed by the user in the
same manner as any other location in the s tatic
memory array. The M48T512Y/V also has its own
Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When V

is out of toler-

CC

ance, the circuit write protects the TIMEKEEPER
register data and external SRAM, providi ng data
security in the midst of unpredictable system oper­ation. As V

falls, the control circuitry automati-

CC

cally switches to the battery, maintaining data and
clock operation until valid power is restored.

The M48T512Y/V directly replaces industry stan­dard 512Kb x 8 SRAMs. It also p rovides the non­volatility of Flash without any requirement for spe­cial write timing or limitations on the number of
writes that can be performed.

2/14

READ MODE

The M48T512Y/V is in the Read Mode whenever

(Write Enable) is high and E (Chip Enable) is

W
low. The unique address specified by the 19 A d­dress Inputs defines which one of the 524,288
bytes of data is to be access ed. Valid dat a will be
available at the D ata I/O pins within Address Ac-

M48T512Y, M48T512V

Table 3. Operating Modes

Mode

Deselect
Write
Read
Read

Deselect
Deselect

Note: 1. X = VIH or VIL.

2. See T able 7 for details.

cess T ime (t

AVQV

4.5V to 5.5V

3.0V to 3.6V

V

to V

SO

) after the last address input sig­nal is stable, providing the E
are also satisfied. If the E

(1)

V

CC

or

(2)

(min)

PFD

(2)

≤ V

SO

and G access times

and G access times are

E G W DQ0-DQ7 Power

V

IH

V

IL

V

IL

V

IL

X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode

not met, valid data will be available after the latter
of the Chip Enable Access Times (t
Enable Access Time (t

). The state of the eight

GLQV

three-state Data I/O signals is controlled by E
G

. If the outputs are activated before t

ELQV

) or Output

and

, the

AVQV

data lines will be driven t o an ind eterminate state
until t
while E
main valid for Output Data Hold Time (t

. If the Address Inputs are changed

AVQV

and G remain active, output data will re-

) but

AXQX

will go indeterminate until the next Address Ac­cess.

WRITE MODE

The M48T512Y/V is in the Wri te Mode whenever

(Write Enable) and E (Chip Enable) are low

W
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W
earlier rising edge of W
be held valid throughout the cycle. E
turn high for a minimum of t
or t

from Write Enable prior to the initiation of

WHAX

or E. A write is terminated by the

or E. The addresses must

or W must r e-

from Chip Enable

EHAX

another read or write cycle. Data-in must be valid

prior to the end of write and remain valid for

t

DVWH

t

afterward. G should be kept high during

WHDX

write cycles to avoid bus c ontention; although, if
the output bus has been activated by a low on E
and G a low on W will disable the outputs t
ter W

falls .

WLQZ

af-

X X High Z Standby
X

V

IL

V

IH

V

IL

V

IH

V

IH

D

IN

D

OUT

High Z Active

Active
Active

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no longer
driven.

Figure 3. AC Testing Load Circuit

DEVICE
UNDER

TEST

CL includes JIG capacitance

650Ω

CL = 100pF

1.75V

AI01803C

3/14

M48T512Y, M48T512V

Figure 4. Block Diagram

OSCILLATOR AND

CLOCK CHAIN

32,768 Hz

CRYSTAL

POWER

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

V

CC

DATA RETENTION MODE

With valid V

applied, the M48T512Y/V operates

CC

as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au­tomatically deselect, write protecting itself when
V

falls between V

CC

(max), V

PFD

(min) win-

PFD

dow. All outputs become high impedance an d all
inputs are treated as "don't care".

Note: A power fa ilure during a writ e cycle may cor­rupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
At voltage s below V
in a write protected state, provided the V
time is not less than t
spond to transient noise s pi kes on V

(min), the memory will be

PFD

. The M48T512Y/V may re-

F

that cr os s

CC

CC

fall

into the deselect window during the time the de­vice is sampling V
power supply lines is recomm ended. When V

.Therefore, decoupling of the

CC

CC

drops below VSO, the control circuit switches pow­er to the internal battery, preserving data and pow­ering the clock. The internal energy source will
maintain data in the M48T512Y/V for an accumu­lated period of at least 10 years at room tem pera­ture. As system power rises above V

SO

, the

battery is disconnected, and the power supply is

8 x 8

TIMEKEEPER

REGISTERS

A0-A18

DQ0-DQ7

E

W

G

AI02384

V

PFD

524,280 x 8

SRAM ARRAY

V

SS

switched to external VCC. Write protection contin­ues until V
Normal RAM operation can resume t
exceeds V

reaches V

CC

(max). Refer to Application Note

PFD

(min) plus t

PFD

ER

ER

after V

(AN1012) on the ST Web Site for more information
on battery life.

CLOCK OPERATIONS

Reading the Clock Updates to the TIMEKEEPER
registers should be halted before clock data is
read to prevent reading data in transition. Because
the BiPO RT TIMEKEEPER cells in the R AM array
are only data registers, and not the actual clock
counters, updating the registers can be halted
without disturbing the clock itself. Updating is halt­ed when a '1' is written to t he REA D bi t, D6 i n the
Control Register (7FFF8h). As long as a '1' re­mains in that position, updat ing is halted. After a
halt is issued, the registers reflect the count; that
is, the day, date, and time that were current at the
moment the halt comm and was issued. All of the
TIMEKEEPER registers are updated simulta­neously. A halt will not interrupt an update in
progress. Updating occurs 1 second after the
READ bit is reset to a '0'.

(min).

CC

4/14

M48T512Y, M48T512V

Table 5. Capacitance

(T

= 25 °C, f = 1 MHz)

A

(1)

Symbol Parameter Test Condition Min Max Unit

C

C

IO

Note: 1. Effective capacitance measured with po wer suppl y at 5V (M48T512Y) or 3.3V (M48T512V ). Sampled only, not 100% tested.

2. Outputs desele cted.

Input Capacitance

IN

(2)

Input / Output Capacitance

V

V

OUT

IN

= 0V

= 0V

20 pF
20 pF

Table 6A. DC Characteristics

= 0 to 70 °C; VCC = 4.5V to 5.5V)

(T

A

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

I

LO

I

CC

I

CC1

I

CC2

V

V

V

V

OH

Note: 1. Outputs deselected.

Input Leakage Current

(1)

Output Leakage Current
Supply Current Outputs open 115 mA

Supply Current (Standby) TTL
Supply Current (Standby) CMOS

Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2.2

IH

Output Low Voltage

OL

Output High Voltage

0V ≤ V

IN

0V ≤ V

OUT

E

= V

E

= VCC – 0.2V

I

= 2.1mA

OL

I

= –1mA

OH

≤ V

≤ V

IH

CC

CC

±2 µA
±2 µA

8mA
4mA

V

+ 0.3

CC

0.4 V

2.4 V

V

Table 6B. DC Characteristics

= 0 to 70 °C; VCC = 3.0V to 3.6V)

(T

A

Symbol Parameter Test Condition Min Max Unit

(1)

Input Leakage Current

I

LI

(1)

Output Leakage Current

I

LO

I

CC

I

CC1

I

CC2

V

V

V

V

OH

Note: 1. Outputs deselected.

Supply Current Outputs open 60 mA
Supply Current (Standby) TTL
Supply Current (Standby) CMOS

Input Low Voltage –0.3 0.4 V

IL

Input High Voltage 2.2

IH

Output Low Voltage

OL

Output High Voltage

0V ≤ V

IN

0V ≤ V

OUT

E

= V

E

= VCC – 0.2V

I

= 2.1mA

OL

I

= –1mA

OH

≤ V

≤ V

IH

CC

CC

±2 µA
±2 µA

4mA
3mA

V

+ 0.3

CC

0.4 V

2.2 V

V

5/14

M48T512Y, M48T512V

Figure 5. Power Down/Up Mode AC Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

VSO
V

SS

INPUTS

(Including E)

OUTPUTS

tWP

VALID VALID

Table 7. Power Down/Up Trip Points DC Characteristics

tF

tR

tER

RECOGNIZEDRECOGNIZED

AI02385

tFB

tDR

tRB

DON'T CARE

HIGH-Z

(1)

(TA = 0 to 70 °C)

Symbol Parameter Min Typ Max Unit

V

PFD

Power-fail Deselect Voltage

M48T512Y 4.2 4.35 4.5 V
M48T512V 2.7 2.9 3.0 V

V

SO

t

DR

Note: 1. All voltages referenced to VSS.

2. At 25°C.

Battery Back-up Switchover Voltage

V

M48T512V

(2)

Expected Data Retention Time 10 YEARS

PFD

–100mV

Table 8. Power Down/Up AC Characteristics

(T

= 0 to 70 °C)

A

Symbol Parameter Min Max Unit

M48T512Y 3.0 V

(1)

t

F

t

FB

t

R

t

RB

t

WP

t

ER

Note: 1. V

2. V

V

(max) to V

PFD

(2)

V

(min) to VSS VCC Fall Time

PFD

V

(min) to V

PFD

VSS to V

PFD

Write Protect Time on VCC = V

(min) V

PFD

(max) VCC Rise Time

PFD

(min) V

Rise Time

CC

Fall Time

CC

PFD

300 µs

M48T512Y 10 µs
M48T512V 150 µs

10 µs

1µs

40 150 µs

E Recovery Time 40 200 ms

(max) to V

PFD

es V

(min).

PFD

(min) to VSS fall time of less than tFB may cause corruption of RAM data.

PFD

(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-

PFD

6/14

Table 9. Read Mode AC Characteristics

(T

= 0 to 70 °C)

A

M48T512Y, M48T512V

M48T512Y M48T512V

Symbol Parameter

Min Max Min Max

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. CL = 100pF.

2. C

Read Cycle Time 70 85 ns

(1)

Address Valid to Output Valid 70 85 ns

(1)

Chip Enable Low to Output Valid 70 85 ns

(1)

Output Enable Low to Output Valid 40 55 ns

(2)

Chip Enable Low to Output Transition 5 5 ns

(2)

Output Enable Low to Output Transition 5 5 ns

(2)

Chip Enable High to Output Hi-Z 25 30 ns

(2)

Output Enable High to Output Hi-Z 25 30 ns

(1)

Address Transition to Output Transition 10 5 ns

= 5pF.

L

Figure 6. Address Controlled, Read Mode AC Waveforms

tAVAV

Unit-70 -85

A0-A16

tAVQV

tAXQX

DQ0-DQ7

DATA VALID

Setting the Clock. Bit D7 of the Control Register
(7FFF8h) is the WRITE bit. Setting the WRITE bit
to a '1', like the READ bit, halts updates to the
TIMEKEEPER registers. The user can then load
them with the correct day, date, and time data in
24 hour BCD format (see Table 11). Resetting the
WRITE bit to a '0' then t ransfers the values o f all
time registers 7FFFFh-7FFF9h to the actual TIME­KEEPER counters and allows normal operation to
resume. After the WRITE bit is reset, the next
clock update will occur approximately one second
later. See Application Note, AN923, (TIMEKEEP­ERS "ROLLING INTO" THE 21ST CENTURY) on
the ST Web Site for more information on Century
Rollover.

VALID

DATA VALID

AI02324

Note: Upon power-up, both the WRITE bit and the
READ bit w ill be re s et to '0'.

Stopping and Starting the Oscillator. The os­cillator may be stopped at any time. If the device is
going to spend a significant amount of time on the
shelf, the oscillator can be turned off to minimize
current drain on the battery. The STOP bit is locat­ed at Bit D7 within 7FFF9h. Setting it to a '1' stops
the oscillator. The M48T512Y/V is shipped from
STMicroelectronics with the STOP bit set to a '1'.
When reset to a '0', the M48T512Y/V oscillator
starts after approximately one second.

Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).

7/14

M48T512Y, M48T512V

Table 10. Write Mode AC Characteristics

(T

= 0 to 70 °C)

A

M48T512Y M48T512V

Symbol Parameter

t

AVAV

t

AVWL

t

AVEL

t

WLWH

t

ELEH

t

WHAX

t

EHAX

t

DVWH

t

DVEH

t

WHDX

t

EHDX

(1, 2)

t

WLQZ

t

AVWH

t

AVE1H

(1, 2)

t

WHQX

Note: 1. CL = 5pF.

2. If E

Write Cycle Time 70 85 ns
Address Valid to Write Enable Low 0 0 ns
Address Valid to Chip Enable Low 0 0 ns
Write Enable Pulse Width 50 60 ns
Chip Enable Low to Chip Enable High 55 65 ns
Write Enable High to Address Transition 5 5 ns
Chip Enable High to Address Transition 10 15 ns
Input Valid to Write Enable High 30 35 ns
Input Valid to Chip Enable High 30 35 ns
Write Enable High to Input Transition 5 5 ns
Chip Enable High to Input Transition 10 15 ns

Write Enable Low to Output Hi-Z 25 30 ns
Address Valid to Write Enable High 60 70 ns

Address Valid to Chip Enable High 60 70 ns
Write Enable High to Output Transition 5 5 ns

goes low simultaneously with W goin g l ow, the output s remain in the high impedance state.

Unit-70 -85

Min Max Min Max

Calibrating the Clock. The M48T512Y/V is driv-

en by a quartz c ontr olled oscillator w ith a nominal
frequency of 32,768Hz. The devices are factory
calibrated at 25°C and tested f or accuracy. Clock
accuracy will not exceed 35 ppm (parts per million)
oscillator frequency error at 25°C, which equates
to about ±1.53 minutes per month. When t he Cal­ibration circuit is properly employed, accuracy im­proves to better than +4 ppm at 25°C. The
oscillation rate of crystals change s with tempera­ture. The M48T512Y/V design employs periodic
counter correction. The calibration c ircuit adds or
subtracts counts from the o scillator divider circuit
at the divide by 256 stage, as shown in Figure 10.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load­ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-

8/14

tracting counts slows the clock down. The Calibra­tion bits occupy the five lower order bits (D4-D0) in
the Control Register 7FFF8h. These bits can be
set to represent any value between 0 and 31 in bi­nary form. Bit D5 is a Sign bit; '1' indicates positive
calibration, '0' indicates negative calibration. Cali­bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each cal ibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 actual oscillator cycles; that
is, +4.068 or –2.034 ppm of adjustment per cali­bration step in the calibration register.

M48T512Y, M48T512V

Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

tAVAV

A0-A18

tAVQV tAXQX

tELQV

E

tELQX

G

tGLQX

DQ0-DQ7

VALID

tGLQV

Figure 8. Write Enable Controlled, Write AC Waveforms

tEHQZ

tGHQZ

DATA OUT

AI02389

A0-A18

E

W

DQ0-DQ7

tAVEL

tAVWL

tWLQZ

tAVAV
VALID

tAVWH

tWLWH

tDVWH

tWHAX

tWHQX

tWHDX

DATA INPUT

AI02386

9/14

M48T512Y, M48T512V

Figure 9. Chip Enable Controlled, Write AC Waveforms

tAVAV

A0-A18

tAVEL

E

tAVWL

W

DQ0-DQ7

Assuming that the oscillator is running at exactly
32,768Hz, each of the 31 increments in the Cali-

bration byte would represent +1 0.7 or –5.35 sec­onds per month which corresponds to a total range
of +5.5 or –2.75 minutes pe r month. Figure 10 il­lustrate s a TIMEKEEPER calibrati o n wavefor m.

One method for ascertaining how much calibration
a given M48T512Y/V may require involves setting
the clock, letting it run for a month and compa ring
it to a known accurate reference and recording de­viation over a fixed period of time.

Calibration values, including the number of sec­onds lost or gained in a given period, can be found
in STMicroelectronics Application Note: TIME­KEEPER CALI BRATION. T his all ows the d esigner
to give the end user the ability to calibrate the
clock as the environment requires, even if the f inal
product is packaged in a non-user serviceable en­closure. The designer could provide a simple utility
that accesses the Calibration bi ts. Fo r m ore in for­mation on calibration, see Application Note (TIME­KEEPER CALIBRATION) on the ST Web Site .

VALID

tAVEH

tELEH

DATA INPUT

tDVWH

tEHAX

tWHDX

POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION

Note: I

transients, including those produced by

CC

output switching, can produce voltage fluctua­tions, resulting in spikes on the V
transients can be reduced if capacitors are used to
store energy, which stabilizes the V
energy stored in the bypass c apacitors will be re­leased as low going spikes are generated or ener­gy will be absorbed when overshoots occur. A
ceramic bypass capacitor value of 0.1µF is recom­mended in order to provide the needed filtering. In
addition to transients that are caused by normal
SRAM operation, power cycling can generate neg­ative voltage spikes on V
below V

by as much as one volt. These negative

SS

that drive it to values

CC

spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, ST recommends connecting
a schottky diode from V
nected to V

, anode to VSS). (Schottky diode

CC

to VSS (cathode con-

CC

1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount).

AI02387

bus. These

CC

bus. The

CC

10/14

M48T512Y, M48T512V

Table 11. Register Map

Address

Data

D7 D6 D5 D4 D3 D2 D1 D0

7FFFFh 10 Years Year Year 00-99

7FFFEh 0 0 0 10 M Month Month 01-12
7FFFDh 0 0 10 Date Date Date 01-31
7FFFCh 0 0 0 0 0 Day Day 01-07

7FFFBh 0 0 10 Hours Hours Hour 00-23

7FFFAh 0 10 Minutes Minutes Minutes 00-59

7FFF9h ST 10 Seconds Seconds Seconds 00-59

7FFF8h W R S Calibration Control

Keys: S = SIGN Bit

R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to zero

Function/Rang e

BCD Format

Figure 10. Cal ib rat i on Waveform

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

AI00594B

11/14

M48T512Y, M48T512V

Table 12. Ordering Information Scheme

Example: M48T512Y -70 PM 1

Device Type

M48T

Supply Voltage and Write Protect Voltage

512Y = V
512V = V

Speed

-70 = 70ns

-85 = 85 ns

Package

PM = PMDIP32

Temperature Range

1 = 0 to 70 °C

= 4.5V to 5.5V; V

CC

= 3.0V to 3.6V; V

CC

= 4.2V to 4.5V

PFD

= 2.7V to 3.0V

PFD

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the ST Sales Office nearest to you.

Table 13. Revision History

Date Revision Details

June 1998 First Issue

(Min) changed

PFD

12/03/99

M48T512Y: V
Figure 3 changed

changed (Figure 5, Table 8)

t

FB

t

changed (Figure 5, Table 8)

RB

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M48T512Y, M48T512V

Table 14. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 9.27 9.52 0.365 0.375

A1 0.38 – 0.015 –

B 0.43 0.59 0.017 0.023
C 0.20 0.3 3 0.008 0.013
D 42.42 43.18 1.670 1.700

E 18.03 18.80 0.710 0.740
e1 2.29 2.7 9 0.090 0.110
e3 34.29 41.91 1. 350 1.650
eA 14.99 16.0 0 0.590 0.630

L 3.05 3.81 0. 120 0.150
S 1.91 2.79 0.075 0.110
N 32 32

mm inches

Figure 11. PMDIP32 - 32 pin Plastic Module DIP, Package Outline

A1AL

S

Be1

e3

D

N

E

1

Drawing is not to scale.

C

eA

PMDIP

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M48T512Y, M48T512V

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