WDIWatchdog Input
EChip Enable
GOutput Enable
WWrite Enable
V
CC
V
SS
NCNot connected Internally
Interrupt / Frequency Test Output
(Open Drain)
Supply Voltage
Ground
PFD
PFD
≤ 4.5V
≤ 3.0V
SNAPHAT (SH)
Battery
44
1
SOH44 (MH)
Figure 1. Logic Diagram
V
CC
15
A0-A14
W
E
G
WDI
M48T37Y
M48T37V
V
SS
M48T37Y
M48T37V
8
DQ0-DQ7
RST
IRQ/FT
AI02172
1/20February 2000
M48T37Y, M48T37V
Table 2. Absolute Maximum Ratings
SymbolParameterValueUnit
T
A
T
STG
(2)
T
SLD
V
IO
V
CC
I
O
P
D
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHATsockets.
Ambient Operating Temperature
Storage Temperature (VCCOff,Oscillator Off)
Lead Solder Temperature for 10 seconds260°C
Input or Output Voltages
Supply Voltage
Output Current10mA
Power Dissipation1W
(1)
Grade 10 to 70°C
Grade 6–40 to 85°C
SNAPHAT–40 to 85°C
SOIC–55 to 125°C
M48T37Y–0.3 to 7V
M48T37V–0.3 to 4.6V
M48T37Y–0.3 to 7V
M48T37V–0.3 to 4.6V
W
A13
A8
A9
A11
G
NC
NC
A10
E
NC
DQ7
DQ6
DQ5DQ1
DQ4
DQ3
NC
DESCRIPTION
The M48T37Y/37V TIMEKEEPER RAM is a
32Kb x8 non-volatile static RAM and real time
clock. The monolithic chip is available in a special
package which provides a highly integrated battery backed-up memory and real time clock solution.
The 44 lead 330mil SOIC package provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing
containing the battery and crystal. The unique design allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape &Reel
form. For the 44 lead SOIC, the battery/crystal
package (i.e. SNAPHAT) part number is ”M4T28BR12SH” or ”M4T32-BR12SH”.
Caution: Donot place theSNAPHAT battery/crystal topin conductive foam,as this will drain the lithium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T37Y/37V are integrated on one silicon chip.
Note: 1. X = VIHor VIL;VSO= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
4.5V to 5.5V
(M48T37Y)
3.0V to 3.6V
(M48T37V)
to V
V
SO
Figure 3. Block Diagram
IRQ/FTWDI
OSCILLATOR AND
CLOCK CHAIN
32,768
Hz
CRYSTAL
POWER
XXHigh ZStandby
XVILD
V
IL
V
IH
V
IH
V
IH
16 x 8 BiPORT
SRAM ARRAY
IN
D
OUT
High ZActive
Active
Active
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
CC
RSTV
V
PFD
32,752 x
SRAM ARRAY
8
V
SS
A0-A14
DQ0-DQ7
E
W
G
AI03253
3/20
M48T37Y, M48T37V
Table 4. AC Measurement Conditions
Input Rise and Fall Times≤ 5ns
Input Pulse Voltages0 to 3V
Input and Output Timing Ref. Voltages1.5V
Note that Output Hi-Z isdefined as the point where data is no longer
driven.
The memory locations, to provide user accessible
BYTEWIDE clock information are in the bytes
with addresses 7FF1 and 7FF9h-7FFFh (located
in Table 11). The clock locations contain the century, year, month, date, day, hour, minute, and
second in 24hour BCD format. Corrections for 28,
29 (leap year-compliant until the year 2100), 30,
and 31 day months are made automatically.
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control microprocessor and provides a reset orinterrupt to it.
Byte 7FF2h-7FF5h are reserved for clock alarm
programming.
These bytes can be used to set the alarm. This will
generate an active low signal on the IRQ/FT pin
when the alarm bytes match the date, hours, minutes and seconds of the clock. The eight clock
bytes are not the actual clock counters themselves; theyare memory locations consistingof BiPORT read/write memory cells. The M48T37Y/
37V includes a clock control circuit which updates
the clock bytes with current information once per
second. The information can be accessed by the
user in the same manner as any other location in
the static memory array.
The M48T37Y/37V alsohas its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCCsupply for an out of tolerance
condition. When VCCis out of tolerance, the circuit
writes protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation broughton by low VCC.AsVCCfalls
below the Battery Back-up Switchover Voltage
(VSO), the control circuitry connects the battery
which maintains data and clock operation until valid power returns.
Figure 4. AC Testing Load Circuit
DEVICE
UNDER
TEST
CLincludes JIG capacitance
Note: Excluding open-drain output pins.
645Ω
CL= 100pF
1.75V
AI02325
READ MODE
The M48T37Y/37V is in the Read Mode whenever
Write Enable (W) is high and Chip Enable (E) is
low. The unique address specified by the 15 AddressInputs defineswhich oneof the 32,752 bytes
of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access
time (t
) after the last address input signal is
AVQV
stable, providing that the E and OutputEnable (G)
access times are also satisfied. If the E and G access times are not met, valid data will be available
after the latter of the Chip Enable Access time
(t
) or Output Enable Access time (t
ELQV
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E andG. If the outputs are activated before t
indeterminate state until t
, the data lineswill be driven to an
AVQV
AVQV
.
If the Address Inputs are changed while E and G
remain active,output data will remainvalid for Output Data Hold time (t
) but will be indetermi-
AXQX
nate until the next Address Access.
4/20
M48T37Y, M48T37V
Table 5. Capacitance
(1, 2)
(TA=25°C)
SymbolParameterTest ConditionMinMaxUnit
C
IN
C
IO
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Input Capacitance
(3)
Input / Output Capacitance
V
V
OUT
IN
=0V
=0V
10pF
10pF
Table 6. DC Characteristics
(TA= 0 to 70 °C or –40 to 85 °C)
M48T37YM48T37V
V
SymbolParameterTestCondition
(1)
I
LI
I
LO
I
I
CC1
I
CC2
V
IL
V
V
V
V
OH
Note: 1. Outputs deselected.
Input Leakage Current
(1)
Output Leakage Current
Supply CurrentOutputs open5033mA
CC
Supply Current (Standby)
TTL
Supply Current (Standby)
CMOS
(2)
Input Low Voltage–0.30.8–0.30.8V
Input High Voltage2.2
IH
Output Low Voltage
OL
(standard)
Output Low Voltage
OL
(open drain)
(2)
Output High VoltageIOH= –1mA2.42.4V
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
0V ≤ V
0V ≤ V
E=V
I
OL
I
OL
IN
OUT
E=V
– 0.2V
CC
= 2.1mA
= 10mA
≤ V
≤ V
IH
CC
CC
= 4.5V to 5.5VVCC= 3.0V to 3.6V
CC
MinMaxMinMax
±1±1µA
±1±1µA
32mA
32mA
V
CC
+ 0.3
2.2
VCC+ 0.3
0.40.4V
0.40.4V
Unit
V
5/20
M48T37Y, M48T37V
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(TA= 0 to 70 °C or –40 to 85 °C)
SymbolParameterMinTypMaxUnit
M48T37Y4.24.44.5V
V
V
t
Note: 1. All voltages referenced to VSS.
Power-fail Deselect Voltage
PFD
Battery Back-up Switchover Voltage
SO
Expected Data Retention Time (25°C)
DR
2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
M48T37V2.72.93.0V
M48T37Y
M48T37V
Grade 1
Grade 6
10
5
(2)
V
BAT
V
–100mV
PFD
7YEARS
YEARS
Table 8. Power Down/Up AC Characteristics
(TA= 0 to 70 °C or –40 to 85 °C)
SymbolParameterMinMaxUnit
(1)
V
t
F
t
FB
t
R
t
RB
t
REC
Note: 1. V
2. V
3. t
(max) to V
PFD
(2)
V
(min) to VSSVCCFallTime
PFD
V
(min) to V
PFD
VSSto V
(3)
V
(max) to V
PFD
es V
PFD
(min) to VSSfall time of less than tFBmay cause corruption of RAM data.
PFD
(min) = 20ms for Industrial Temperature Range - grade 6 device.
REC
PFD
(max) to RST High
PFD
(min)fall time of less than tF may result in deselection/write protection not occurring until200µs afterVCCpass-
PFD
(min).
(min) VCCFall Time300µs
PFD
M48T37Y10µs
M48T37V150µs
(max) VCCRise Time
PFD
10µs
(min) VCCRise Time1µs
40200ms
V
V
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
V
SO
6/20
RST
INPUTS
OUTPUTS
tF
VALID
VALIDVALID
tFB
tDR
DON’T CARE
HIGH-Z
tRB
tR
tREC
VALID
AI03078
Loading...
+ 14 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.