SGS Thomson Microelectronics M48T35Y-70PC1, M48T35, M48T35Y-70MH1, M48T35Y Datasheet

M48T35

M48T35Y

256 Kbit (32Kb x8) TIMEKEEPER® SRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY

■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS

■ BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES and SECONDS

■ FREQUENCY TEST OUTPUT for REAL TIME

CLOCK

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

(V

= Power-fail Deselect Voltage):

PFD

– M48T35: 4.5V ≤ V
– M48T35Y: 4.2V ≤ V

■ SELF-CONTAINED BATTERY and CRYSTA L

PFD

PFD

≤ 4.75V

≤ 4.5V

in the CAPHAT DIP PACKAGE

■ SOIC PACKAGE PROVID ES D IREC T

CONNECTION for a SNAPHAT HOUSING
CONTAINING the BATTERY and CRYSTAL

■ SNAPHAT

®

HOUSING (BATTERY and

CRYSTAL) is REPLAC EABLE

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 32Kb x8 SRAMs

SNAPHAT (SH)

Battery

28

28

1

SOH28 (MH)

Figure 1. Logic Diagram

V

CC

15

A0-A14

1

PCDIP28 (PC)

Battery CAPHAT

8

DQ0-DQ7

Table 1. Signal Names

A0-A14 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
W
V
V

CC

SS

Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground

W

M48T35

M48T35Y

E

G

V

SS

AI01620B

1/18February 2000

M48T35, M48T35Y

Figure 2A. DIP Connections

A14 V

1

A12

2
3

A7

4

A6

5

A5

6

A4

7

A3
A2
A1
A0

DQ0

8
9
10
11

M48T35

M48T35Y

12
13

DQ2

14

SS

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

(2)

T

SLD

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional opera tion of the devi ce at these or any other conditions above those i ndi cated in th e operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoo ts bel ow –0.3V are not allowed on any pi n while in the B attery Ba ck-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Ambient Operating Temperature

Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V

Supply Voltage –0.3 to 7 V
Output Current 20 mA
Power Dissipation 1 W

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01621B

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

(1)

Figure 2B. SOIC Connections

A14 V
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

1
2
3
4
5
6
7

M48T35Y

8
9
10
11
12

DQ2

SS

Grade 1 0 to 70 °C
Grade 6 –40 to 85 °C

13
14

–40 to 85 °C

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01622B

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

DESCRIPTION

®

The M48T35/35Y TIMEKEEPER

RAM is a 32Kb
x8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packag­es to provide a highly integrated battery backed-up
memory and real time clock solution.

The M48T35/35Y is a non-volatile pin and function
equivalent to any JEDEC standard 32Kb x8
SRAM. It also easily fits into many ROM, EPROM,

2/18

and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number o f writes
that can be performed.

The 28 pin 600mil DIP CAPHAT houses the
M48T35/35Y silicon with a quartz crystal and a
long life lithium button cell in a single package.

The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-

M48T35, M48T35Y

V

PFD

≤ V

CC

or

SO

(1)

(min)

(2)

E G W DQ0-DQ7 Power

V

IH

V

IL

V

IL

V

IL

X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode

Table 3. Operating Modes

Mode

Deselect
Write
Read
Read

Deselect
Deselect

Note: 1. X = VIH or VIL; VSO = Battery Back-up Swit ch ov er Volta ge.

2. See T able 7 for deta ils.

4.75V to 5.5V

4.5V to 5.5V

V

to V

SO

Figure 3. Block Diagram

OSCILLATOR AND

CLOCK CHAIN

32,768 Hz
CRYSTAL

X X High Z Standby
X

V

IL

V

IH

V

IL

V

IH

V

IH

8 x 8 BiPORT

SRAM ARRAY

D

D

OUT

IN

Active
Active

High Z Active

A0-A14

POWER

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

V

CC

nection to a separate SNAPHAT housing cont ain­ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser­tion of the SNAPHAT housing after reflow pre­vents potential battery and c rystal dam age due to
the high temperatures required for device surface­mounting. The SNAPHAT housing is keyed to pre­vent reverse insertion. The SOIC and battery/crys­tal packages are shipped separately in plastic anti­static tubes or in Tape & Reel form.

DQ0-DQ7

E

W

G

AI01623

V

PFD

32,760 x 8

SRAM ARRAY

V

SS

For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4T28­BR12SH1".

As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T35/35Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE clock information in the bytes with ad­dresses 7FF8h-7FFFh.

3/18

M48T35, M48T35Y

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no longer
driven.

The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for­mat. Corrections for 28, 29 (leap year), 30, and 31
day months are made automatically. Byte 7FF8h
is the clock control register. This byte controls user
access to the clock information and also stores the
clock calibration setting.

The eight clock bytes are not the actual clock
counters themselves; they are memory locat ions
consisting of BiPORT read/write memory cells.
The M48T35/35Y includes a clock control circuit
which updates the clock bytes with current infor­mation once per second. The information can be
accessed by the user i n t he sa me m anner as any
other location in the static memory array.

The M48T35/35Y also has its own Power-fail De­tect circuit. The control circuitry constantly moni­tors the single 5V supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the S RAM, p roviding a high degree
of data security in the midst of unpredictable s ys­tem operation brought on by low V

. As VCC falls

CC

below approximately 3V, the control circuitry con­nects the battery which maintains data and clock
operation until valid power returns.

READ MODE

The M48T35/35Y is in the Read Mode whenever

(Write Enable) is high and E (Chip Enable) is

W
low. The unique address specified by the 15 A d­dress Inputs defines which one of the 32,768 bytes
of data is to be acces sed. Valid data will be avail­able at the Data I/O pi ns within Address Access
time (t
stable, providing that the E

) after the last address input s ignal is

AVQV

and G access times

are also satisfied.
If the E

and G access times are not met, valid data

will be avai la ble af ter the latte r of the C hip Enable

Figure 4. AC Testing Load Circuit

5V

1.9kΩ

DEVICE
UNDER

TEST

1kΩ

CL includes JIG capacitance

Access time (t
(t

).

GLQV

ELQV

) or Output Enable Access time

OUT

CL = 100pF or 5pF

AI01030

The state of the eight t hree-s tate Da ta I/O s i gnals
is controlled by E
ed before t
indeterminate state until t

If the Address Inputs are changed while E

and G. If the outputs are activat-

, the data lines will be driven to an

AVQV

AVQV

.

and G
remain active, output data will remain valid for Out­put Data Hold time (t

) but will go indetermi-

AXQX

nate until the next Address Access.

WRITE MODE

The M48T35/35Y is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring f alling edge of W

or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E
of t

EHAX

or W must return high for a minimum

from Chip Enable or t

from Write En-

WHAX

able prior to the initiation of another read or write
cycle. Data -in must be vali d t
of write and remain valid for t

prior to the end

DVWH

afterward. G

WHDX

should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E
will disab le the ou t pu t s t

and G, a low on W

after W falls.

WLQZ

4/18

M48T35, M48T35Y

Table 5. Capacitance

(T

= 25 °C)

A

(1, 2)

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IO

Note: 1. Effective capacitance measured with power suppl y at 5V.

2. Sampled only, not 100% tested.

3. Outputs desele ct ed.

Input Capacitance

(3)

Input / Output Capacitance

V

V

OUT

IN

= 0V

= 0V

10 pF
10 pF

Table 6. DC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

A

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

I

LO

I

CC

I

CC1

I

CC2

V

IL

V

IH

V

OL

V

OH

Note: 1. Outputs deselected.

2. Negativ e s p i k e s of –1V allo wed for up t o 10 ns once pe r cycle .

Input Leakage Current

(1)

Output Leakage Current
Supply Current Outputs open 50 mA
Supply Current (Standby) TTL

Supply Current (Standby) CMOS

(2)

Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2
Output Low Voltage

Output High Voltage

0V ≤ V

IN

0V ≤ V

OUT

E

= V

E

= VCC – 0.2V

I

= 2.1mA

OL

I

= –1mA

OH

≤ V

≤ V

IH

CC

CC

±1 µA
±5 µA

3mA
3mA

V

+ 0.3

CC

0.4 V

2.4 V

V

Table 7. Power Down/Up Trip Points DC Characteristics

(1)

(TA = 0 to 70 °C or –40 to 85 °C)

Symbol Parameter Min Typ Max Unit

V

PFD

V

SO

t

DR

Note: 1. All voltages referenced to VSS.

2. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top t

3. Usi ng larger M4T 32-BR12SH6 SNAPHA T t op (recommended for I ndustrial Temperature Range - grade 6 device).

Power-fail Deselect Voltage

Battery Back-up Switchover Voltage 3.0 V

Expected Data Retention Time
(at 25°C)

M48T35 4.5 4.6 4.75 V

M48T35Y 4.2 4.35 4.5 V

Grade 1
Grade 6

10
10

(2)

(3)

= 7 years (typ) .

DR

YEARS
YEARS

5/18

M48T35, M48T35Y

Table 8. Power Down/Up AC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C)

A

Symbol Parameter Min Max Unit

t

PD

t

F

t

FB

t

R

t

RB

t

REC

Note: 1. V

2. V

3. t

E or W at VIH before Power Down

(1)

V

(max) to V

PFD

(2)

V

(3)

PFD

es V

PFD

PFD

(min) = 20ms for indust ri al temperature grad e (6) device.

REC

(min) to VSS VCC Fall Time

PFD

V

(min) to V

PFD

VSS to V
V

(max) to V

(min).

(min) to VSS fall time of less than tFB may cause corruption of RAM data.

PFD

(max) to Inputs Recognized

PFD

(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-

PFD

(min) VCC Fall Time

PFD

(max) VCC Rise Time

PFD

(min) VCC Rise Time

Figure 5. Power Down/Up Mode AC Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

VSO

tF

tPD

INPUTS

tFB

tDR

tRB

DON'T CARE

0 µs

300 µs

10 µs
10 µs

1µs

40 200 ms

tR

tREC

RECOGNIZEDRECOGNIZED

6/18

OUTPUTS

VALID VALID

(PER CONTROL INPUT)

HIGH-Z

(PER CONTROL INPUT)

AI01168C

Table 9. Read Mode AC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

A

M48T35, M48T35Y

M48T35 / M48T35Y

Symbol Parameter

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. CL = 100pF.

2. C

Read Cycle Time 70 ns

(1)

Address Valid to Output Valid 70 ns

(1)

Chip Enable Low to Output Valid 70 ns

(1)

Output Enable Low to Output Valid 35 ns

(2)

Chip Enable Low to Output Transition 5 ns

(2)

Output Enable Low to Output Transition 5 ns

(2)

Chip Enable High to Output Hi-Z 25 ns

(2)

Output Enable High to Output Hi-Z 25 ns

(1)

Address Transition to Output Transition 10 ns

= 5pF.

L

Figure 6. Read Mode AC Waveforms.

Unit-70

Min Max

A0-A14

E

G

DQ0-DQ7

Note: Write Enable (W

) = High.

tAVAV
VALID

tAVQV tAXQX

tELQV

tELQX

tGLQX

tGLQV

tGHQZ

VALID

tEHQZ

AI00925

7/18

M48T35, M48T35Y

Table 10. Write Mode AC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

A

M48T35 / M48T35Y

Symbol Parameter

t

AVAV

t

AVWL

t

AVEL

t

WLWH

t

ELEH

t

WHAX

t

EHAX

t

DVWH

t

DVEH

t

WHDX

t

EHDX

(1, 2)

t

WLQZ

t

AVWH

t

AVEH

(1, 2)

t

WHQX

Note: 1. CL = 5pF.

2. If E

Write Cycle Time 70 ns
Address Valid to Write Enable Low 0 ns
Address Valid to Chip Enable Low 0 ns
Write Enable Pulse Width 50 ns
Chip Enable Low to Chip Enable High 55 ns
Write Enable High to Address Transition 0 ns
Chip Enable High to Address Transition 0 ns
Input Valid to Write Enable High 30 ns
Input Valid to Chip Enable High 30 ns
Write Enable High to Input Transition 5 ns
Chip Enable High to Input Transition 5 ns

Write Enable Low to Output Hi-Z 25 ns
Address Valid to Write Enable High 60 ns

Address Valid to Chip Enable High 60 ns
Write Enable High to Output Transition 5 ns

goes low simultaneously with W going l ow, the output s remain in the hi gh i mpedanc e st ate.

Unit-70

Min Max

DATA RETENTION MODE

With valid V

applied, the M48T35/35Y operates

CC

as a conventional BYTEWIDE static RAM. Should
the supply voltage de cay, the RA M will a utomati­cally power-fail deselect, write protecting itself
when V

falls w ithin t he V

CC

PFD

(max), V

PFD

(min)
window. All outputs become high impedance, and
all inputs are treated as "don't care."

Note: A power failure during a write cycle may cor­rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below V

(min), the user can be as-

PFD

sured the memory will be in a write protected state,
provided the V

fall time is not less than tF. The

CC

M48T35/35Y may respond to transient noise
spikes on V
during the time the device is sampling V

that reach into the deselect window

CC

. There-

CC

fore, decoupling of the power supply lines is rec­ommended.

8/18

When V

drops below VSO, the control circuit

CC

switches power to the internal battery which pre­serves data and powers the clock. The internal
button cell will maintain data in the M48T35/35Y
for an accumulated period of at least 7 years when

is less than VSO. As system power returns

V

CC

and V

rises above VSO, the battery is discon-

CC

nected, and the power supply is switched to exter­nal V
reaches V
kept high as V

. Write protection continues until V

CC

(min) plus t

PFD

rises past V

CC

(min). E should be

REC

(min) to prevent

PFD

CC

inadvertent write cycles prior to processor stabili­zation. Normal RAM operation c an resume t
after VCC exceeds V

PFD

(max).

REC

For more information on Battery Storage Life refer
to the Application Note AN1012.

Figure 7. Write Enable Controlled, Write AC Waveform

tAVAV

M48T35, M48T35Y

A0-A14

tAVEL

E

tAVWL

W

tWLQZ

DQ0-DQ7

VALID

tAVWH

tWLWH

Figure 8. Chip Enable Controlled, Write AC Waveforms

tAVAV

tDVWH

tWHAX

tWHQX

tWHDX

DATA INPUT

AI00926

A0-A14

E

W

DQ0-DQ7

tAVEL

tAVWL

VALID

tAVEH

tELEH

DATA INPUT

tDVEH

tEHAX

tEHDX

AI00927

9/18

M48T35, M48T35Y

Table 11. Register Map

Address

Data

D7 D6 D5 D4 D3 D2 D1 D0

7FFFh 10 Years Year Year 00-99
7FFEh 0 0 0 10 M Month Month 01-12
7FFDh 0 0 10 Date Date: Day of Month Date 01-31
7FFCh 0 FT CEB CB 0 Day of Week Century/Day 00-01/01-07
7FFBh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23
7FFAh 0 10 Minutes Minutes Minutes 00-59
7FF9h ST 10 Seconds Seconds Seconds 00-59
7FF8h W R S Calibration Control

Keys: S = Sign Bit

FT = Frequen cy T est Bit (Must be set to ‘0’ upo n power for nor m al operation)
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to ze ro
CEB = Cent ury Enable Bit
CB = Century Bit

Note: When CEB is set to ‘1’, CB will toggle from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn of the century (dependent upon the initial value set).

When CEB is set to ‘0’, CB will not toggle.
The WRIT E B i t does not need to be set to writ e to CEB and CB.

Function/Ran ge

BCD Format

CLOCK OPERATIONS

Reading the Clock Updates to the TIMEKEEPER
registers should be halted before clock data is
read to prevent reading data in transition. Because
the BiPO RT TIMEKEEPER cells in the R AM array
are only data registers, and not the actual clock
counters, updating the registers can be halted
without disturbing the clock itself.

Updating is halted when a ’1’ is written to the
READ bit, D6 in the Con trol Register 7FF8h. As
long as a ’1’ remains in that position, updating is
halted. After a h alt is issu ed, the registers reflect
the count; tha t is, the day, dat e, and the time that
were current at the moment the halt command was
issued.

All of the TIMEKEEPER registers are updated si­multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.

Setting the Clock

Bit D7 of the Control Register 7FF8h is the WRITE
bit. Setting the WRITE bit to a ’1’, like the READ
bit, halts updates to the T IMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD f ormat (see
Table 11). Resetting the WRITE bit to a ’0’ then
transfers the values of all time registers 7FF9h­7FFFh to the actual TIMEKEEPER counters and

allows normal operation to resume.The FT bit and
the bits marked as ’0’ in Table 11 must be written
to ’0’ to allow for normal TIMEKEEPER and RAM
operation. After the WRITE bit is reset, the next
clock update will occur within one second.

See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" on the for information
on Century Rollover.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ’1’ stops the oscillator. The M48T35/35Y is
shipped from STMicroelectronics with the STOP
bit set to a ’1’. When reset to a ’0’, the M48T35/35Y
oscillator starts within 1 second.

Calib ratin g t h e C lock

The M48T35/35Y is driven b y a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed 35 ppm
(parts per million) oscillator frequency error at

25 °C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M 48T35 /35 Y im proves t o better
than ±4 ppm at 25 °C. The oscillation rate of any
crystal changes with temperature (see Figure 10).

10/18

Figure 9. Clock Calibration

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

M48T35, M48T35Y

AI00594B

Most clock chips compensate for crystal frequency
and temperature shift error with cumberso me trim
capacitors. The M48T35/35Y design, however,
employs periodic c ounter correction. The calibra­tion circuit adds or subtracts counts from the oscil­lator divider circuit at th e divide by 256 stage, as
shown in Figure 9. The number of times pulses are
blanked (subtracted, n egative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five Calibration bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indi­cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 m inute
cycle. The first 62 m inutes i n t he c ycle m ay , onc e
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi­nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, t he first 12 will be affected,
and so on.

Therefore, each cal ibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra­tion step in the cal ibration registe r. Ass um ing that
the oscillator is in fact running at exactly 32,768
Hz, each of the 31 increm ents in the Calibration
byte would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.

Two methods are available for ascertaining how
much calibration a given M48T35/35Y may re­quire. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi­nal product is packaged in a non-user serviceable
enclosure.

All the designer has to do is provide a simple utility
that accesses the Calibration byte.

The second approach is better suit ed to a manu­facturing environment, and involves the use of
some test equipment. When the F requency Test
(FT) bit, the seventh-most significant bit in the Day
Register is set to a ’1’, and D7 of the Seconds Reg­ister is a ’0’ (Oscillator Running), DQ0 will toggle at
512Hz during a read of the Seconds Register. Any
deviation from 512 Hz indicates the degree and di­rection of oscillator frequency shift at the test tem­perature. For example, a reading of 512.01024 Hz
would indicate a +20 ppm oscillator frequen cy er-

ror, requiring a –10 (WR001010) to be loaded into
the Calibration Byte for correction. Note that set­ting or changing the Calibration Byte does n ot af­fect the Frequency test output frequency.

The FT bit MUST be reset to '0' for normal clock
operations to resume. The FT bit is automatically
Reset on power-up.

For more information on calibration, see the Appli­cation Note AN934 "TIMEKEEPER Calibration".

11/18

M48T35, M48T35Y

Figure 10. Crystal Accuracy Across Temp eratur e

Frequency (ppm)

20

0

–20

–40

–60

–80

∆F

–100

–120

–140

–160

0 10203040506070

Temperature °C

= -0.038 (T - T

F

ppm

C

T0 = 25 °C

)2 ± 10%

0

2

80–10–20–30–40

AI00999

POWER SUPPLY DECOUPLING and
UNDERSHOOT PROTECTION

I

transients, including those produced by output

CC

switching, can produce voltage fluctuations, re­sulting in spikes on the V

bus. These transients

CC

can be reduced if capacitors are used to store en­ergy, which stabilizes the V

bus. The energy

CC

stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass ca-

pacitor value of 0.1µF (as shown in Figure 11) is
recommended in order to provide the needed fil­terin g.

In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg­ative voltage spikes on VCC that drive it to values
below VSS by as much as one Volt. These nega­tive spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con­nect a schottky diode from V
connected to V

, anode to VSS). Schottky diode

CC

to VSS (cathode

CC

1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.

Figure 11. Supply Voltage Protection

V

CC

V

CC

0.1µF DEVICE

V

SS

AI02169

12/18

Table 12. Ordering Information Scheme

Example: M48T35Y -70 MH 1 TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

(1)

35

= VCC = 4.75V to 5.5V; V

35Y = V

= 4.5V to 5.5V; V

CC

Speed

-70 = 70ns

Package

PC = PCDIP28

(2)

MH

= SOH28

Temperature Range

1 = 0 to 70 °C

(3)

6

= –40 to 85 °C

= 4.5V to 5.5V

PFD

= 4.2V to 4.5V

PFD

M48T35, M48T35Y

Shipping Method for SOIC

blank = Tubes
TR = Tape & Reel

Note: 1. The M48T35 part is off ered with the PCDIP28 ( i.e. CAPHAT) package on l y.

2. The S OIC package (SOH28) req ui res the battery package (SNAPHAT ) which is ordered separately unde r the part number
"M4TXX-BR12SH1" in pl astic tube or " M 4T XX-BR12SH1TR" in Tape & Reel for m.

3. Avail able in SOIC package only.

Caution: Do not place the SNAPHAT battery package "M4TXX-BR12SH1" in conductive foam since will drain the lithium button-cell bat-

tery.

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the ST Sales Office nearest to you.

Table 13. Revision History

Date Revision Details

November 1999 First Issue

t

02/07/00

Description changed (Table 7)

DR

13/18

M48T35, M48T35Y

Table 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data

Symb

Typ Min Max Typ M in Max

A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012

D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722

e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430

eA 15.24 16.0 0 0.600 0.630

L 3.05 3.81 0.120 0.150

N 28 28

mm inches

Figure 12. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline

A2

A1AL

B1 B e1

eA

e3

D

N

E

1

Drawing is not to scale.

C

PCDIP

14/18

M48T35, M48T35Y

Table 15. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT,
Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 1.27 – – 0.050 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N 28 28

CP 0.10 0.004

mm inches

Figure 13. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline

A2

A

C

Be

eB

CP

D

N

E

H

LA1 α

1

SOH-A

Drawing is not to scale.

15/18

M48T35, M48T35Y

Table 16. M4T28-BR12S H SNAPHAT Hous ing for 48 mAh Bat tery & Cryst al, Package Mechanical Da ta

Symb

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015

B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

mm inches

Figure 14. M4T28-BR12SH SNAPHA T Hou sing for 48 mAh Battery & Crystal, Package Outline

A2

A3

L

eA

D

A1

A

B

eB

E

SHTK

Drawing is not to scale.

16/18

M48T35, M48T35Y

Table 17. M4T28-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015

B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

mm inches

Figure 15. M4T28-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline

A2

A3

L

eA

D

A1

A

B

eB

E

SHTK

Drawing is not to scale.

17/18

M48T35, M48T35Y

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18/18