SGS Thomson Microelectronics M29F100B, M29F100T Datasheet

1 Mbit (128Kb x8 or 64Kb x16, Boot Block)

5V ± 10% SUPPLYVOLTAGEfor PROGRAM, ERASEand READOPERATIONS

FASTACCESSTIME: 70ns FASTPROGRAMMING TIME –10µs by Byte / 16µs by Word typical PROGRAM/ERASE CONTROLLER(P/E.C.) – Program Byte-by-Byteor Word-by-Word – StatusRegister bits and Ready/Busy Output MEMORYBLOCKS – Boot Block (Top or Bottom location) – Parameterand Main blocks BLOCK, MULTI-BLOCKand CHIPERASE MULTI-BLOCKPROTECTION/TEMPORARY

UNPROTECTION MODES ERASESUSPEND and RESUMEMODES – Read and Program anotherBlockduring

Erase Suspend LOW POWER CONSUMPTION – Stand-byand Automatic Stand-by 100,000 PROGRAM/ERASECYCLESper

BLOCK 20 YEARSDATARETENTION – Defectivity below 1ppm/year ELECTRONICSIGNATURE – ManufacturerCode: 0020h – Device Code, M29F100T:00D0h – Device Code, M29F100B:00D1h

DESCRIPTION

The M29F100 is a non-volatile memory that may beerasedelectricallyat theblock or chiplevel and programmedin-systemona Byte-by-Byteor Wordby-Word basis using only a single 5V V For Program and Erase operations the necessary high voltages are generatedinternally. The device can also be programmed in standard programmers.

Thearraymatrixorganisationallowseach blockto be erased and reprogrammed without affecting otherblocks. Blockscan be protectedagainst programing and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over100,000 cycles.

supply.

M29F100T

M29F100B

Single Supply Flash Memory

12 x 20 mm

Figure1. LogicDiagram

A0-A15

M29F100T M29F100B

SO44 (M)TSOP48 (N)

DQ0-DQ14

DQ15A–1 BYTE RB

AI01974

July 1998 1/30

M29F100T, M29F100B

Figure2A. TSOPPin Connections

A15

1 A14 A13 A12 A11 A10 DQ14

A8 NC NC

W RP NC NC RB NC NC

A7 A6 A5 A4 A3 A2 A1

M29F100T

M29F100B

(Normal)

24 25

37 36

AI01975

NC BYTE V

DQ15A–1 DQ7

DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G V

E A0

Figure2B. TSOPReverse PinConnections

BYTE

DQ15A–1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4 V

DQ11

DQ3

DQ10

DQ2 DQ9 DQ1 DQ8 DQ0

M29F100T

M29F100B

(Reverse)

24 25

AI01976

37 36

A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB NC NC A7 A6 A5 A4 A3 A2 A1

Warning: NC = Not Connected. Warning: NC = Not Connected.

Figure2C. SO Pin Connections

Table 1. Signal Names

A0-A15 Address Inputs

NC RP

1 2 3

NC A8

4 5

A5 A4

M29F100T M29F100B

12 13 14 15 16 17DQ1 18 19 20 21

DQ0

DQ8

DQ9

DQ10

DQ3

DQ11

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 2322

AI01977

WRB

A9 A10 A11 A12 A13 A14 A15 NC BYTE V

DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5DQ2 DQ12 DQ4 V

DQ0-DQ7 Data Input/Outputs, Command Inputs DQ8-DQ14 Data Input/Outputs DQ15A–1 Data Input/Outputor AddressInput E Chip Enable G Output Enable W Write Enable RP Reset / Block TemporaryUnprotect RB Ready/Busy Output BYTE Byte/Word Organisation V

Supply Voltage Ground

Warning: NC = Not Connected.

2/30

M29F100T, M29F100B

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(2)

(A9, E, G, RP)

Notes: 1. Except for therating ”Operating Temperature Range”, stressesabove those listedin theTable ”AbsoluteMaximum Ratings”

may cause permanent damage to thedevice. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operatingsections of this specification is not implied.Exposure to Absolute Maximum Rating conditions for extended periods may affectdevice reliability.Refer also tothe STMicroelectronics SURE Programand other relevant quality documents.

2. Minimum Voltagemay undershoot to –2V during transitionand for less than 20ns.

3. Depends on range.

Ambient Operating Temperature Temperature Under Bias –50 to 125 Storage Temperature –65 to 150 Input or Output Voltages –0.6to 7 V Supply Voltage –0.6to 7 V

(2)

A9, E, G, RP Voltage –0.6to 13.5 V

DESCRIPTION(Cont’d) Instructionsfor Read/Reset, Auto Select for read-

ing the Electronic Signature or Block Protection status,Programming,BlockandChipErase,Erase Suspend and Resume are written to the device in cyclesofcommandstoa CommandInterfaceusing standardmicroprocessorwrite timings.

Thedevice is offered in TSOP48(12 x 20mm)and SO44packages.Both normal and reversepinouts are available for the TSOP48package.

Organisation

The M29F100 is organisedas 128Kb x8 or 64Kb x16 bits selectable by the BYTE signal. When BYTE is Low the Byte-wide x8 organisation is selectedand the address lines are DQ15A–1and A0-A15. The Data Input/Outputsignal DQ15A–1 actsas addresslineA–1which selectsthe loweror upper Byte of the memory word for output on DQ0-DQ7,DQ8-DQ14remainat Highimpedance. WhenBYTEis Highthe memoryusesthe address inputs A0-A15 and the Data Input/Outputs DQ0DQ15.Memory controlisprovided by ChipEnable E, OutputEnable G andWrite EnableW inputs.

AReset/BlockTemporaryUnprotection RPtri-level input providesa hardware reset whenpulled Low, andwhenheldHigh(atV

)temporarily unprotects

blocks previously protected allowing them to be programedanderased.EraseandProgramoperations are controlled by an internal Program/Erase Controller(P/E.C.).StatusRegister data outputon DQ7providesa Data Pollingsignal, and DQ6and DQ2provideTogglesignals to indicatethe stateof

(1)

(3)

–40 to 125

the P/E.C operations. A Ready/Busy RB output indicatesthe completionof theinternalalgorithms.

MemoryBlocks

Thedevicesfeatureasymmetrically blocked architectureprovidingsystemmemory integration.Both M29F100Tand M29F100B devices have an array of 5 blocks, one Boot Block of 16 KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, one Main Block of 32 KBytes or 16 KWordsand one Main Blocks of 64 KBytesor 32 KWords.TheM29F100Thas the Boot Blockat the top of the memory add ress space and the M29F100B locates the Boot Block starting at the bottom. The memory maps are showed in Figure

3. Each block can be erased separately,any combination of blocks can be specified for multi-block eraseor the entire chipmay beerased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any blocknot being ersased, and then resumed.

Block protection provides additional data security. Each block can be separately protected or unprotectedagainst Program or Erase on programming equipment.All previouslyprotected blocks can be temporarilyunprotectedin the application.

Bus Operations

The following operations can be performed using theappropriatebus cycles:Read(Array,Electronic Signature, Block Protection Status), Write command, Output Disable,Standby,Reset, Block Protection, Unprotection, Protection Verify, Unprotection Verify and Block Temporary Unprotection.See Tables4 and 5.

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M29F100T, M29F100B

Figure3. MemoryMap and Block Address Table(x8)

M29F100B

64K MAIN BLOCK

32K MAIN BLOCK

8K PARAMETER BLOCK

16K BOOT BLOCK

AI01978

1FFFFh 1C000h

1BFFFh

1A000h

19FFFh

18000h

17FFFh

10000h

0FFFFh

00000h

M29F100T

16K BOOTBLOCK

8K PARAMETER BLOCK

32K MAIN BLOCK

64K MAIN BLOCK

1FFFFh

10000h

0FFFFh

08000h

07FFFh

06000h

05FFFh

04000h

03FFFh

00000h

Table 3A. M29F100T Block AddressTable

Address Range (x8) Address Range (x16) A15 A14 A13 A12

00000h-0FFFFh 0000h-7FFFh 0 X X X 10000h-17FFFh 8000h-BFFFh 1 0 X X

18000h-19FFFh C000h-CFFFh 1 1 0 0 1A000h-1BFFFh D000h-DFFFh 1 1 0 1 1C000h-1FFFFh E000h-FFFFh 1 1 1 X

Table 3B. M29F100B BlockAddress Table

Address Range (x8) Address Range (x16) A15 A14 A13 A12

00000h-03FFFh 0000h-1FFFh 0 0 0 X

04000h-05FFFh 2000h-2FFFh 0 0 1 0

06000h-07FFFh 3000h-3FFFh 0 0 1 1

08000h-0FFFFh 4000h-7FFFh 0 1 X X

10000h-1FFFFh 8000h-FFFFh 1 X X X

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M29F100T, M29F100B

CommandInterface

Instructions,made up of commands written in cycles,can be givento theProgram/EraseController through a Command Interface (C.I.). For added dataprotection,program or erase executionstarts after4 or 6 cycles.The first,second,fourthandfifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Program/Erase Controller instructions. The ’Command’itself and its confirmation,when applicable, are given on the third, fourth or sixth cycles. Any incorrectcommand or any improper command sequencewill resetthe deviceto ReadArray mode.

Instructions

Seven instructions are defined to perform Read Array, Auto Select(to readtheElectronicSignature or BlockProtectionStatus),Program,Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations.The Status Register Data Polling, Toggle, Error bits and the RB output may be read at anytime, duringprogramming or erase,to monitor the progress of the operation.

Instructionsare composedof up to six cycles.The first two cycles input a Coded sequence to the CommandInterfacewhich iscommontoall instructions (see Table 8). The third cycle inputs the instruction set-up command. Subsequent cycles outputthe addressed data,ElectronicSignatureor Block Protection Status for Read operations. In orderto giveadditionaldataprotection,the instructionsfor Programand Blockor Chip Erase require furthercommandinputs.ForaPrograminstruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a furtherCoded sequence before the Eraseconfirm commandon thesixth cycle. Erasure of a memory blockmaybesuspended,inordertoreaddatafrom anotherblock or to programdata in anotherblock, and then resumed.

When power is first applied or if V

, the command interface is reset to Read

LKO

falls below

Array.

SIGNALDESCRIPTIONS

See Figure 1 and Table1. AddressInputs (A0-A15).The addressinputs for

thememoryarrayarelatchedduringa write operation on the falling edge of Chip Enable E or Write EnableW. In Word-wide organisationthe address lines are A0-A15, in Byte-wide organisation DQ15A–1acts as an additionalLSB address line.

WhenA9 is raisedto V

, eithera Read Electronic

Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combinationof levelson A0,A1,A6, A12 and A15.

Data Input/Outputs (DQ0-DQ7). These Inputs/Outputsare used in theByte-wide and Wordwide organisat ions. The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status registerData Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Errorbit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputsaredisabledandwhenRPis at aLowlevel.

Data Input/Outputs (DQ8-DQ14and DQ15A–1).

These Inputs/Outputsare additionally used in the Word-wideorganisation.WhenBYTEis HighDQ8DQ14 and DQ15A–1 act as the MSB of the Data Inputor Output,functioningas describedfor DQ0DQ7 above, and DQ8-DQ15 are ’don’t care’ for commandinputs or statusoutputs. When BYTEis Low,DQ8-DQ14are highimpedance,DQ15A–1is theAddress A–1 input.

Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders andsenseamplifiers.E Highdeselectsthememory andreducesthepower consumptiontothestandby level. E can also be used to control writing to the commandregister and to the memory array,while Wremainsat a low level.TheChip Enablemustbe forcedto V

duringthe Block Unprotectionopera-

tion. OutputEnable (G). TheOutput Enable gates the

outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to V

level during

BlockProtectionand Unprotection operations. WriteEnable(W). This inputcontrols writingto the

CommandRegisterand Addressand Datalatches. Byte/Word Organization Select (BYTE). The

BYTEinput selects the outputconfigurationfor the device: Byte-wide (x8) mode or Word-wide (x16) mode. When BYTEis Low,the Byte-widemode is selectedand the data is read and programmedon DQ0-DQ7. In this mode, DQ8-DQ14 are at high impedance and DQ15A–1 is the LSB address. When BYTE is High, the Word-wide mode is selected and the data is read and programmed on DQ0-DQ15.

5/30

M29F100T, M29F100B

Ready/Busy Output (RB). Ready/Busy is an

open-drainoutputandgivestheinternalstateof the P/E.C. of the device.When RB is Low, the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructionsexcept the Erase Suspendinstruction. WhenRBis High,the deviceis readyforany Read, Program or Erase operation. The RB will also be Highwhen the memoryis putin EraseSuspendor Standbymodes.

Reset/Block Temporary Unprotect Input (RP).

The RP Input provides hardware reset and protected block(s) temporary unprotection functions. Reset of the memory is acheived by pullingRP to

for at least 500ns. When the reset pulse is

given,if thememoryis in Read or Standbymodes, it will be availablefor new operationsin 50nsafter the rising edge of RP. If the memory is in Erase, Erase Suspend or Program modes the reset will take 10µs during which the RB signal will be held

.Theendof thememoryresetwillbeindicated

atV

by the rising edge of RB. A hardware reset during anEraseor Programoperationwillcorruptthe data beingprogrammedor the sector(s)being erased.

Temporary block unprotection is made by holding RP at V

. In this condition previously protected

blockscan be programmed or erased. The transitionof RP fromV When RP is returned from V

toVIDmust slowerthan500ns.

to VIHall blocks

temporarilyunprotectedwill be again protected.

Supply Voltage. The power supply for all

operations(Read, Programand Erase).

Ground. VSSis the reference for all voltage

measurements.

DEVICEOPERATIONS

See Tables 4, 5 and 6. Read. Read operations are used to output the

contents of the Memory Array,the ElectronicSignature,theStatusRegisteror the BlockProtection Status.Both Chip Enable E and Output Enable G must be low in order to read the output of the memory.

Write.Writeoperationsareused to giveInstruction Commandsto thememoryor tolatch input datato beprogrammed.Awrite operationisinitiatedwhen Chip Enable E is Low and Write Enable W is Low withOutput Enable G High.Addressesare latched onthe fallingedge ofWorEwhicheveroccurslast. CommandsandInputDataarelatchedontherising edgeof W or E whichever occurs first.

OutputDisable.The dataoutputsare highimpedancewhen the OutputEnableG is High with Write EnableW High.

Standby. The memory is in standby when Chip EnableE is High and theP/E.C.is idle. Thepower consumption is reduced to the standbylevel and the outputs are high impedance, independent of the Output Enable G or WriteEnable W inputs.

AutomaticStandby. After 150ns of bus inactivity and when CMOS levels are drivingthe addresses, the chip automatically enters a pseudo-standby modewhere consumptionis reducedto the CMOS standbyvalue, while outputsstill drive the bus.

ElectronicSignature. Two codes identifying the manufacturer andthe devicecan bereadfrom the memory. The manufacturer’s code for STMicroelectronicsis20h,the devicecodeis D0hfor the M29F100T(Top Boot) and D1h forthe M29F100B (Bottom Boot). These codes allow programming equipment or applicationsto automatically match their interface to the characteristics of the M29F100.The ElectronicSignatureis output by a Read operationwhen the voltageapplied to A9 is

and addressinput A1 is Low.The manufac-

at V

turer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7.

TheElectronic Signaturecan alsobe read, without raisingA9to V

, bygivingthe memorythe Instruc-

tion AS. If the Byte-wide configuration is selected thecodesare output onDQ0-DQ7withDQ8-DQ14 at High impedance; if the Word-wide configuration isselectedthe codes are output onDQ0-DQ7with DQ8-DQ15at 00h.

Block Protection. Each block can be separately protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or eraseoperations.Thismodeis activatedwhenboth A9 and G are raised to V

and an address in the

blockis appliedon A12-A15.The BlockProtection algorithmis showninFigure14. Blockprotectionis initiatedon the edge of W falling to V a delayof 100µs,the edge of W rising to V

. Thenafter

ends theprotectionoperations.Blockprotectionverifyis achievedby bringingG, E, A0andA6toV

, while W is atVIHandA9atVID. Underthese

toV

andA1

conditions,reading the data outputwill yield 01h if the block defined by the inputs on A12-A15 is protected.Any attempt to programor erase a protectedblock will be ignored by the device.

6/30

M29F100T, M29F100B

Table 4. User Bus Operations

(1)

Operation E G W RP BYTE A0 A1 A6 A9 A12 A15

Read Word V

Read Byte V

Write Word V

Write Byte V Output Disable V

Standby V

ILVIL

ILVIH

ILVIH IH

Reset X X X V Block

Protection Blocks

Unprotection Block

Protection Verify

Block Unprotection Verify

Block Temporary Unprotection

Notes: 1. X = V

(2,4) V

(2,4)

ILVIDVIL

(4)VIDVIDVIL

VILV

XX X V

or V

2. Block Address must be given on A12-A15 bits.

3. See Table6.

4. Operation performed onprogramming equipment.

A0 A1 A6 A9 A12 A15

A0 A1 A6 A9 A12 A15 Data Input Data Input

A0 A1 A6 A9 A12 A15

X X X X X X X Hi-Z Hi-Z Hi-Z

XXVIHX X X X X X X Hi-Z Hi-Z Hi-Z

X X X X X X X Hi-Z Hi-Z Hi-Z

Pulse V

XXXXVIDXX X X X

XXXXVIDVIHV

XVILVIHVILVIDA12 A15 X X

XVILVIHVIHVIDA12 A15 X X

X XXXXXX X X X

DQ15

A–1

Data

Output

Address

Input

Address

Input

XXX

DQ8-

DQ14

Data

Output

Hi-Z

DQ0-DQ7

Data

Output

Data

Output

Data Input

Block

Protect

(3)

Status

Block

Protect

(3)

Status

Table 5. Read ElectronicSignature (followingAS instructionor with A9 = VID)

Org. Code Device E G W BYTE A0 A1

Word-

wide

Manufact.

Code

Device

Code

Manufact.

Code

M29F100T V M29F100B V

VILV

VILVILDon’t Care 0 00h 20h

VILVILDon’t Care

Byte-

wide

Device

M29F100T V

VILV

Code

M29F100B V

VILV

Other

Addresses

VILDon’t Care 0 00h D0h VILDon’t Care 0 00h D1h

VILDon’t Care

DQ15

A–1

Don’t Care

Table 6. Read Block Protectionwith AS Instruction

Code E G W A0 A1 A12 - A15

Protected Block V Unprotected Block V

V V

Block Address Don’t Care 01h

Block Address Don’t Care 00h

Addresses

Other

DQ8 DQ14

DQ0 -

DQ7

Hi-Z 20h

Hi-Z D0h

Hi-Z D1h

DQ0 - DQ7

7/30

M29F100T, M29F100B

Block Temporary Unprotection. Any previously

protectedblock can be temporarilyunprotectedin orderto changestoreddata.Thetemporaryunprotection mode is activated by bringing RP to V

During the temporary unprotection mode the previously protected blocks are unprotected. A block can be selected and data can be modified by executingtheEraseorPrograminstructionwiththe RPsignal heldat V

. When RPis returnedto VIH,

all the previously protected blocks are again protected.

Block Unprotection. All protectedblocks can be unprotected on programming equipmentto allow updating of bit contents. All blocks must first be protectedbefore the unprotectionoperation.Block unprotectionis activated when A9, G and E are at

and A12, A15 at VIH. The Block Unprotection

algorithm is shown in Figure 15. Unprotection is initiatedbytheedgeofW fallingtoV

.Aftera delay

of 10ms, the unprotection operation will end. Unprotectionverifyis achievedby bringingGand E to

whileA0 is at VIL, A6 and A1 are atVIHandA9

remains at V

. In these conditions, reading the

outputdata willyield 00h if theblock definedby the inputsA12-A15hasbeen succesfullyunprotected. Eachblock mustbeseparatelyverified bygivingits address in order to ensure that it has beenunprotected.

INSTRUCTIONS AND COMMANDS

The Command Interface latches commands written to the memory. Instructionsare madeup from one or more commands to perform Read Memory Array, ReadElectronicSignature,ReadBlock Protection, Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made of address and data sequences. The instructionsrequirefrom 1 to 6 cycles,thefirstor first threeof whichare alwayswrite operationsusedto initiatethe instruction. They are followed by either furtherwrite cycles toconfirmthe first command or executethe commandimmediately. Commandsequencing must be followed exactly. Any invalid combinationof commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Instructionsare initialised by twoinitial Coded cycleswhich unlockthe CommandInterface.In addition, for Erase, instruction confirmation is again precededby the two Coded cycles.

Status RegisterBits

P/E.C.statusis indicatedduring executionbyData Polling on DQ7, detectionof Toggleon DQ6 and DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase commandexecutionwill automaticallyoutputthesefive StatusRegisterbits.The P/E.C.automaticallysets

bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked. See Tables9 and 10.

Data Polling Bit (DQ7). When Programmingoperations are in progress, this bit outputs the complement of the bit being programmed on DQ7. DuringEraseoperation,it outputsa ’0’.After completionof the operation,DQ7will outputthe bit last programmedor a ’1’ after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programmingor after the sixth W pulse for erase. It must be performedat the address being programmedor at an address within the block being erased. If all the blocksselectedfor erasureare protected,DQ7 will beset to ’0’for about100µs, andthenreturnto the previous addressed memorydata value. See Figure11forthe Data Polling flowchart and Figure10 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from ’0’ to ’1’ at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend mode, DQ7 will output ’1’ if the read is attempted onablockbeingerasedandthedatavalueon other blocks. During Program operation in Erase SuspendMode, DQ7 will have the same behaviouras in the normal program execution outside of the suspendmode.

Table 7. Commands

Hex Code Command

00h Invalid/Reserved 10h Chip Erase Confirm 20h Reserved 30h Block Erase Resume/Confirm 80h Set-up Erase

90h

A0h Program B0h EraseSuspend F0h Read Array/Reset

Read Electronic Signature/ Block Protection Status

8/30

M29F100T, M29F100B

Table 8. Instructions

(1)

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

(2,4)

Read/Reset MemoryArray

(3,7)

Addr.

Data F0h

Byte AAAAh 5555h AAAAh

(3,7)

Addr.

Word 5555h 2AAAh 5555h

Read Memory Array until a new write cycle is initiated.

ReadMemory Array until a new write cycle isinitiated.

Data AAh 55h F0h

(4)

AutoSelect 3+

Addr.

(3,7)

Word 5555h 2AAAh 5555h

ReadElectronic Signatureor Block Protection Status until a new writecycle is initiated. See Note 5 and6.

Byte AAAAh 5555h AAAAh

Data AAh 55h 90h

PG Program 4

BE BlockErase 6

Byte AAAAh 5555h AAAAh

(3,7)

Addr.

Word 5555h 2AAAh 5555h

Data AAh 55h A0h

Byte AAAAh 5555h AAAAh AAAAh 5555h

(3,7)

Addr.

Word 5555h 2AAAh 5555h 5555h 2AAAh

Program

Address

Program

Data

Read Data Polling or ToggleBit until Program completes.

Block

Address

Additional

Block

Data AAh 55h 80h AAh 55h 30h 30h

CE Chip Erase 6

Addr.

Word 5555h 2AAAh 5555h 5555h 2AAAh 5555h

Byte AAAAh 5555h AAAAh AAAAh 5555h AAAAh

(3,7)

Data AAh 55h 80h AAh 55h 10h

(3,7)

Notes: 1. Commands not interpreted in this table will default to read array mode.

Suspend

Erase

Resume

2. Await of t before starting any new operation (see Table14 and Figure 9).

3. X= Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations.Any number of readcycles can occur after the command cycles.

5. SignatureAddress bits A0,A1 at V Device code.

6. Block Protection Address: A0 at V

7. ForCoded cycles address inputs A15is don’t care.

8. Optional,additional Blocks addresses must be entered within the erasetimeout delay after last writeentry, timeout status can be verified through DQ3 value (see EraseTimerBit DQ3 description). When full command is entered, read Data Polling or Togglebit until Erase is completed or suspended.

9. Read Data Polling, Togglebits or RB until Erase completes.

10.During Erase Suspend, Read and Data Programfunctions are allowed in blocks not being erased.

is necessary after a Read/Reset command if the memory was in an Erase or Program mode

PLYH

Erase

(10)

Addr.

Data B0h

(3,7)

Addr.

Data 30h

will output Manufacturer code (20h). Address bits A0 at VIHandA1 at VILwill output

,A1atVIHand A12-A15 within the Block will output the Block Protection status.

Read until Togglestops, then read all the data needed from any Block(s) not being erased then Resume Erase.

Read Data Polling or ToggleBits until Erase completes or Erase is suspended another time

(8)

Note 9

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